2011-09-11 11:33:40 +02:00
|
|
|
/*
|
|
|
|
|
* Sparc CPU init helpers
|
|
|
|
|
*
|
|
|
|
|
* Copyright (c) 2003-2005 Fabrice Bellard
|
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|
*
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|
* This library is free software; you can redistribute it and/or
|
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|
|
* modify it under the terms of the GNU Lesser General Public
|
|
|
|
|
* License as published by the Free Software Foundation; either
|
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|
|
|
* version 2 of the License, or (at your option) any later version.
|
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|
|
*
|
|
|
|
|
* This library is distributed in the hope that it will be useful,
|
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|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
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|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|
|
|
|
* Lesser General Public License for more details.
|
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|
*
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|
|
* You should have received a copy of the GNU Lesser General Public
|
|
|
|
|
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
|
|
|
|
*/
|
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|
|
2016-01-26 19:16:59 +01:00
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|
|
#include "qemu/osdep.h"
|
include/qemu/osdep.h: Don't include qapi/error.h
Commit 57cb38b included qapi/error.h into qemu/osdep.h to get the
Error typedef. Since then, we've moved to include qemu/osdep.h
everywhere. Its file comment explains: "To avoid getting into
possible circular include dependencies, this file should not include
any other QEMU headers, with the exceptions of config-host.h,
compiler.h, os-posix.h and os-win32.h, all of which are doing a
similar job to this file and are under similar constraints."
qapi/error.h doesn't do a similar job, and it doesn't adhere to
similar constraints: it includes qapi-types.h. That's in excess of
100KiB of crap most .c files don't actually need.
Add the typedef to qemu/typedefs.h, and include that instead of
qapi/error.h. Include qapi/error.h in .c files that need it and don't
get it now. Include qapi-types.h in qom/object.h for uint16List.
Update scripts/clean-includes accordingly. Update it further to match
reality: replace config.h by config-target.h, add sysemu/os-posix.h,
sysemu/os-win32.h. Update the list of includes in the qemu/osdep.h
comment quoted above similarly.
This reduces the number of objects depending on qapi/error.h from "all
of them" to less than a third. Unfortunately, the number depending on
qapi-types.h shrinks only a little. More work is needed for that one.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
[Fix compilation without the spice devel packages. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-03-14 09:01:28 +01:00
|
|
|
#include "qapi/error.h"
|
2011-09-11 11:33:40 +02:00
|
|
|
#include "cpu.h"
|
2019-05-23 16:35:07 +02:00
|
|
|
#include "qemu/module.h"
|
2019-04-17 21:17:57 +02:00
|
|
|
#include "qemu/qemu-print.h"
|
2016-03-15 13:18:37 +01:00
|
|
|
#include "exec/exec-all.h"
|
2017-08-24 18:31:27 +02:00
|
|
|
#include "hw/qdev-properties.h"
|
|
|
|
|
#include "qapi/visitor.h"
|
2011-09-11 11:33:40 +02:00
|
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|
|
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|
|
//#define DEBUG_FEATURES
|
|
|
|
|
|
cpu: Use DeviceClass reset instead of a special CPUClass reset
The CPUClass has a 'reset' method. This is a legacy from when
TYPE_CPU used not to inherit from TYPE_DEVICE. We don't need it any
more, as we can simply use the TYPE_DEVICE reset. The 'cpu_reset()'
function is kept as the API which most places use to reset a CPU; it
is now a wrapper which calls device_cold_reset() and then the
tracepoint function.
This change should not cause CPU objects to be reset more often
than they are at the moment, because:
* nobody is directly calling device_cold_reset() or
qdev_reset_all() on CPU objects
* no CPU object is on a qbus, so they will not be reset either
by somebody calling qbus_reset_all()/bus_cold_reset(), or
by the main "reset sysbus and everything in the qbus tree"
reset that most devices are reset by
Note that this does not change the need for each machine or whatever
to use qemu_register_reset() to arrange to call cpu_reset() -- that
is necessary because CPU objects are not on any qbus, so they don't
get reset when the qbus tree rooted at the sysbus bus is reset, and
this isn't being changed here.
All the changes to the files under target/ were made using the
included Coccinelle script, except:
(1) the deletion of the now-inaccurate and not terribly useful
"CPUClass::reset" comments was done with a perl one-liner afterwards:
perl -n -i -e '/ CPUClass::reset/ or print' target/*/*.c
(2) this bit of the s390 change was done by hand, because the
Coccinelle script is not sophisticated enough to handle the
parent_reset call being inside another function:
| @@ -96,8 +96,9 @@ static void s390_cpu_reset(CPUState *s, cpu_reset_type type)
| S390CPU *cpu = S390_CPU(s);
| S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);
| CPUS390XState *env = &cpu->env;
|+ DeviceState *dev = DEVICE(s);
|
|- scc->parent_reset(s);
|+ scc->parent_reset(dev);
| cpu->env.sigp_order = 0;
| s390_cpu_set_state(S390_CPU_STATE_STOPPED, cpu);
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20200303100511.5498-1-peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-03-03 11:05:11 +01:00
|
|
|
static void sparc_cpu_reset(DeviceState *dev)
|
2012-04-05 01:29:40 +02:00
|
|
|
{
|
cpu: Use DeviceClass reset instead of a special CPUClass reset
The CPUClass has a 'reset' method. This is a legacy from when
TYPE_CPU used not to inherit from TYPE_DEVICE. We don't need it any
more, as we can simply use the TYPE_DEVICE reset. The 'cpu_reset()'
function is kept as the API which most places use to reset a CPU; it
is now a wrapper which calls device_cold_reset() and then the
tracepoint function.
This change should not cause CPU objects to be reset more often
than they are at the moment, because:
* nobody is directly calling device_cold_reset() or
qdev_reset_all() on CPU objects
* no CPU object is on a qbus, so they will not be reset either
by somebody calling qbus_reset_all()/bus_cold_reset(), or
by the main "reset sysbus and everything in the qbus tree"
reset that most devices are reset by
Note that this does not change the need for each machine or whatever
to use qemu_register_reset() to arrange to call cpu_reset() -- that
is necessary because CPU objects are not on any qbus, so they don't
get reset when the qbus tree rooted at the sysbus bus is reset, and
this isn't being changed here.
All the changes to the files under target/ were made using the
included Coccinelle script, except:
(1) the deletion of the now-inaccurate and not terribly useful
"CPUClass::reset" comments was done with a perl one-liner afterwards:
perl -n -i -e '/ CPUClass::reset/ or print' target/*/*.c
(2) this bit of the s390 change was done by hand, because the
Coccinelle script is not sophisticated enough to handle the
parent_reset call being inside another function:
| @@ -96,8 +96,9 @@ static void s390_cpu_reset(CPUState *s, cpu_reset_type type)
| S390CPU *cpu = S390_CPU(s);
| S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);
| CPUS390XState *env = &cpu->env;
|+ DeviceState *dev = DEVICE(s);
|
|- scc->parent_reset(s);
|+ scc->parent_reset(dev);
| cpu->env.sigp_order = 0;
| s390_cpu_set_state(S390_CPU_STATE_STOPPED, cpu);
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20200303100511.5498-1-peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-03-03 11:05:11 +01:00
|
|
|
CPUState *s = CPU(dev);
|
2012-04-05 01:29:40 +02:00
|
|
|
SPARCCPU *cpu = SPARC_CPU(s);
|
|
|
|
|
SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(cpu);
|
|
|
|
|
CPUSPARCState *env = &cpu->env;
|
|
|
|
|
|
cpu: Use DeviceClass reset instead of a special CPUClass reset
The CPUClass has a 'reset' method. This is a legacy from when
TYPE_CPU used not to inherit from TYPE_DEVICE. We don't need it any
more, as we can simply use the TYPE_DEVICE reset. The 'cpu_reset()'
function is kept as the API which most places use to reset a CPU; it
is now a wrapper which calls device_cold_reset() and then the
tracepoint function.
This change should not cause CPU objects to be reset more often
than they are at the moment, because:
* nobody is directly calling device_cold_reset() or
qdev_reset_all() on CPU objects
* no CPU object is on a qbus, so they will not be reset either
by somebody calling qbus_reset_all()/bus_cold_reset(), or
by the main "reset sysbus and everything in the qbus tree"
reset that most devices are reset by
Note that this does not change the need for each machine or whatever
to use qemu_register_reset() to arrange to call cpu_reset() -- that
is necessary because CPU objects are not on any qbus, so they don't
get reset when the qbus tree rooted at the sysbus bus is reset, and
this isn't being changed here.
All the changes to the files under target/ were made using the
included Coccinelle script, except:
(1) the deletion of the now-inaccurate and not terribly useful
"CPUClass::reset" comments was done with a perl one-liner afterwards:
perl -n -i -e '/ CPUClass::reset/ or print' target/*/*.c
(2) this bit of the s390 change was done by hand, because the
Coccinelle script is not sophisticated enough to handle the
parent_reset call being inside another function:
| @@ -96,8 +96,9 @@ static void s390_cpu_reset(CPUState *s, cpu_reset_type type)
| S390CPU *cpu = S390_CPU(s);
| S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);
| CPUS390XState *env = &cpu->env;
|+ DeviceState *dev = DEVICE(s);
|
|- scc->parent_reset(s);
|+ scc->parent_reset(dev);
| cpu->env.sigp_order = 0;
| s390_cpu_set_state(S390_CPU_STATE_STOPPED, cpu);
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20200303100511.5498-1-peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-03-03 11:05:11 +01:00
|
|
|
scc->parent_reset(dev);
|
2012-04-05 01:29:40 +02:00
|
|
|
|
2016-11-14 15:19:17 +01:00
|
|
|
memset(env, 0, offsetof(CPUSPARCState, end_reset_fields));
|
2011-09-11 11:33:40 +02:00
|
|
|
env->cwp = 0;
|
|
|
|
|
#ifndef TARGET_SPARC64
|
|
|
|
|
env->wim = 1;
|
|
|
|
|
#endif
|
|
|
|
|
env->regwptr = env->regbase + (env->cwp * 16);
|
|
|
|
|
CC_OP = CC_OP_FLAGS;
|
|
|
|
|
#if defined(CONFIG_USER_ONLY)
|
|
|
|
|
#ifdef TARGET_SPARC64
|
|
|
|
|
env->cleanwin = env->nwindows - 2;
|
|
|
|
|
env->cansave = env->nwindows - 2;
|
|
|
|
|
env->pstate = PS_RMO | PS_PEF | PS_IE;
|
|
|
|
|
env->asi = 0x82; /* Primary no-fault */
|
|
|
|
|
#endif
|
|
|
|
|
#else
|
|
|
|
|
#if !defined(TARGET_SPARC64)
|
|
|
|
|
env->psret = 0;
|
|
|
|
|
env->psrs = 1;
|
|
|
|
|
env->psrps = 1;
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef TARGET_SPARC64
|
2016-06-07 18:34:49 +02:00
|
|
|
env->pstate = PS_PRIV | PS_RED | PS_PEF;
|
|
|
|
|
if (!cpu_has_hypervisor(env)) {
|
|
|
|
|
env->pstate |= PS_AG;
|
|
|
|
|
}
|
2011-09-11 11:33:40 +02:00
|
|
|
env->hpstate = cpu_has_hypervisor(env) ? HS_PRIV : 0;
|
|
|
|
|
env->tl = env->maxtl;
|
2016-06-07 18:34:49 +02:00
|
|
|
env->gl = 2;
|
2011-09-11 11:33:40 +02:00
|
|
|
cpu_tsptr(env)->tt = TT_POWER_ON_RESET;
|
|
|
|
|
env->lsu = 0;
|
|
|
|
|
#else
|
|
|
|
|
env->mmuregs[0] &= ~(MMU_E | MMU_NF);
|
2017-08-24 18:31:26 +02:00
|
|
|
env->mmuregs[0] |= env->def.mmu_bm;
|
2011-09-11 11:33:40 +02:00
|
|
|
#endif
|
|
|
|
|
env->pc = 0;
|
|
|
|
|
env->npc = env->pc + 4;
|
|
|
|
|
#endif
|
|
|
|
|
env->cache_control = 0;
|
|
|
|
|
}
|
|
|
|
|
|
2014-09-13 18:45:26 +02:00
|
|
|
static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
|
|
|
|
|
{
|
|
|
|
|
if (interrupt_request & CPU_INTERRUPT_HARD) {
|
|
|
|
|
SPARCCPU *cpu = SPARC_CPU(cs);
|
|
|
|
|
CPUSPARCState *env = &cpu->env;
|
|
|
|
|
|
|
|
|
|
if (cpu_interrupts_enabled(env) && env->interrupt_index > 0) {
|
|
|
|
|
int pil = env->interrupt_index & 0xf;
|
|
|
|
|
int type = env->interrupt_index & 0xf0;
|
|
|
|
|
|
|
|
|
|
if (type != TT_EXTINT || cpu_pil_allowed(env, pil)) {
|
|
|
|
|
cs->exception_index = env->interrupt_index;
|
|
|
|
|
sparc_cpu_do_interrupt(cs);
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
2015-07-12 04:00:01 +02:00
|
|
|
static void cpu_sparc_disas_set_info(CPUState *cpu, disassemble_info *info)
|
|
|
|
|
{
|
|
|
|
|
info->print_insn = print_insn_sparc;
|
|
|
|
|
#ifdef TARGET_SPARC64
|
|
|
|
|
info->mach = bfd_mach_sparc_v9b;
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
2017-08-25 16:47:40 +02:00
|
|
|
static void
|
|
|
|
|
cpu_add_feat_as_prop(const char *typename, const char *name, const char *val)
|
|
|
|
|
{
|
|
|
|
|
GlobalProperty *prop = g_new0(typeof(*prop), 1);
|
|
|
|
|
prop->driver = typename;
|
|
|
|
|
prop->property = g_strdup(name);
|
|
|
|
|
prop->value = g_strdup(val);
|
|
|
|
|
qdev_prop_register_global(prop);
|
|
|
|
|
}
|
2016-06-09 19:11:00 +02:00
|
|
|
|
2017-08-25 16:47:40 +02:00
|
|
|
/* Parse "+feature,-feature,feature=foo" CPU feature string */
|
|
|
|
|
static void sparc_cpu_parse_features(const char *typename, char *features,
|
|
|
|
|
Error **errp)
|
2011-09-11 11:33:40 +02:00
|
|
|
{
|
2017-08-25 16:47:40 +02:00
|
|
|
GList *l, *plus_features = NULL, *minus_features = NULL;
|
|
|
|
|
char *featurestr; /* Single 'key=value" string being parsed */
|
|
|
|
|
static bool cpu_globals_initialized;
|
2011-09-11 11:33:40 +02:00
|
|
|
|
2017-08-25 16:47:40 +02:00
|
|
|
if (cpu_globals_initialized) {
|
|
|
|
|
return;
|
2014-03-04 00:38:58 +01:00
|
|
|
}
|
2017-08-25 16:47:40 +02:00
|
|
|
cpu_globals_initialized = true;
|
2014-03-04 00:38:58 +01:00
|
|
|
|
2017-08-25 16:47:40 +02:00
|
|
|
if (!features) {
|
|
|
|
|
return;
|
|
|
|
|
}
|
2011-09-11 11:33:40 +02:00
|
|
|
|
2017-08-25 16:47:40 +02:00
|
|
|
for (featurestr = strtok(features, ",");
|
|
|
|
|
featurestr;
|
|
|
|
|
featurestr = strtok(NULL, ",")) {
|
|
|
|
|
const char *name;
|
|
|
|
|
const char *val = NULL;
|
|
|
|
|
char *eq = NULL;
|
2017-08-24 18:31:25 +02:00
|
|
|
|
2017-08-25 16:47:40 +02:00
|
|
|
/* Compatibility syntax: */
|
|
|
|
|
if (featurestr[0] == '+') {
|
|
|
|
|
plus_features = g_list_append(plus_features,
|
|
|
|
|
g_strdup(featurestr + 1));
|
|
|
|
|
continue;
|
|
|
|
|
} else if (featurestr[0] == '-') {
|
|
|
|
|
minus_features = g_list_append(minus_features,
|
|
|
|
|
g_strdup(featurestr + 1));
|
|
|
|
|
continue;
|
|
|
|
|
}
|
2011-09-11 11:33:40 +02:00
|
|
|
|
2017-08-25 16:47:40 +02:00
|
|
|
eq = strchr(featurestr, '=');
|
|
|
|
|
name = featurestr;
|
|
|
|
|
if (eq) {
|
|
|
|
|
*eq++ = 0;
|
|
|
|
|
val = eq;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Temporarily, only +feat/-feat will be supported
|
|
|
|
|
* for boolean properties until we remove the
|
|
|
|
|
* minus-overrides-plus semantics and just follow
|
|
|
|
|
* the order options appear on the command-line.
|
|
|
|
|
*
|
|
|
|
|
* TODO: warn if user is relying on minus-override-plus semantics
|
|
|
|
|
* TODO: remove minus-override-plus semantics after
|
|
|
|
|
* warning for a few releases
|
|
|
|
|
*/
|
|
|
|
|
if (!strcasecmp(val, "on") ||
|
|
|
|
|
!strcasecmp(val, "off") ||
|
|
|
|
|
!strcasecmp(val, "true") ||
|
|
|
|
|
!strcasecmp(val, "false")) {
|
|
|
|
|
error_setg(errp, "Boolean properties in format %s=%s"
|
|
|
|
|
" are not supported", name, val);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
error_setg(errp, "Unsupported property format: %s", name);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
cpu_add_feat_as_prop(typename, name, val);
|
|
|
|
|
}
|
2011-09-11 11:33:40 +02:00
|
|
|
|
2017-08-25 16:47:40 +02:00
|
|
|
for (l = plus_features; l; l = l->next) {
|
|
|
|
|
const char *name = l->data;
|
|
|
|
|
cpu_add_feat_as_prop(typename, name, "on");
|
2011-09-11 11:33:40 +02:00
|
|
|
}
|
2017-08-25 16:47:40 +02:00
|
|
|
g_list_free_full(plus_features, g_free);
|
2013-01-16 04:13:19 +01:00
|
|
|
|
2017-08-25 16:47:40 +02:00
|
|
|
for (l = minus_features; l; l = l->next) {
|
|
|
|
|
const char *name = l->data;
|
|
|
|
|
cpu_add_feat_as_prop(typename, name, "off");
|
|
|
|
|
}
|
|
|
|
|
g_list_free_full(minus_features, g_free);
|
|
|
|
|
}
|
2011-09-11 11:33:40 +02:00
|
|
|
|
|
|
|
|
void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
|
|
|
|
|
{
|
|
|
|
|
#if !defined(TARGET_SPARC64)
|
|
|
|
|
env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static const sparc_def_t sparc_defs[] = {
|
|
|
|
|
#ifdef TARGET_SPARC64
|
|
|
|
|
{
|
|
|
|
|
.name = "Fujitsu Sparc64",
|
|
|
|
|
.iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)),
|
|
|
|
|
.fpu_version = 0x00000000,
|
|
|
|
|
.mmu_version = mmu_us_12,
|
|
|
|
|
.nwindows = 4,
|
|
|
|
|
.maxtl = 4,
|
|
|
|
|
.features = CPU_DEFAULT_FEATURES,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "Fujitsu Sparc64 III",
|
|
|
|
|
.iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)),
|
|
|
|
|
.fpu_version = 0x00000000,
|
|
|
|
|
.mmu_version = mmu_us_12,
|
|
|
|
|
.nwindows = 5,
|
|
|
|
|
.maxtl = 4,
|
|
|
|
|
.features = CPU_DEFAULT_FEATURES,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "Fujitsu Sparc64 IV",
|
|
|
|
|
.iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)),
|
|
|
|
|
.fpu_version = 0x00000000,
|
|
|
|
|
.mmu_version = mmu_us_12,
|
|
|
|
|
.nwindows = 8,
|
|
|
|
|
.maxtl = 5,
|
|
|
|
|
.features = CPU_DEFAULT_FEATURES,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "Fujitsu Sparc64 V",
|
|
|
|
|
.iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)),
|
|
|
|
|
.fpu_version = 0x00000000,
|
|
|
|
|
.mmu_version = mmu_us_12,
|
|
|
|
|
.nwindows = 8,
|
|
|
|
|
.maxtl = 5,
|
|
|
|
|
.features = CPU_DEFAULT_FEATURES,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "TI UltraSparc I",
|
|
|
|
|
.iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
|
|
|
|
|
.fpu_version = 0x00000000,
|
|
|
|
|
.mmu_version = mmu_us_12,
|
|
|
|
|
.nwindows = 8,
|
|
|
|
|
.maxtl = 5,
|
|
|
|
|
.features = CPU_DEFAULT_FEATURES,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "TI UltraSparc II",
|
|
|
|
|
.iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)),
|
|
|
|
|
.fpu_version = 0x00000000,
|
|
|
|
|
.mmu_version = mmu_us_12,
|
|
|
|
|
.nwindows = 8,
|
|
|
|
|
.maxtl = 5,
|
|
|
|
|
.features = CPU_DEFAULT_FEATURES,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "TI UltraSparc IIi",
|
|
|
|
|
.iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)),
|
|
|
|
|
.fpu_version = 0x00000000,
|
|
|
|
|
.mmu_version = mmu_us_12,
|
|
|
|
|
.nwindows = 8,
|
|
|
|
|
.maxtl = 5,
|
|
|
|
|
.features = CPU_DEFAULT_FEATURES,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "TI UltraSparc IIe",
|
|
|
|
|
.iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)),
|
|
|
|
|
.fpu_version = 0x00000000,
|
|
|
|
|
.mmu_version = mmu_us_12,
|
|
|
|
|
.nwindows = 8,
|
|
|
|
|
.maxtl = 5,
|
|
|
|
|
.features = CPU_DEFAULT_FEATURES,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "Sun UltraSparc III",
|
|
|
|
|
.iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)),
|
|
|
|
|
.fpu_version = 0x00000000,
|
|
|
|
|
.mmu_version = mmu_us_12,
|
|
|
|
|
.nwindows = 8,
|
|
|
|
|
.maxtl = 5,
|
|
|
|
|
.features = CPU_DEFAULT_FEATURES,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "Sun UltraSparc III Cu",
|
|
|
|
|
.iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)),
|
|
|
|
|
.fpu_version = 0x00000000,
|
|
|
|
|
.mmu_version = mmu_us_3,
|
|
|
|
|
.nwindows = 8,
|
|
|
|
|
.maxtl = 5,
|
|
|
|
|
.features = CPU_DEFAULT_FEATURES,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "Sun UltraSparc IIIi",
|
|
|
|
|
.iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)),
|
|
|
|
|
.fpu_version = 0x00000000,
|
|
|
|
|
.mmu_version = mmu_us_12,
|
|
|
|
|
.nwindows = 8,
|
|
|
|
|
.maxtl = 5,
|
|
|
|
|
.features = CPU_DEFAULT_FEATURES,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "Sun UltraSparc IV",
|
|
|
|
|
.iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)),
|
|
|
|
|
.fpu_version = 0x00000000,
|
|
|
|
|
.mmu_version = mmu_us_4,
|
|
|
|
|
.nwindows = 8,
|
|
|
|
|
.maxtl = 5,
|
|
|
|
|
.features = CPU_DEFAULT_FEATURES,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "Sun UltraSparc IV+",
|
|
|
|
|
.iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)),
|
|
|
|
|
.fpu_version = 0x00000000,
|
|
|
|
|
.mmu_version = mmu_us_12,
|
|
|
|
|
.nwindows = 8,
|
|
|
|
|
.maxtl = 5,
|
|
|
|
|
.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "Sun UltraSparc IIIi+",
|
|
|
|
|
.iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)),
|
|
|
|
|
.fpu_version = 0x00000000,
|
|
|
|
|
.mmu_version = mmu_us_3,
|
|
|
|
|
.nwindows = 8,
|
|
|
|
|
.maxtl = 5,
|
|
|
|
|
.features = CPU_DEFAULT_FEATURES,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "Sun UltraSparc T1",
|
|
|
|
|
/* defined in sparc_ifu_fdp.v and ctu.h */
|
|
|
|
|
.iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)),
|
|
|
|
|
.fpu_version = 0x00000000,
|
|
|
|
|
.mmu_version = mmu_sun4v,
|
|
|
|
|
.nwindows = 8,
|
|
|
|
|
.maxtl = 6,
|
|
|
|
|
.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
|
|
|
|
|
| CPU_FEATURE_GL,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "Sun UltraSparc T2",
|
|
|
|
|
/* defined in tlu_asi_ctl.v and n2_revid_cust.v */
|
|
|
|
|
.iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)),
|
|
|
|
|
.fpu_version = 0x00000000,
|
|
|
|
|
.mmu_version = mmu_sun4v,
|
|
|
|
|
.nwindows = 8,
|
|
|
|
|
.maxtl = 6,
|
|
|
|
|
.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
|
|
|
|
|
| CPU_FEATURE_GL,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "NEC UltraSparc I",
|
|
|
|
|
.iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
|
|
|
|
|
.fpu_version = 0x00000000,
|
|
|
|
|
.mmu_version = mmu_us_12,
|
|
|
|
|
.nwindows = 8,
|
|
|
|
|
.maxtl = 5,
|
|
|
|
|
.features = CPU_DEFAULT_FEATURES,
|
|
|
|
|
},
|
|
|
|
|
#else
|
|
|
|
|
{
|
|
|
|
|
.name = "Fujitsu MB86904",
|
|
|
|
|
.iu_version = 0x04 << 24, /* Impl 0, ver 4 */
|
|
|
|
|
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
|
|
|
|
|
.mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
|
|
|
|
|
.mmu_bm = 0x00004000,
|
|
|
|
|
.mmu_ctpr_mask = 0x00ffffc0,
|
|
|
|
|
.mmu_cxr_mask = 0x000000ff,
|
|
|
|
|
.mmu_sfsr_mask = 0x00016fff,
|
|
|
|
|
.mmu_trcr_mask = 0x00ffffff,
|
|
|
|
|
.nwindows = 8,
|
|
|
|
|
.features = CPU_DEFAULT_FEATURES,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "Fujitsu MB86907",
|
|
|
|
|
.iu_version = 0x05 << 24, /* Impl 0, ver 5 */
|
|
|
|
|
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
|
|
|
|
|
.mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
|
|
|
|
|
.mmu_bm = 0x00004000,
|
|
|
|
|
.mmu_ctpr_mask = 0xffffffc0,
|
|
|
|
|
.mmu_cxr_mask = 0x000000ff,
|
|
|
|
|
.mmu_sfsr_mask = 0x00016fff,
|
|
|
|
|
.mmu_trcr_mask = 0xffffffff,
|
|
|
|
|
.nwindows = 8,
|
|
|
|
|
.features = CPU_DEFAULT_FEATURES,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "TI MicroSparc I",
|
|
|
|
|
.iu_version = 0x41000000,
|
|
|
|
|
.fpu_version = 4 << 17,
|
|
|
|
|
.mmu_version = 0x41000000,
|
|
|
|
|
.mmu_bm = 0x00004000,
|
|
|
|
|
.mmu_ctpr_mask = 0x007ffff0,
|
|
|
|
|
.mmu_cxr_mask = 0x0000003f,
|
|
|
|
|
.mmu_sfsr_mask = 0x00016fff,
|
|
|
|
|
.mmu_trcr_mask = 0x0000003f,
|
|
|
|
|
.nwindows = 7,
|
|
|
|
|
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_MUL |
|
|
|
|
|
CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT |
|
|
|
|
|
CPU_FEATURE_FMUL,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "TI MicroSparc II",
|
|
|
|
|
.iu_version = 0x42000000,
|
|
|
|
|
.fpu_version = 4 << 17,
|
|
|
|
|
.mmu_version = 0x02000000,
|
|
|
|
|
.mmu_bm = 0x00004000,
|
|
|
|
|
.mmu_ctpr_mask = 0x00ffffc0,
|
|
|
|
|
.mmu_cxr_mask = 0x000000ff,
|
|
|
|
|
.mmu_sfsr_mask = 0x00016fff,
|
|
|
|
|
.mmu_trcr_mask = 0x00ffffff,
|
|
|
|
|
.nwindows = 8,
|
|
|
|
|
.features = CPU_DEFAULT_FEATURES,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "TI MicroSparc IIep",
|
|
|
|
|
.iu_version = 0x42000000,
|
|
|
|
|
.fpu_version = 4 << 17,
|
|
|
|
|
.mmu_version = 0x04000000,
|
|
|
|
|
.mmu_bm = 0x00004000,
|
|
|
|
|
.mmu_ctpr_mask = 0x00ffffc0,
|
|
|
|
|
.mmu_cxr_mask = 0x000000ff,
|
|
|
|
|
.mmu_sfsr_mask = 0x00016bff,
|
|
|
|
|
.mmu_trcr_mask = 0x00ffffff,
|
|
|
|
|
.nwindows = 8,
|
|
|
|
|
.features = CPU_DEFAULT_FEATURES,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "TI SuperSparc 40", /* STP1020NPGA */
|
|
|
|
|
.iu_version = 0x41000000, /* SuperSPARC 2.x */
|
|
|
|
|
.fpu_version = 0 << 17,
|
|
|
|
|
.mmu_version = 0x00000800, /* SuperSPARC 2.x, no MXCC */
|
|
|
|
|
.mmu_bm = 0x00002000,
|
|
|
|
|
.mmu_ctpr_mask = 0xffffffc0,
|
|
|
|
|
.mmu_cxr_mask = 0x0000ffff,
|
|
|
|
|
.mmu_sfsr_mask = 0xffffffff,
|
|
|
|
|
.mmu_trcr_mask = 0xffffffff,
|
|
|
|
|
.nwindows = 8,
|
|
|
|
|
.features = CPU_DEFAULT_FEATURES,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "TI SuperSparc 50", /* STP1020PGA */
|
|
|
|
|
.iu_version = 0x40000000, /* SuperSPARC 3.x */
|
|
|
|
|
.fpu_version = 0 << 17,
|
|
|
|
|
.mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
|
|
|
|
|
.mmu_bm = 0x00002000,
|
|
|
|
|
.mmu_ctpr_mask = 0xffffffc0,
|
|
|
|
|
.mmu_cxr_mask = 0x0000ffff,
|
|
|
|
|
.mmu_sfsr_mask = 0xffffffff,
|
|
|
|
|
.mmu_trcr_mask = 0xffffffff,
|
|
|
|
|
.nwindows = 8,
|
|
|
|
|
.features = CPU_DEFAULT_FEATURES,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "TI SuperSparc 51",
|
|
|
|
|
.iu_version = 0x40000000, /* SuperSPARC 3.x */
|
|
|
|
|
.fpu_version = 0 << 17,
|
|
|
|
|
.mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
|
|
|
|
|
.mmu_bm = 0x00002000,
|
|
|
|
|
.mmu_ctpr_mask = 0xffffffc0,
|
|
|
|
|
.mmu_cxr_mask = 0x0000ffff,
|
|
|
|
|
.mmu_sfsr_mask = 0xffffffff,
|
|
|
|
|
.mmu_trcr_mask = 0xffffffff,
|
|
|
|
|
.mxcc_version = 0x00000104,
|
|
|
|
|
.nwindows = 8,
|
|
|
|
|
.features = CPU_DEFAULT_FEATURES,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "TI SuperSparc 60", /* STP1020APGA */
|
|
|
|
|
.iu_version = 0x40000000, /* SuperSPARC 3.x */
|
|
|
|
|
.fpu_version = 0 << 17,
|
|
|
|
|
.mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
|
|
|
|
|
.mmu_bm = 0x00002000,
|
|
|
|
|
.mmu_ctpr_mask = 0xffffffc0,
|
|
|
|
|
.mmu_cxr_mask = 0x0000ffff,
|
|
|
|
|
.mmu_sfsr_mask = 0xffffffff,
|
|
|
|
|
.mmu_trcr_mask = 0xffffffff,
|
|
|
|
|
.nwindows = 8,
|
|
|
|
|
.features = CPU_DEFAULT_FEATURES,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "TI SuperSparc 61",
|
|
|
|
|
.iu_version = 0x44000000, /* SuperSPARC 3.x */
|
|
|
|
|
.fpu_version = 0 << 17,
|
|
|
|
|
.mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
|
|
|
|
|
.mmu_bm = 0x00002000,
|
|
|
|
|
.mmu_ctpr_mask = 0xffffffc0,
|
|
|
|
|
.mmu_cxr_mask = 0x0000ffff,
|
|
|
|
|
.mmu_sfsr_mask = 0xffffffff,
|
|
|
|
|
.mmu_trcr_mask = 0xffffffff,
|
|
|
|
|
.mxcc_version = 0x00000104,
|
|
|
|
|
.nwindows = 8,
|
|
|
|
|
.features = CPU_DEFAULT_FEATURES,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "TI SuperSparc II",
|
|
|
|
|
.iu_version = 0x40000000, /* SuperSPARC II 1.x */
|
|
|
|
|
.fpu_version = 0 << 17,
|
|
|
|
|
.mmu_version = 0x08000000, /* SuperSPARC II 1.x, MXCC */
|
|
|
|
|
.mmu_bm = 0x00002000,
|
|
|
|
|
.mmu_ctpr_mask = 0xffffffc0,
|
|
|
|
|
.mmu_cxr_mask = 0x0000ffff,
|
|
|
|
|
.mmu_sfsr_mask = 0xffffffff,
|
|
|
|
|
.mmu_trcr_mask = 0xffffffff,
|
|
|
|
|
.mxcc_version = 0x00000104,
|
|
|
|
|
.nwindows = 8,
|
|
|
|
|
.features = CPU_DEFAULT_FEATURES,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "LEON2",
|
|
|
|
|
.iu_version = 0xf2000000,
|
|
|
|
|
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
|
|
|
|
|
.mmu_version = 0xf2000000,
|
|
|
|
|
.mmu_bm = 0x00004000,
|
|
|
|
|
.mmu_ctpr_mask = 0x007ffff0,
|
|
|
|
|
.mmu_cxr_mask = 0x0000003f,
|
|
|
|
|
.mmu_sfsr_mask = 0xffffffff,
|
|
|
|
|
.mmu_trcr_mask = 0xffffffff,
|
|
|
|
|
.nwindows = 8,
|
|
|
|
|
.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "LEON3",
|
|
|
|
|
.iu_version = 0xf3000000,
|
|
|
|
|
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
|
|
|
|
|
.mmu_version = 0xf3000000,
|
|
|
|
|
.mmu_bm = 0x00000000,
|
2013-02-19 12:45:06 +01:00
|
|
|
.mmu_ctpr_mask = 0xfffffffc,
|
|
|
|
|
.mmu_cxr_mask = 0x000000ff,
|
2011-09-11 11:33:40 +02:00
|
|
|
.mmu_sfsr_mask = 0xffffffff,
|
|
|
|
|
.mmu_trcr_mask = 0xffffffff,
|
|
|
|
|
.nwindows = 8,
|
|
|
|
|
.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN |
|
target-sparc: Add and use CPU_FEATURE_CASA
The LEON3 processor has support for the CASA instruction which is
normally only available for SPARC V9 processors. Binutils 2.24
and GCC 4.9 will support this instruction for LEON3. GCC uses it to
generate C11 atomic operations.
The CAS synthetic instruction uses an ASI of 0x80. If TARGET_SPARC64 is
not defined use a supervisor data load/store for an ASI of 0x80 in
helper_ld_asi()/helper_st_asi(). The supervisor data load/store was
choosen according to the LEON3 documentation.
The ASI 0x80 is defined in the SPARC V9 manual, Table 12—Address Space
Identifiers (ASIs). Here we have: 0x80, ASI_PRIMARY, Unrestricted
access, Primary address space.
Tested with the following program:
#include <assert.h>
#include <stdatomic.h>
void test(void)
{
atomic_int a;
int e;
_Bool b;
atomic_store(&a, 1);
e = 1;
b = atomic_compare_exchange_strong(&a, &e, 2);
assert(b);
assert(atomic_load(&a) == 2);
atomic_store(&a, 3);
e = 4;
b = atomic_compare_exchange_strong(&a, &e, 5);
assert(!b);
assert(atomic_load(&a) == 3);
}
Tested also on a NGMP board with a LEON4 processor.
Reviewed-by: Fabien Chouteau <chouteau@adacore.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2014-03-11 10:36:00 +01:00
|
|
|
CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL | CPU_FEATURE_POWERDOWN |
|
|
|
|
|
CPU_FEATURE_CASA,
|
2011-09-11 11:33:40 +02:00
|
|
|
},
|
|
|
|
|
#endif
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const char * const feature_name[] = {
|
|
|
|
|
"float",
|
|
|
|
|
"float128",
|
|
|
|
|
"swap",
|
|
|
|
|
"mul",
|
|
|
|
|
"div",
|
|
|
|
|
"flush",
|
|
|
|
|
"fsqrt",
|
|
|
|
|
"fmul",
|
|
|
|
|
"vis1",
|
|
|
|
|
"vis2",
|
|
|
|
|
"fsmuld",
|
|
|
|
|
"hypv",
|
|
|
|
|
"cmt",
|
|
|
|
|
"gl",
|
|
|
|
|
};
|
|
|
|
|
|
2019-04-17 21:17:57 +02:00
|
|
|
static void print_features(uint32_t features, const char *prefix)
|
2011-09-11 11:33:40 +02:00
|
|
|
{
|
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(feature_name); i++) {
|
|
|
|
|
if (feature_name[i] && (features & (1 << i))) {
|
|
|
|
|
if (prefix) {
|
2019-04-17 21:17:57 +02:00
|
|
|
qemu_printf("%s", prefix);
|
2011-09-11 11:33:40 +02:00
|
|
|
}
|
2019-04-17 21:17:57 +02:00
|
|
|
qemu_printf("%s ", feature_name[i]);
|
2011-09-11 11:33:40 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2019-04-17 21:17:57 +02:00
|
|
|
void sparc_cpu_list(void)
|
2011-09-11 11:33:40 +02:00
|
|
|
{
|
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
|
2019-04-17 21:17:57 +02:00
|
|
|
qemu_printf("Sparc %16s IU " TARGET_FMT_lx
|
|
|
|
|
" FPU %08x MMU %08x NWINS %d ",
|
|
|
|
|
sparc_defs[i].name,
|
|
|
|
|
sparc_defs[i].iu_version,
|
|
|
|
|
sparc_defs[i].fpu_version,
|
|
|
|
|
sparc_defs[i].mmu_version,
|
|
|
|
|
sparc_defs[i].nwindows);
|
|
|
|
|
print_features(CPU_DEFAULT_FEATURES & ~sparc_defs[i].features, "-");
|
|
|
|
|
print_features(~CPU_DEFAULT_FEATURES & sparc_defs[i].features, "+");
|
|
|
|
|
qemu_printf("\n");
|
2011-09-11 11:33:40 +02:00
|
|
|
}
|
2019-04-17 21:17:57 +02:00
|
|
|
qemu_printf("Default CPU feature flags (use '-' to remove): ");
|
|
|
|
|
print_features(CPU_DEFAULT_FEATURES, NULL);
|
|
|
|
|
qemu_printf("\n");
|
|
|
|
|
qemu_printf("Available CPU feature flags (use '+' to add): ");
|
|
|
|
|
print_features(~CPU_DEFAULT_FEATURES, NULL);
|
|
|
|
|
qemu_printf("\n");
|
|
|
|
|
qemu_printf("Numerical features (use '=' to set): iu_version "
|
|
|
|
|
"fpu_version mmu_version nwindows\n");
|
2011-09-11 11:33:40 +02:00
|
|
|
}
|
|
|
|
|
|
2019-04-17 21:18:02 +02:00
|
|
|
static void cpu_print_cc(FILE *f, uint32_t cc)
|
2011-09-11 11:33:40 +02:00
|
|
|
{
|
2019-04-17 21:18:02 +02:00
|
|
|
qemu_fprintf(f, "%c%c%c%c", cc & PSR_NEG ? 'N' : '-',
|
|
|
|
|
cc & PSR_ZERO ? 'Z' : '-', cc & PSR_OVF ? 'V' : '-',
|
|
|
|
|
cc & PSR_CARRY ? 'C' : '-');
|
2011-09-11 11:33:40 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#ifdef TARGET_SPARC64
|
|
|
|
|
#define REGS_PER_LINE 4
|
|
|
|
|
#else
|
|
|
|
|
#define REGS_PER_LINE 8
|
|
|
|
|
#endif
|
|
|
|
|
|
2019-04-17 21:18:02 +02:00
|
|
|
void sparc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
|
2011-09-11 11:33:40 +02:00
|
|
|
{
|
2013-05-27 01:33:50 +02:00
|
|
|
SPARCCPU *cpu = SPARC_CPU(cs);
|
|
|
|
|
CPUSPARCState *env = &cpu->env;
|
2011-09-11 11:33:40 +02:00
|
|
|
int i, x;
|
|
|
|
|
|
2019-04-17 21:18:02 +02:00
|
|
|
qemu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc,
|
|
|
|
|
env->npc);
|
2011-09-11 11:33:40 +02:00
|
|
|
|
|
|
|
|
for (i = 0; i < 8; i++) {
|
|
|
|
|
if (i % REGS_PER_LINE == 0) {
|
2019-04-17 21:18:02 +02:00
|
|
|
qemu_fprintf(f, "%%g%d-%d:", i, i + REGS_PER_LINE - 1);
|
2011-09-11 11:33:40 +02:00
|
|
|
}
|
2019-04-17 21:18:02 +02:00
|
|
|
qemu_fprintf(f, " " TARGET_FMT_lx, env->gregs[i]);
|
2011-09-11 11:33:40 +02:00
|
|
|
if (i % REGS_PER_LINE == REGS_PER_LINE - 1) {
|
2019-04-17 21:18:02 +02:00
|
|
|
qemu_fprintf(f, "\n");
|
2011-09-11 11:33:40 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
for (x = 0; x < 3; x++) {
|
|
|
|
|
for (i = 0; i < 8; i++) {
|
|
|
|
|
if (i % REGS_PER_LINE == 0) {
|
2019-04-17 21:18:02 +02:00
|
|
|
qemu_fprintf(f, "%%%c%d-%d: ",
|
|
|
|
|
x == 0 ? 'o' : (x == 1 ? 'l' : 'i'),
|
|
|
|
|
i, i + REGS_PER_LINE - 1);
|
2011-09-11 11:33:40 +02:00
|
|
|
}
|
2019-04-17 21:18:02 +02:00
|
|
|
qemu_fprintf(f, TARGET_FMT_lx " ", env->regwptr[i + x * 8]);
|
2011-09-11 11:33:40 +02:00
|
|
|
if (i % REGS_PER_LINE == REGS_PER_LINE - 1) {
|
2019-04-17 21:18:02 +02:00
|
|
|
qemu_fprintf(f, "\n");
|
2011-09-11 11:33:40 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
2012-10-06 01:54:48 +02:00
|
|
|
|
2018-05-11 05:42:10 +02:00
|
|
|
if (flags & CPU_DUMP_FPU) {
|
|
|
|
|
for (i = 0; i < TARGET_DPREGS; i++) {
|
|
|
|
|
if ((i & 3) == 0) {
|
2019-04-17 21:18:02 +02:00
|
|
|
qemu_fprintf(f, "%%f%02d: ", i * 2);
|
2018-05-11 05:42:10 +02:00
|
|
|
}
|
2019-04-17 21:18:02 +02:00
|
|
|
qemu_fprintf(f, " %016" PRIx64, env->fpr[i].ll);
|
2018-05-11 05:42:10 +02:00
|
|
|
if ((i & 3) == 3) {
|
2019-04-17 21:18:02 +02:00
|
|
|
qemu_fprintf(f, "\n");
|
2018-05-11 05:42:10 +02:00
|
|
|
}
|
2011-09-11 11:33:40 +02:00
|
|
|
}
|
|
|
|
|
}
|
2018-05-11 05:42:10 +02:00
|
|
|
|
2011-09-11 11:33:40 +02:00
|
|
|
#ifdef TARGET_SPARC64
|
2019-04-17 21:18:02 +02:00
|
|
|
qemu_fprintf(f, "pstate: %08x ccr: %02x (icc: ", env->pstate,
|
|
|
|
|
(unsigned)cpu_get_ccr(env));
|
|
|
|
|
cpu_print_cc(f, cpu_get_ccr(env) << PSR_CARRY_SHIFT);
|
|
|
|
|
qemu_fprintf(f, " xcc: ");
|
|
|
|
|
cpu_print_cc(f, cpu_get_ccr(env) << (PSR_CARRY_SHIFT - 4));
|
|
|
|
|
qemu_fprintf(f, ") asi: %02x tl: %d pil: %x gl: %d\n", env->asi, env->tl,
|
|
|
|
|
env->psrpil, env->gl);
|
|
|
|
|
qemu_fprintf(f, "tbr: " TARGET_FMT_lx " hpstate: " TARGET_FMT_lx " htba: "
|
|
|
|
|
TARGET_FMT_lx "\n", env->tbr, env->hpstate, env->htba);
|
|
|
|
|
qemu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate: %d "
|
|
|
|
|
"cleanwin: %d cwp: %d\n",
|
|
|
|
|
env->cansave, env->canrestore, env->otherwin, env->wstate,
|
|
|
|
|
env->cleanwin, env->nwindows - 1 - env->cwp);
|
|
|
|
|
qemu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx " fprs: "
|
|
|
|
|
TARGET_FMT_lx "\n", env->fsr, env->y, env->fprs);
|
2016-06-07 18:34:49 +02:00
|
|
|
|
2011-09-11 11:33:40 +02:00
|
|
|
#else
|
2019-04-17 21:18:02 +02:00
|
|
|
qemu_fprintf(f, "psr: %08x (icc: ", cpu_get_psr(env));
|
|
|
|
|
cpu_print_cc(f, cpu_get_psr(env));
|
|
|
|
|
qemu_fprintf(f, " SPE: %c%c%c) wim: %08x\n", env->psrs ? 'S' : '-',
|
|
|
|
|
env->psrps ? 'P' : '-', env->psret ? 'E' : '-',
|
|
|
|
|
env->wim);
|
|
|
|
|
qemu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx "\n",
|
|
|
|
|
env->fsr, env->y);
|
2011-09-11 11:33:40 +02:00
|
|
|
#endif
|
2019-04-17 21:18:02 +02:00
|
|
|
qemu_fprintf(f, "\n");
|
2011-09-11 11:33:40 +02:00
|
|
|
}
|
2012-04-05 01:29:40 +02:00
|
|
|
|
2013-06-21 19:09:18 +02:00
|
|
|
static void sparc_cpu_set_pc(CPUState *cs, vaddr value)
|
|
|
|
|
{
|
|
|
|
|
SPARCCPU *cpu = SPARC_CPU(cs);
|
|
|
|
|
|
|
|
|
|
cpu->env.pc = value;
|
|
|
|
|
cpu->env.npc = value + 4;
|
|
|
|
|
}
|
|
|
|
|
|
2013-06-28 19:31:32 +02:00
|
|
|
static void sparc_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
|
|
|
|
|
{
|
|
|
|
|
SPARCCPU *cpu = SPARC_CPU(cs);
|
|
|
|
|
|
|
|
|
|
cpu->env.pc = tb->pc;
|
|
|
|
|
cpu->env.npc = tb->cs_base;
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-25 18:53:55 +02:00
|
|
|
static bool sparc_cpu_has_work(CPUState *cs)
|
|
|
|
|
{
|
|
|
|
|
SPARCCPU *cpu = SPARC_CPU(cs);
|
|
|
|
|
CPUSPARCState *env = &cpu->env;
|
|
|
|
|
|
|
|
|
|
return (cs->interrupt_request & CPU_INTERRUPT_HARD) &&
|
|
|
|
|
cpu_interrupts_enabled(env);
|
|
|
|
|
}
|
|
|
|
|
|
2017-08-24 18:31:25 +02:00
|
|
|
static char *sparc_cpu_type_name(const char *cpu_model)
|
|
|
|
|
{
|
2017-10-05 15:51:05 +02:00
|
|
|
char *name = g_strdup_printf(SPARC_CPU_TYPE_NAME("%s"), cpu_model);
|
2017-08-24 18:31:25 +02:00
|
|
|
char *s = name;
|
|
|
|
|
|
|
|
|
|
/* SPARC cpu model names happen to have whitespaces,
|
|
|
|
|
* as type names shouldn't have spaces replace them with '-'
|
|
|
|
|
*/
|
|
|
|
|
while ((s = strchr(s, ' '))) {
|
|
|
|
|
*s = '-';
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return name;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static ObjectClass *sparc_cpu_class_by_name(const char *cpu_model)
|
|
|
|
|
{
|
|
|
|
|
ObjectClass *oc;
|
|
|
|
|
char *typename;
|
|
|
|
|
|
|
|
|
|
typename = sparc_cpu_type_name(cpu_model);
|
|
|
|
|
oc = object_class_by_name(typename);
|
|
|
|
|
g_free(typename);
|
|
|
|
|
return oc;
|
|
|
|
|
}
|
|
|
|
|
|
2013-01-16 04:13:19 +01:00
|
|
|
static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
|
|
|
|
|
{
|
2016-10-20 13:26:03 +02:00
|
|
|
CPUState *cs = CPU(dev);
|
2013-01-16 04:13:19 +01:00
|
|
|
SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev);
|
2016-10-20 13:26:03 +02:00
|
|
|
Error *local_err = NULL;
|
2014-03-04 01:26:33 +01:00
|
|
|
SPARCCPU *cpu = SPARC_CPU(dev);
|
|
|
|
|
CPUSPARCState *env = &cpu->env;
|
|
|
|
|
|
2017-08-24 18:31:28 +02:00
|
|
|
#if defined(CONFIG_USER_ONLY)
|
2017-08-24 18:31:26 +02:00
|
|
|
if ((env->def.features & CPU_FEATURE_FLOAT)) {
|
|
|
|
|
env->def.features |= CPU_FEATURE_FLOAT128;
|
2014-03-04 01:26:33 +01:00
|
|
|
}
|
|
|
|
|
#endif
|
2013-01-16 04:13:19 +01:00
|
|
|
|
2017-08-24 18:31:28 +02:00
|
|
|
env->version = env->def.iu_version;
|
|
|
|
|
env->fsr = env->def.fpu_version;
|
|
|
|
|
env->nwindows = env->def.nwindows;
|
|
|
|
|
#if !defined(TARGET_SPARC64)
|
|
|
|
|
env->mmuregs[0] |= env->def.mmu_version;
|
|
|
|
|
cpu_sparc_set_id(env, 0);
|
|
|
|
|
env->mxccregs[7] |= env->def.mxcc_version;
|
|
|
|
|
#else
|
|
|
|
|
env->mmu_version = env->def.mmu_version;
|
|
|
|
|
env->maxtl = env->def.maxtl;
|
|
|
|
|
env->version |= env->def.maxtl << 8;
|
|
|
|
|
env->version |= env->def.nwindows - 1;
|
|
|
|
|
#endif
|
|
|
|
|
|
2016-10-20 13:26:03 +02:00
|
|
|
cpu_exec_realizefn(cs, &local_err);
|
|
|
|
|
if (local_err != NULL) {
|
|
|
|
|
error_propagate(errp, local_err);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
qemu_init_vcpu(cs);
|
2013-07-27 02:53:25 +02:00
|
|
|
|
2013-01-16 04:13:19 +01:00
|
|
|
scc->parent_realize(dev, errp);
|
|
|
|
|
}
|
|
|
|
|
|
2012-04-05 01:29:40 +02:00
|
|
|
static void sparc_cpu_initfn(Object *obj)
|
|
|
|
|
{
|
|
|
|
|
SPARCCPU *cpu = SPARC_CPU(obj);
|
2017-08-24 18:31:25 +02:00
|
|
|
SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(obj);
|
2012-04-05 01:29:40 +02:00
|
|
|
CPUSPARCState *env = &cpu->env;
|
|
|
|
|
|
2019-03-28 22:26:22 +01:00
|
|
|
cpu_set_cpustate_pointers(cpu);
|
2013-01-20 01:34:18 +01:00
|
|
|
|
2017-08-24 18:31:26 +02:00
|
|
|
if (scc->cpu_def) {
|
|
|
|
|
env->def = *scc->cpu_def;
|
|
|
|
|
}
|
2012-04-05 01:29:40 +02:00
|
|
|
}
|
|
|
|
|
|
2017-08-24 18:31:27 +02:00
|
|
|
static void sparc_get_nwindows(Object *obj, Visitor *v, const char *name,
|
|
|
|
|
void *opaque, Error **errp)
|
|
|
|
|
{
|
|
|
|
|
SPARCCPU *cpu = SPARC_CPU(obj);
|
|
|
|
|
int64_t value = cpu->env.def.nwindows;
|
|
|
|
|
|
|
|
|
|
visit_type_int(v, name, &value, errp);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void sparc_set_nwindows(Object *obj, Visitor *v, const char *name,
|
|
|
|
|
void *opaque, Error **errp)
|
|
|
|
|
{
|
|
|
|
|
const int64_t min = MIN_NWINDOWS;
|
|
|
|
|
const int64_t max = MAX_NWINDOWS;
|
|
|
|
|
SPARCCPU *cpu = SPARC_CPU(obj);
|
|
|
|
|
int64_t value;
|
|
|
|
|
|
error: Eliminate error_propagate() with Coccinelle, part 1
When all we do with an Error we receive into a local variable is
propagating to somewhere else, we can just as well receive it there
right away. Convert
if (!foo(..., &err)) {
...
error_propagate(errp, err);
...
return ...
}
to
if (!foo(..., errp)) {
...
...
return ...
}
where nothing else needs @err. Coccinelle script:
@rule1 forall@
identifier fun, err, errp, lbl;
expression list args, args2;
binary operator op;
constant c1, c2;
symbol false;
@@
if (
(
- fun(args, &err, args2)
+ fun(args, errp, args2)
|
- !fun(args, &err, args2)
+ !fun(args, errp, args2)
|
- fun(args, &err, args2) op c1
+ fun(args, errp, args2) op c1
)
)
{
... when != err
when != lbl:
when strict
- error_propagate(errp, err);
... when != err
(
return;
|
return c2;
|
return false;
)
}
@rule2 forall@
identifier fun, err, errp, lbl;
expression list args, args2;
expression var;
binary operator op;
constant c1, c2;
symbol false;
@@
- var = fun(args, &err, args2);
+ var = fun(args, errp, args2);
... when != err
if (
(
var
|
!var
|
var op c1
)
)
{
... when != err
when != lbl:
when strict
- error_propagate(errp, err);
... when != err
(
return;
|
return c2;
|
return false;
|
return var;
)
}
@depends on rule1 || rule2@
identifier err;
@@
- Error *err = NULL;
... when != err
Not exactly elegant, I'm afraid.
The "when != lbl:" is necessary to avoid transforming
if (fun(args, &err)) {
goto out
}
...
out:
error_propagate(errp, err);
even though other paths to label out still need the error_propagate().
For an actual example, see sclp_realize().
Without the "when strict", Coccinelle transforms vfio_msix_setup(),
incorrectly. I don't know what exactly "when strict" does, only that
it helps here.
The match of return is narrower than what I want, but I can't figure
out how to express "return where the operand doesn't use @err". For
an example where it's too narrow, see vfio_intx_enable().
Silently fails to convert hw/arm/armsse.c, because Coccinelle gets
confused by ARMSSE being used both as typedef and function-like macro
there. Converted manually.
Line breaks tidied up manually. One nested declaration of @local_err
deleted manually. Preexisting unwanted blank line dropped in
hw/riscv/sifive_e.c.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-Id: <20200707160613.848843-35-armbru@redhat.com>
2020-07-07 18:06:02 +02:00
|
|
|
if (!visit_type_int(v, name, &value, errp)) {
|
2017-08-24 18:31:27 +02:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (value < min || value > max) {
|
|
|
|
|
error_setg(errp, "Property %s.%s doesn't take value %" PRId64
|
|
|
|
|
" (minimum: %" PRId64 ", maximum: %" PRId64 ")",
|
|
|
|
|
object_get_typename(obj), name ? name : "null",
|
|
|
|
|
value, min, max);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
cpu->env.def.nwindows = value;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static PropertyInfo qdev_prop_nwindows = {
|
|
|
|
|
.name = "int",
|
|
|
|
|
.get = sparc_get_nwindows,
|
|
|
|
|
.set = sparc_set_nwindows,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static Property sparc_cpu_properties[] = {
|
|
|
|
|
DEFINE_PROP_BIT("float", SPARCCPU, env.def.features, 0, false),
|
|
|
|
|
DEFINE_PROP_BIT("float128", SPARCCPU, env.def.features, 1, false),
|
|
|
|
|
DEFINE_PROP_BIT("swap", SPARCCPU, env.def.features, 2, false),
|
|
|
|
|
DEFINE_PROP_BIT("mul", SPARCCPU, env.def.features, 3, false),
|
|
|
|
|
DEFINE_PROP_BIT("div", SPARCCPU, env.def.features, 4, false),
|
|
|
|
|
DEFINE_PROP_BIT("flush", SPARCCPU, env.def.features, 5, false),
|
|
|
|
|
DEFINE_PROP_BIT("fsqrt", SPARCCPU, env.def.features, 6, false),
|
|
|
|
|
DEFINE_PROP_BIT("fmul", SPARCCPU, env.def.features, 7, false),
|
|
|
|
|
DEFINE_PROP_BIT("vis1", SPARCCPU, env.def.features, 8, false),
|
|
|
|
|
DEFINE_PROP_BIT("vis2", SPARCCPU, env.def.features, 9, false),
|
|
|
|
|
DEFINE_PROP_BIT("fsmuld", SPARCCPU, env.def.features, 10, false),
|
|
|
|
|
DEFINE_PROP_BIT("hypv", SPARCCPU, env.def.features, 11, false),
|
|
|
|
|
DEFINE_PROP_BIT("cmt", SPARCCPU, env.def.features, 12, false),
|
|
|
|
|
DEFINE_PROP_BIT("gl", SPARCCPU, env.def.features, 13, false),
|
|
|
|
|
DEFINE_PROP_UNSIGNED("iu-version", SPARCCPU, env.def.iu_version, 0,
|
|
|
|
|
qdev_prop_uint64, target_ulong),
|
|
|
|
|
DEFINE_PROP_UINT32("fpu-version", SPARCCPU, env.def.fpu_version, 0),
|
|
|
|
|
DEFINE_PROP_UINT32("mmu-version", SPARCCPU, env.def.mmu_version, 0),
|
|
|
|
|
{ .name = "nwindows", .info = &qdev_prop_nwindows },
|
|
|
|
|
DEFINE_PROP_END_OF_LIST()
|
|
|
|
|
};
|
|
|
|
|
|
2012-04-05 01:29:40 +02:00
|
|
|
static void sparc_cpu_class_init(ObjectClass *oc, void *data)
|
|
|
|
|
{
|
|
|
|
|
SPARCCPUClass *scc = SPARC_CPU_CLASS(oc);
|
|
|
|
|
CPUClass *cc = CPU_CLASS(oc);
|
2013-01-16 04:13:19 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
|
|
2018-01-14 03:04:12 +01:00
|
|
|
device_class_set_parent_realize(dc, sparc_cpu_realizefn,
|
|
|
|
|
&scc->parent_realize);
|
2020-01-10 16:30:32 +01:00
|
|
|
device_class_set_props(dc, sparc_cpu_properties);
|
2012-04-05 01:29:40 +02:00
|
|
|
|
cpu: Use DeviceClass reset instead of a special CPUClass reset
The CPUClass has a 'reset' method. This is a legacy from when
TYPE_CPU used not to inherit from TYPE_DEVICE. We don't need it any
more, as we can simply use the TYPE_DEVICE reset. The 'cpu_reset()'
function is kept as the API which most places use to reset a CPU; it
is now a wrapper which calls device_cold_reset() and then the
tracepoint function.
This change should not cause CPU objects to be reset more often
than they are at the moment, because:
* nobody is directly calling device_cold_reset() or
qdev_reset_all() on CPU objects
* no CPU object is on a qbus, so they will not be reset either
by somebody calling qbus_reset_all()/bus_cold_reset(), or
by the main "reset sysbus and everything in the qbus tree"
reset that most devices are reset by
Note that this does not change the need for each machine or whatever
to use qemu_register_reset() to arrange to call cpu_reset() -- that
is necessary because CPU objects are not on any qbus, so they don't
get reset when the qbus tree rooted at the sysbus bus is reset, and
this isn't being changed here.
All the changes to the files under target/ were made using the
included Coccinelle script, except:
(1) the deletion of the now-inaccurate and not terribly useful
"CPUClass::reset" comments was done with a perl one-liner afterwards:
perl -n -i -e '/ CPUClass::reset/ or print' target/*/*.c
(2) this bit of the s390 change was done by hand, because the
Coccinelle script is not sophisticated enough to handle the
parent_reset call being inside another function:
| @@ -96,8 +96,9 @@ static void s390_cpu_reset(CPUState *s, cpu_reset_type type)
| S390CPU *cpu = S390_CPU(s);
| S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);
| CPUS390XState *env = &cpu->env;
|+ DeviceState *dev = DEVICE(s);
|
|- scc->parent_reset(s);
|+ scc->parent_reset(dev);
| cpu->env.sigp_order = 0;
| s390_cpu_set_state(S390_CPU_STATE_STOPPED, cpu);
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20200303100511.5498-1-peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-03-03 11:05:11 +01:00
|
|
|
device_class_set_parent_reset(dc, sparc_cpu_reset, &scc->parent_reset);
|
2013-02-02 10:57:51 +01:00
|
|
|
|
2017-08-24 18:31:25 +02:00
|
|
|
cc->class_by_name = sparc_cpu_class_by_name;
|
2017-08-25 16:47:40 +02:00
|
|
|
cc->parse_features = sparc_cpu_parse_features;
|
2013-08-25 18:53:55 +02:00
|
|
|
cc->has_work = sparc_cpu_has_work;
|
2013-02-02 10:57:51 +01:00
|
|
|
cc->do_interrupt = sparc_cpu_do_interrupt;
|
2014-09-13 18:45:26 +02:00
|
|
|
cc->cpu_exec_interrupt = sparc_cpu_exec_interrupt;
|
2013-05-27 01:33:50 +02:00
|
|
|
cc->dump_state = sparc_cpu_dump_state;
|
2013-06-27 19:09:09 +02:00
|
|
|
#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
|
|
|
|
|
cc->memory_rw_debug = sparc_cpu_memory_rw_debug;
|
|
|
|
|
#endif
|
2013-06-21 19:09:18 +02:00
|
|
|
cc->set_pc = sparc_cpu_set_pc;
|
2013-06-28 19:31:32 +02:00
|
|
|
cc->synchronize_from_tb = sparc_cpu_synchronize_from_tb;
|
2013-06-29 04:18:45 +02:00
|
|
|
cc->gdb_read_register = sparc_cpu_gdb_read_register;
|
|
|
|
|
cc->gdb_write_register = sparc_cpu_gdb_write_register;
|
2019-04-03 02:16:41 +02:00
|
|
|
cc->tlb_fill = sparc_cpu_tlb_fill;
|
|
|
|
|
#ifndef CONFIG_USER_ONLY
|
2019-08-01 20:30:12 +02:00
|
|
|
cc->do_transaction_failed = sparc_cpu_do_transaction_failed;
|
2014-03-28 18:14:58 +01:00
|
|
|
cc->do_unaligned_access = sparc_cpu_do_unaligned_access;
|
2013-06-29 18:55:54 +02:00
|
|
|
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
|
2016-01-11 13:40:26 +01:00
|
|
|
cc->vmsd = &vmstate_sparc_cpu;
|
2013-06-29 18:55:54 +02:00
|
|
|
#endif
|
2015-07-12 04:00:01 +02:00
|
|
|
cc->disas_set_info = cpu_sparc_disas_set_info;
|
2017-10-16 04:02:42 +02:00
|
|
|
cc->tcg_initialize = sparc_tcg_init;
|
2013-06-28 23:18:47 +02:00
|
|
|
|
|
|
|
|
#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
|
|
|
|
|
cc->gdb_num_core_regs = 86;
|
|
|
|
|
#else
|
|
|
|
|
cc->gdb_num_core_regs = 72;
|
|
|
|
|
#endif
|
2012-04-05 01:29:40 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static const TypeInfo sparc_cpu_type_info = {
|
|
|
|
|
.name = TYPE_SPARC_CPU,
|
|
|
|
|
.parent = TYPE_CPU,
|
|
|
|
|
.instance_size = sizeof(SPARCCPU),
|
|
|
|
|
.instance_init = sparc_cpu_initfn,
|
2017-08-24 18:31:25 +02:00
|
|
|
.abstract = true,
|
2012-04-05 01:29:40 +02:00
|
|
|
.class_size = sizeof(SPARCCPUClass),
|
|
|
|
|
.class_init = sparc_cpu_class_init,
|
|
|
|
|
};
|
|
|
|
|
|
2017-08-24 18:31:25 +02:00
|
|
|
static void sparc_cpu_cpudef_class_init(ObjectClass *oc, void *data)
|
|
|
|
|
{
|
|
|
|
|
SPARCCPUClass *scc = SPARC_CPU_CLASS(oc);
|
|
|
|
|
scc->cpu_def = data;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void sparc_register_cpudef_type(const struct sparc_def_t *def)
|
|
|
|
|
{
|
|
|
|
|
char *typename = sparc_cpu_type_name(def->name);
|
|
|
|
|
TypeInfo ti = {
|
|
|
|
|
.name = typename,
|
|
|
|
|
.parent = TYPE_SPARC_CPU,
|
|
|
|
|
.class_init = sparc_cpu_cpudef_class_init,
|
|
|
|
|
.class_data = (void *)def,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
type_register(&ti);
|
|
|
|
|
g_free(typename);
|
|
|
|
|
}
|
|
|
|
|
|
2012-04-05 01:29:40 +02:00
|
|
|
static void sparc_cpu_register_types(void)
|
|
|
|
|
{
|
2017-08-24 18:31:25 +02:00
|
|
|
int i;
|
|
|
|
|
|
2012-04-05 01:29:40 +02:00
|
|
|
type_register_static(&sparc_cpu_type_info);
|
2017-08-24 18:31:25 +02:00
|
|
|
for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
|
|
|
|
|
sparc_register_cpudef_type(&sparc_defs[i]);
|
|
|
|
|
}
|
2012-04-05 01:29:40 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
type_init(sparc_cpu_register_types)
|