2006-04-27 23:07:38 +02:00
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/*
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* SH4 emulation
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2007-09-16 23:08:06 +02:00
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*
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2006-04-27 23:07:38 +02:00
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* Copyright (c) 2005 Samuel Tardieu
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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2019-02-13 14:52:50 +01:00
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* version 2.1 of the License, or (at your option) any later version.
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2006-04-27 23:07:38 +02:00
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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2009-07-16 22:47:01 +02:00
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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2006-04-27 23:07:38 +02:00
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*/
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2016-01-26 19:17:20 +01:00
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#include "qemu/osdep.h"
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2011-07-13 14:44:15 +02:00
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#include "cpu.h"
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2014-04-08 07:31:41 +02:00
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#include "exec/helper-proto.h"
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2016-03-15 13:18:37 +01:00
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#include "exec/exec-all.h"
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2014-03-28 19:42:10 +01:00
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#include "exec/cpu_ldst.h"
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2018-01-19 19:24:22 +01:00
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#include "fpu/softfloat.h"
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2006-04-27 23:07:38 +02:00
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#ifndef CONFIG_USER_ONLY
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2017-05-01 23:20:43 +02:00
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void superh_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
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MMUAccessType access_type,
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int mmu_idx, uintptr_t retaddr)
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{
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2021-07-29 02:16:56 +02:00
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CPUSH4State *env = cs->env_ptr;
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env->tea = addr;
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2017-05-01 23:20:43 +02:00
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switch (access_type) {
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case MMU_INST_FETCH:
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case MMU_DATA_LOAD:
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cs->exception_index = 0x0e0;
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break;
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case MMU_DATA_STORE:
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cs->exception_index = 0x100;
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break;
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2021-07-29 02:16:56 +02:00
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default:
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g_assert_not_reached();
|
2017-05-01 23:20:43 +02:00
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}
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cpu_loop_exit_restore(cs, retaddr);
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}
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2006-04-27 23:07:38 +02:00
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#endif
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2012-09-02 12:37:06 +02:00
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void helper_ldtlb(CPUSH4State *env)
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2008-05-09 20:45:55 +02:00
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{
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#ifdef CONFIG_USER_ONLY
|
2019-03-23 03:26:42 +01:00
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cpu_abort(env_cpu(env), "Unhandled ldtlb");
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2008-05-09 20:45:55 +02:00
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#else
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cpu_load_tlb(env);
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#endif
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}
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2012-09-16 13:12:21 +02:00
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static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int index,
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uintptr_t retaddr)
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2008-08-30 01:01:41 +02:00
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{
|
2019-03-23 03:26:42 +01:00
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CPUState *cs = env_cpu(env);
|
2013-08-26 08:31:06 +02:00
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cs->exception_index = index;
|
2017-05-10 08:58:27 +02:00
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cpu_loop_exit_restore(cs, retaddr);
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2008-08-30 01:01:41 +02:00
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}
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2012-09-02 12:37:06 +02:00
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void helper_raise_illegal_instruction(CPUSH4State *env)
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2011-01-14 20:39:18 +01:00
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{
|
2012-09-16 13:12:21 +02:00
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raise_exception(env, 0x180, 0);
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2011-01-14 20:39:18 +01:00
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}
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2012-09-02 12:37:06 +02:00
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void helper_raise_slot_illegal_instruction(CPUSH4State *env)
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2008-08-30 01:01:41 +02:00
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{
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2012-09-16 13:12:21 +02:00
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raise_exception(env, 0x1a0, 0);
|
2008-08-30 01:01:41 +02:00
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}
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2012-09-02 12:37:06 +02:00
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void helper_raise_fpu_disable(CPUSH4State *env)
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2008-12-07 23:46:31 +01:00
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{
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2012-09-16 13:12:21 +02:00
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raise_exception(env, 0x800, 0);
|
2008-12-07 23:46:31 +01:00
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}
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2012-09-02 12:37:06 +02:00
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void helper_raise_slot_fpu_disable(CPUSH4State *env)
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2008-12-07 23:46:31 +01:00
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{
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2012-09-16 13:12:21 +02:00
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raise_exception(env, 0x820, 0);
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2008-12-07 23:46:31 +01:00
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}
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2012-09-16 13:12:21 +02:00
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void helper_sleep(CPUSH4State *env)
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2008-08-30 01:01:41 +02:00
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{
|
2019-03-23 03:26:42 +01:00
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CPUState *cs = env_cpu(env);
|
2013-01-17 18:51:17 +01:00
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cs->halted = 1;
|
2011-02-24 12:31:41 +01:00
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env->in_sleep = 1;
|
2012-09-16 13:12:21 +02:00
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raise_exception(env, EXCP_HLT, 0);
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2008-08-30 01:01:41 +02:00
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}
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2012-09-02 12:37:06 +02:00
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void helper_trapa(CPUSH4State *env, uint32_t tra)
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2008-08-30 01:01:41 +02:00
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{
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env->tra = tra << 2;
|
2012-09-16 13:12:21 +02:00
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raise_exception(env, 0x160, 0);
|
2008-08-30 01:01:41 +02:00
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}
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2017-07-18 22:02:31 +02:00
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void helper_exclusive(CPUSH4State *env)
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{
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/* We do not want cpu_restore_state to run. */
|
2019-03-23 00:07:18 +01:00
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cpu_loop_exit_atomic(env_cpu(env), 0);
|
2017-07-18 22:02:31 +02:00
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}
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2012-09-02 12:37:06 +02:00
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void helper_movcal(CPUSH4State *env, uint32_t address, uint32_t value)
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2009-04-02 01:10:46 +02:00
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{
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if (cpu_sh4_is_cached (env, address))
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{
|
2016-07-12 14:50:59 +02:00
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memory_content *r = g_new(memory_content, 1);
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2009-04-02 01:10:46 +02:00
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r->address = address;
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r->value = value;
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r->next = NULL;
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*(env->movcal_backup_tail) = r;
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env->movcal_backup_tail = &(r->next);
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}
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}
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2012-09-02 12:37:06 +02:00
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void helper_discard_movcal_backup(CPUSH4State *env)
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2009-04-02 01:10:46 +02:00
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{
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memory_content *current = env->movcal_backup;
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while(current)
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{
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memory_content *next = current->next;
|
2016-07-12 14:50:59 +02:00
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g_free(current);
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2009-04-02 01:10:46 +02:00
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env->movcal_backup = current = next;
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2009-09-21 20:11:34 +02:00
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if (current == NULL)
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2009-04-02 01:10:46 +02:00
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env->movcal_backup_tail = &(env->movcal_backup);
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}
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}
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2012-09-02 12:37:06 +02:00
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void helper_ocbi(CPUSH4State *env, uint32_t address)
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2009-04-02 01:10:46 +02:00
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{
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memory_content **current = &(env->movcal_backup);
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while (*current)
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{
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uint32_t a = (*current)->address;
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if ((a & ~0x1F) == (address & ~0x1F))
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{
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memory_content *next = (*current)->next;
|
2012-09-02 12:37:06 +02:00
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cpu_stl_data(env, a, (*current)->value);
|
2009-04-02 01:10:46 +02:00
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2009-09-21 20:11:34 +02:00
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if (next == NULL)
|
2009-04-02 01:10:46 +02:00
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{
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env->movcal_backup_tail = current;
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}
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|
2016-07-12 14:50:59 +02:00
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g_free(*current);
|
2009-04-02 01:10:46 +02:00
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*current = next;
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break;
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}
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}
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}
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2012-09-02 12:37:06 +02:00
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void helper_macl(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
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2006-04-27 23:07:38 +02:00
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{
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int64_t res;
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res = ((uint64_t) env->mach << 32) | env->macl;
|
2008-08-30 15:55:14 +02:00
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res += (int64_t) (int32_t) arg0 *(int64_t) (int32_t) arg1;
|
2006-04-27 23:07:38 +02:00
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env->mach = (res >> 32) & 0xffffffff;
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env->macl = res & 0xffffffff;
|
2015-05-25 01:28:56 +02:00
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if (env->sr & (1u << SR_S)) {
|
2006-04-27 23:07:38 +02:00
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if (res < 0)
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env->mach |= 0xffff0000;
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else
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env->mach &= 0x00007fff;
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}
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}
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|
2012-09-02 12:37:06 +02:00
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void helper_macw(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
|
2006-04-27 23:07:38 +02:00
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{
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int64_t res;
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res = ((uint64_t) env->mach << 32) | env->macl;
|
2008-08-30 15:55:14 +02:00
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res += (int64_t) (int16_t) arg0 *(int64_t) (int16_t) arg1;
|
2006-04-27 23:07:38 +02:00
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env->mach = (res >> 32) & 0xffffffff;
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env->macl = res & 0xffffffff;
|
2015-05-25 01:28:56 +02:00
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if (env->sr & (1u << SR_S)) {
|
2006-04-27 23:07:38 +02:00
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if (res < -0x80000000) {
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env->mach = 1;
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env->macl = 0x80000000;
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} else if (res > 0x000000007fffffff) {
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env->mach = 1;
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env->macl = 0x7fffffff;
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}
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}
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}
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|
2012-09-02 12:37:06 +02:00
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void helper_ld_fpscr(CPUSH4State *env, uint32_t val)
|
2008-08-31 00:07:52 +02:00
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{
|
2011-01-14 20:39:18 +01:00
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env->fpscr = val & FPSCR_MASK;
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if ((val & FPSCR_RM_MASK) == FPSCR_RM_ZERO) {
|
2008-08-31 00:07:52 +02:00
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set_float_rounding_mode(float_round_to_zero, &env->fp_status);
|
2011-01-14 20:39:18 +01:00
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} else {
|
2008-08-31 00:07:52 +02:00
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set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
|
2011-01-14 20:39:18 +01:00
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}
|
2011-01-14 20:39:18 +01:00
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set_flush_to_zero((val & FPSCR_DN) != 0, &env->fp_status);
|
2008-08-31 00:07:52 +02:00
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}
|
2008-09-02 00:11:56 +02:00
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|
2012-09-02 12:37:06 +02:00
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static void update_fpscr(CPUSH4State *env, uintptr_t retaddr)
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2011-01-14 20:39:18 +01:00
|
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{
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int xcpt, cause, enable;
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xcpt = get_float_exception_flags(&env->fp_status);
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|
2017-07-02 20:34:55 +02:00
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/* Clear the cause entries */
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env->fpscr &= ~FPSCR_CAUSE_MASK;
|
2011-01-14 20:39:18 +01:00
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if (unlikely(xcpt)) {
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if (xcpt & float_flag_invalid) {
|
2017-07-02 20:34:55 +02:00
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env->fpscr |= FPSCR_CAUSE_V;
|
2011-01-14 20:39:18 +01:00
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}
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|
if (xcpt & float_flag_divbyzero) {
|
2017-07-02 20:34:55 +02:00
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|
env->fpscr |= FPSCR_CAUSE_Z;
|
2011-01-14 20:39:18 +01:00
|
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}
|
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|
if (xcpt & float_flag_overflow) {
|
2017-07-02 20:34:55 +02:00
|
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|
env->fpscr |= FPSCR_CAUSE_O;
|
2011-01-14 20:39:18 +01:00
|
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|
}
|
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|
|
if (xcpt & float_flag_underflow) {
|
2017-07-02 20:34:55 +02:00
|
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|
env->fpscr |= FPSCR_CAUSE_U;
|
2011-01-14 20:39:18 +01:00
|
|
|
}
|
|
|
|
if (xcpt & float_flag_inexact) {
|
2017-07-02 20:34:55 +02:00
|
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|
env->fpscr |= FPSCR_CAUSE_I;
|
2011-01-14 20:39:18 +01:00
|
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}
|
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|
2017-07-02 20:34:55 +02:00
|
|
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/* Accumulate in flag entries */
|
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env->fpscr |= (env->fpscr & FPSCR_CAUSE_MASK)
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>> (FPSCR_CAUSE_SHIFT - FPSCR_FLAG_SHIFT);
|
2011-01-14 20:39:18 +01:00
|
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|
|
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|
|
/* Generate an exception if enabled */
|
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cause = (env->fpscr & FPSCR_CAUSE_MASK) >> FPSCR_CAUSE_SHIFT;
|
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|
|
enable = (env->fpscr & FPSCR_ENABLE_MASK) >> FPSCR_ENABLE_SHIFT;
|
|
|
|
if (cause & enable) {
|
2012-09-16 13:12:21 +02:00
|
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|
raise_exception(env, 0x120, retaddr);
|
2011-01-14 20:39:18 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-09-02 12:37:06 +02:00
|
|
|
float32 helper_fadd_FT(CPUSH4State *env, float32 t0, float32 t1)
|
2008-09-02 00:11:56 +02:00
|
|
|
{
|
2011-01-14 20:39:18 +01:00
|
|
|
set_float_exception_flags(0, &env->fp_status);
|
2011-04-10 21:09:12 +02:00
|
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|
t0 = float32_add(t0, t1, &env->fp_status);
|
2012-09-02 12:37:06 +02:00
|
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|
update_fpscr(env, GETPC());
|
2011-04-10 21:09:12 +02:00
|
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|
return t0;
|
2008-09-02 00:11:56 +02:00
|
|
|
}
|
|
|
|
|
2012-09-02 12:37:06 +02:00
|
|
|
float64 helper_fadd_DT(CPUSH4State *env, float64 t0, float64 t1)
|
2008-09-02 00:11:56 +02:00
|
|
|
{
|
2011-01-14 20:39:18 +01:00
|
|
|
set_float_exception_flags(0, &env->fp_status);
|
2011-04-10 21:09:12 +02:00
|
|
|
t0 = float64_add(t0, t1, &env->fp_status);
|
2012-09-02 12:37:06 +02:00
|
|
|
update_fpscr(env, GETPC());
|
2011-04-10 21:09:12 +02:00
|
|
|
return t0;
|
2008-09-02 00:11:56 +02:00
|
|
|
}
|
|
|
|
|
2017-07-02 21:31:25 +02:00
|
|
|
uint32_t helper_fcmp_eq_FT(CPUSH4State *env, float32 t0, float32 t1)
|
2008-09-02 00:11:56 +02:00
|
|
|
{
|
2011-01-14 20:39:18 +01:00
|
|
|
int relation;
|
2008-11-19 19:00:39 +01:00
|
|
|
|
2011-01-14 20:39:18 +01:00
|
|
|
set_float_exception_flags(0, &env->fp_status);
|
2011-04-10 21:09:12 +02:00
|
|
|
relation = float32_compare(t0, t1, &env->fp_status);
|
2017-07-02 21:23:56 +02:00
|
|
|
update_fpscr(env, GETPC());
|
2017-07-02 21:31:25 +02:00
|
|
|
return relation == float_relation_equal;
|
2008-09-02 00:11:56 +02:00
|
|
|
}
|
|
|
|
|
2017-07-02 21:31:25 +02:00
|
|
|
uint32_t helper_fcmp_eq_DT(CPUSH4State *env, float64 t0, float64 t1)
|
2008-09-02 00:11:56 +02:00
|
|
|
{
|
2011-01-14 20:39:18 +01:00
|
|
|
int relation;
|
2008-11-19 19:00:39 +01:00
|
|
|
|
2011-01-14 20:39:18 +01:00
|
|
|
set_float_exception_flags(0, &env->fp_status);
|
2011-04-10 21:09:12 +02:00
|
|
|
relation = float64_compare(t0, t1, &env->fp_status);
|
2017-07-02 21:23:56 +02:00
|
|
|
update_fpscr(env, GETPC());
|
2017-07-02 21:31:25 +02:00
|
|
|
return relation == float_relation_equal;
|
2008-09-02 00:11:56 +02:00
|
|
|
}
|
|
|
|
|
2017-07-02 21:31:25 +02:00
|
|
|
uint32_t helper_fcmp_gt_FT(CPUSH4State *env, float32 t0, float32 t1)
|
2008-09-02 00:11:56 +02:00
|
|
|
{
|
2011-01-14 20:39:18 +01:00
|
|
|
int relation;
|
2008-11-19 19:00:39 +01:00
|
|
|
|
2011-01-14 20:39:18 +01:00
|
|
|
set_float_exception_flags(0, &env->fp_status);
|
2011-04-10 21:09:12 +02:00
|
|
|
relation = float32_compare(t0, t1, &env->fp_status);
|
2017-07-02 21:23:56 +02:00
|
|
|
update_fpscr(env, GETPC());
|
2017-07-02 21:31:25 +02:00
|
|
|
return relation == float_relation_greater;
|
2008-09-02 00:11:56 +02:00
|
|
|
}
|
|
|
|
|
2017-07-02 21:31:25 +02:00
|
|
|
uint32_t helper_fcmp_gt_DT(CPUSH4State *env, float64 t0, float64 t1)
|
2008-09-02 00:11:56 +02:00
|
|
|
{
|
2011-01-14 20:39:18 +01:00
|
|
|
int relation;
|
2008-11-19 19:00:39 +01:00
|
|
|
|
2011-01-14 20:39:18 +01:00
|
|
|
set_float_exception_flags(0, &env->fp_status);
|
2011-04-10 21:09:12 +02:00
|
|
|
relation = float64_compare(t0, t1, &env->fp_status);
|
2017-07-02 21:23:56 +02:00
|
|
|
update_fpscr(env, GETPC());
|
2017-07-02 21:31:25 +02:00
|
|
|
return relation == float_relation_greater;
|
2008-09-02 00:11:56 +02:00
|
|
|
}
|
|
|
|
|
2012-09-02 12:37:06 +02:00
|
|
|
float64 helper_fcnvsd_FT_DT(CPUSH4State *env, float32 t0)
|
2008-09-02 00:11:56 +02:00
|
|
|
{
|
2011-04-10 21:09:12 +02:00
|
|
|
float64 ret;
|
2011-01-14 20:39:18 +01:00
|
|
|
set_float_exception_flags(0, &env->fp_status);
|
2011-04-10 21:09:12 +02:00
|
|
|
ret = float32_to_float64(t0, &env->fp_status);
|
2012-09-02 12:37:06 +02:00
|
|
|
update_fpscr(env, GETPC());
|
2011-04-10 21:09:12 +02:00
|
|
|
return ret;
|
2008-09-02 00:11:56 +02:00
|
|
|
}
|
|
|
|
|
2012-09-02 12:37:06 +02:00
|
|
|
float32 helper_fcnvds_DT_FT(CPUSH4State *env, float64 t0)
|
2008-09-02 00:11:56 +02:00
|
|
|
{
|
2011-04-10 21:09:12 +02:00
|
|
|
float32 ret;
|
2011-01-14 20:39:18 +01:00
|
|
|
set_float_exception_flags(0, &env->fp_status);
|
2011-04-10 21:09:12 +02:00
|
|
|
ret = float64_to_float32(t0, &env->fp_status);
|
2012-09-02 12:37:06 +02:00
|
|
|
update_fpscr(env, GETPC());
|
2011-04-10 21:09:12 +02:00
|
|
|
return ret;
|
2008-09-02 00:11:56 +02:00
|
|
|
}
|
|
|
|
|
2012-09-02 12:37:06 +02:00
|
|
|
float32 helper_fdiv_FT(CPUSH4State *env, float32 t0, float32 t1)
|
2008-09-02 00:11:56 +02:00
|
|
|
{
|
2011-01-14 20:39:18 +01:00
|
|
|
set_float_exception_flags(0, &env->fp_status);
|
2011-04-10 21:09:12 +02:00
|
|
|
t0 = float32_div(t0, t1, &env->fp_status);
|
2012-09-02 12:37:06 +02:00
|
|
|
update_fpscr(env, GETPC());
|
2011-04-10 21:09:12 +02:00
|
|
|
return t0;
|
2008-09-02 00:11:56 +02:00
|
|
|
}
|
|
|
|
|
2012-09-02 12:37:06 +02:00
|
|
|
float64 helper_fdiv_DT(CPUSH4State *env, float64 t0, float64 t1)
|
2008-09-02 00:11:56 +02:00
|
|
|
{
|
2011-01-14 20:39:18 +01:00
|
|
|
set_float_exception_flags(0, &env->fp_status);
|
2011-04-10 21:09:12 +02:00
|
|
|
t0 = float64_div(t0, t1, &env->fp_status);
|
2012-09-02 12:37:06 +02:00
|
|
|
update_fpscr(env, GETPC());
|
2011-04-10 21:09:12 +02:00
|
|
|
return t0;
|
2008-09-02 00:11:56 +02:00
|
|
|
}
|
|
|
|
|
2012-09-02 12:37:06 +02:00
|
|
|
float32 helper_float_FT(CPUSH4State *env, uint32_t t0)
|
2008-09-02 00:11:56 +02:00
|
|
|
{
|
2011-04-10 21:09:12 +02:00
|
|
|
float32 ret;
|
2011-01-14 20:39:18 +01:00
|
|
|
set_float_exception_flags(0, &env->fp_status);
|
2011-04-10 21:09:12 +02:00
|
|
|
ret = int32_to_float32(t0, &env->fp_status);
|
2012-09-02 12:37:06 +02:00
|
|
|
update_fpscr(env, GETPC());
|
2011-04-10 21:09:12 +02:00
|
|
|
return ret;
|
2008-09-02 00:11:56 +02:00
|
|
|
}
|
|
|
|
|
2012-09-02 12:37:06 +02:00
|
|
|
float64 helper_float_DT(CPUSH4State *env, uint32_t t0)
|
2008-09-02 00:11:56 +02:00
|
|
|
{
|
2011-04-10 21:09:12 +02:00
|
|
|
float64 ret;
|
2011-01-14 20:39:18 +01:00
|
|
|
set_float_exception_flags(0, &env->fp_status);
|
2011-04-10 21:09:12 +02:00
|
|
|
ret = int32_to_float64(t0, &env->fp_status);
|
2012-09-02 12:37:06 +02:00
|
|
|
update_fpscr(env, GETPC());
|
2011-04-10 21:09:12 +02:00
|
|
|
return ret;
|
2008-09-02 00:11:56 +02:00
|
|
|
}
|
|
|
|
|
2012-09-02 12:37:06 +02:00
|
|
|
float32 helper_fmac_FT(CPUSH4State *env, float32 t0, float32 t1, float32 t2)
|
2009-01-14 22:02:59 +01:00
|
|
|
{
|
2011-01-14 20:39:18 +01:00
|
|
|
set_float_exception_flags(0, &env->fp_status);
|
2012-09-16 13:12:20 +02:00
|
|
|
t0 = float32_muladd(t0, t1, t2, 0, &env->fp_status);
|
2012-09-02 12:37:06 +02:00
|
|
|
update_fpscr(env, GETPC());
|
2011-04-10 21:09:12 +02:00
|
|
|
return t0;
|
2009-01-14 22:02:59 +01:00
|
|
|
}
|
|
|
|
|
2012-09-02 12:37:06 +02:00
|
|
|
float32 helper_fmul_FT(CPUSH4State *env, float32 t0, float32 t1)
|
2008-09-02 00:11:56 +02:00
|
|
|
{
|
2011-01-14 20:39:18 +01:00
|
|
|
set_float_exception_flags(0, &env->fp_status);
|
2011-04-10 21:09:12 +02:00
|
|
|
t0 = float32_mul(t0, t1, &env->fp_status);
|
2012-09-02 12:37:06 +02:00
|
|
|
update_fpscr(env, GETPC());
|
2011-04-10 21:09:12 +02:00
|
|
|
return t0;
|
2008-09-02 00:11:56 +02:00
|
|
|
}
|
|
|
|
|
2012-09-02 12:37:06 +02:00
|
|
|
float64 helper_fmul_DT(CPUSH4State *env, float64 t0, float64 t1)
|
2008-09-02 00:11:56 +02:00
|
|
|
{
|
2011-01-14 20:39:18 +01:00
|
|
|
set_float_exception_flags(0, &env->fp_status);
|
2011-04-10 21:09:12 +02:00
|
|
|
t0 = float64_mul(t0, t1, &env->fp_status);
|
2012-09-02 12:37:06 +02:00
|
|
|
update_fpscr(env, GETPC());
|
2011-04-10 21:09:12 +02:00
|
|
|
return t0;
|
2008-09-02 00:11:56 +02:00
|
|
|
}
|
|
|
|
|
2012-09-02 12:37:06 +02:00
|
|
|
float32 helper_fsqrt_FT(CPUSH4State *env, float32 t0)
|
2008-09-02 00:11:56 +02:00
|
|
|
{
|
2011-01-14 20:39:18 +01:00
|
|
|
set_float_exception_flags(0, &env->fp_status);
|
2011-04-10 21:09:12 +02:00
|
|
|
t0 = float32_sqrt(t0, &env->fp_status);
|
2012-09-02 12:37:06 +02:00
|
|
|
update_fpscr(env, GETPC());
|
2011-04-10 21:09:12 +02:00
|
|
|
return t0;
|
2008-09-02 00:11:56 +02:00
|
|
|
}
|
|
|
|
|
2012-09-02 12:37:06 +02:00
|
|
|
float64 helper_fsqrt_DT(CPUSH4State *env, float64 t0)
|
2008-09-02 00:11:56 +02:00
|
|
|
{
|
2011-01-14 20:39:18 +01:00
|
|
|
set_float_exception_flags(0, &env->fp_status);
|
2011-04-10 21:09:12 +02:00
|
|
|
t0 = float64_sqrt(t0, &env->fp_status);
|
2012-09-02 12:37:06 +02:00
|
|
|
update_fpscr(env, GETPC());
|
2011-04-10 21:09:12 +02:00
|
|
|
return t0;
|
2008-09-02 00:11:56 +02:00
|
|
|
}
|
|
|
|
|
2017-07-18 22:02:51 +02:00
|
|
|
float32 helper_fsrra_FT(CPUSH4State *env, float32 t0)
|
|
|
|
{
|
|
|
|
set_float_exception_flags(0, &env->fp_status);
|
|
|
|
/* "Approximate" 1/sqrt(x) via actual computation. */
|
|
|
|
t0 = float32_sqrt(t0, &env->fp_status);
|
|
|
|
t0 = float32_div(float32_one, t0, &env->fp_status);
|
2020-10-27 00:13:00 +01:00
|
|
|
/*
|
|
|
|
* Since this is supposed to be an approximation, an imprecision
|
|
|
|
* exception is required. One supposes this also follows the usual
|
2020-10-09 08:44:44 +02:00
|
|
|
* IEEE rule that other exceptions take precedence.
|
2020-10-27 00:13:00 +01:00
|
|
|
*/
|
2017-07-18 22:02:51 +02:00
|
|
|
if (get_float_exception_flags(&env->fp_status) == 0) {
|
|
|
|
set_float_exception_flags(float_flag_inexact, &env->fp_status);
|
|
|
|
}
|
|
|
|
update_fpscr(env, GETPC());
|
|
|
|
return t0;
|
|
|
|
}
|
|
|
|
|
2012-09-02 12:37:06 +02:00
|
|
|
float32 helper_fsub_FT(CPUSH4State *env, float32 t0, float32 t1)
|
2008-09-02 00:11:56 +02:00
|
|
|
{
|
2011-01-14 20:39:18 +01:00
|
|
|
set_float_exception_flags(0, &env->fp_status);
|
2011-04-10 21:09:12 +02:00
|
|
|
t0 = float32_sub(t0, t1, &env->fp_status);
|
2012-09-02 12:37:06 +02:00
|
|
|
update_fpscr(env, GETPC());
|
2011-04-10 21:09:12 +02:00
|
|
|
return t0;
|
2008-09-02 00:11:56 +02:00
|
|
|
}
|
|
|
|
|
2012-09-02 12:37:06 +02:00
|
|
|
float64 helper_fsub_DT(CPUSH4State *env, float64 t0, float64 t1)
|
2008-09-02 00:11:56 +02:00
|
|
|
{
|
2011-01-14 20:39:18 +01:00
|
|
|
set_float_exception_flags(0, &env->fp_status);
|
2011-04-10 21:09:12 +02:00
|
|
|
t0 = float64_sub(t0, t1, &env->fp_status);
|
2012-09-02 12:37:06 +02:00
|
|
|
update_fpscr(env, GETPC());
|
2011-04-10 21:09:12 +02:00
|
|
|
return t0;
|
2008-09-02 00:11:56 +02:00
|
|
|
}
|
|
|
|
|
2012-09-02 12:37:06 +02:00
|
|
|
uint32_t helper_ftrc_FT(CPUSH4State *env, float32 t0)
|
2008-09-02 00:11:56 +02:00
|
|
|
{
|
2011-01-14 20:39:18 +01:00
|
|
|
uint32_t ret;
|
|
|
|
set_float_exception_flags(0, &env->fp_status);
|
2011-04-10 21:09:12 +02:00
|
|
|
ret = float32_to_int32_round_to_zero(t0, &env->fp_status);
|
2012-09-02 12:37:06 +02:00
|
|
|
update_fpscr(env, GETPC());
|
2011-01-14 20:39:18 +01:00
|
|
|
return ret;
|
2008-09-02 00:11:56 +02:00
|
|
|
}
|
|
|
|
|
2012-09-02 12:37:06 +02:00
|
|
|
uint32_t helper_ftrc_DT(CPUSH4State *env, float64 t0)
|
2008-09-02 00:11:56 +02:00
|
|
|
{
|
2011-01-14 20:39:18 +01:00
|
|
|
uint32_t ret;
|
|
|
|
set_float_exception_flags(0, &env->fp_status);
|
2011-04-10 21:09:12 +02:00
|
|
|
ret = float64_to_int32_round_to_zero(t0, &env->fp_status);
|
2012-09-02 12:37:06 +02:00
|
|
|
update_fpscr(env, GETPC());
|
2011-01-14 20:39:18 +01:00
|
|
|
return ret;
|
2008-09-02 00:11:56 +02:00
|
|
|
}
|
2011-01-14 20:39:18 +01:00
|
|
|
|
2012-09-02 12:37:06 +02:00
|
|
|
void helper_fipr(CPUSH4State *env, uint32_t m, uint32_t n)
|
2011-01-14 20:39:18 +01:00
|
|
|
{
|
|
|
|
int bank, i;
|
|
|
|
float32 r, p;
|
|
|
|
|
|
|
|
bank = (env->sr & FPSCR_FR) ? 16 : 0;
|
|
|
|
r = float32_zero;
|
|
|
|
set_float_exception_flags(0, &env->fp_status);
|
|
|
|
|
|
|
|
for (i = 0 ; i < 4 ; i++) {
|
|
|
|
p = float32_mul(env->fregs[bank + m + i],
|
|
|
|
env->fregs[bank + n + i],
|
|
|
|
&env->fp_status);
|
|
|
|
r = float32_add(r, p, &env->fp_status);
|
|
|
|
}
|
2012-09-02 12:37:06 +02:00
|
|
|
update_fpscr(env, GETPC());
|
2011-01-14 20:39:18 +01:00
|
|
|
|
|
|
|
env->fregs[bank + n + 3] = r;
|
|
|
|
}
|
2011-01-14 20:39:18 +01:00
|
|
|
|
2012-09-02 12:37:06 +02:00
|
|
|
void helper_ftrv(CPUSH4State *env, uint32_t n)
|
2011-01-14 20:39:18 +01:00
|
|
|
{
|
|
|
|
int bank_matrix, bank_vector;
|
|
|
|
int i, j;
|
|
|
|
float32 r[4];
|
|
|
|
float32 p;
|
|
|
|
|
|
|
|
bank_matrix = (env->sr & FPSCR_FR) ? 0 : 16;
|
|
|
|
bank_vector = (env->sr & FPSCR_FR) ? 16 : 0;
|
|
|
|
set_float_exception_flags(0, &env->fp_status);
|
|
|
|
for (i = 0 ; i < 4 ; i++) {
|
|
|
|
r[i] = float32_zero;
|
|
|
|
for (j = 0 ; j < 4 ; j++) {
|
|
|
|
p = float32_mul(env->fregs[bank_matrix + 4 * j + i],
|
|
|
|
env->fregs[bank_vector + j],
|
|
|
|
&env->fp_status);
|
|
|
|
r[i] = float32_add(r[i], p, &env->fp_status);
|
|
|
|
}
|
|
|
|
}
|
2012-09-02 12:37:06 +02:00
|
|
|
update_fpscr(env, GETPC());
|
2011-01-14 20:39:18 +01:00
|
|
|
|
|
|
|
for (i = 0 ; i < 4 ; i++) {
|
|
|
|
env->fregs[bank_vector + i] = r[i];
|
|
|
|
}
|
|
|
|
}
|