2008-12-03 00:53:50 +01:00
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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2009-07-16 22:47:01 +02:00
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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2008-12-03 00:53:50 +01:00
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*
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* Copyright IBM Corp. 2008
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*
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* Authors: Hollis Blanchard <hollisb@us.ibm.com>
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*/
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2022-08-17 17:08:43 +02:00
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/*
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* This file implements emulation of the 32-bit PCI controller found in some
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* 4xx SoCs, such as the 440EP.
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*/
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2008-12-03 00:53:50 +01:00
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2016-01-26 19:16:58 +01:00
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#include "qemu/osdep.h"
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2022-01-04 07:55:34 +01:00
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#include "qemu/log.h"
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2019-08-12 07:23:42 +02:00
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#include "hw/irq.h"
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2013-02-05 17:06:20 +01:00
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#include "hw/ppc/ppc.h"
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#include "hw/ppc/ppc4xx.h"
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2019-08-12 07:23:45 +02:00
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#include "migration/vmstate.h"
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2019-05-23 16:35:07 +02:00
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#include "qemu/module.h"
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2019-08-12 07:23:38 +02:00
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#include "sysemu/reset.h"
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2013-02-04 15:40:22 +01:00
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_host.h"
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2017-02-10 10:27:23 +01:00
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#include "trace.h"
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2020-09-03 22:43:22 +02:00
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#include "qom/object.h"
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2008-12-03 00:53:50 +01:00
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struct PCIMasterMap {
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uint32_t la;
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uint32_t ma;
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uint32_t pcila;
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uint32_t pciha;
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};
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struct PCITargetMap {
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uint32_t ms;
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uint32_t la;
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};
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2020-09-16 20:25:19 +02:00
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OBJECT_DECLARE_SIMPLE_TYPE(PPC4xxPCIState, PPC4xx_PCI_HOST_BRIDGE)
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2012-08-20 19:08:02 +02:00
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2008-12-03 00:53:50 +01:00
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#define PPC4xx_PCI_NR_PMMS 3
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#define PPC4xx_PCI_NR_PTMS 2
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2021-10-19 11:18:17 +02:00
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#define PPC4xx_PCI_NUM_DEVS 5
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2008-12-03 00:53:50 +01:00
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struct PPC4xxPCIState {
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2012-08-20 19:08:09 +02:00
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PCIHostState parent_obj;
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2012-01-10 19:36:26 +01:00
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2008-12-03 00:53:50 +01:00
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struct PCIMasterMap pmm[PPC4xx_PCI_NR_PMMS];
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struct PCITargetMap ptm[PPC4xx_PCI_NR_PTMS];
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2021-10-19 11:18:17 +02:00
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qemu_irq irq[PPC4xx_PCI_NUM_DEVS];
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2008-12-03 00:53:50 +01:00
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2012-01-10 19:36:26 +01:00
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MemoryRegion container;
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MemoryRegion iomem;
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2008-12-03 00:53:50 +01:00
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};
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#define PCIC0_CFGADDR 0x0
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#define PCIC0_CFGDATA 0x4
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2022-08-17 17:08:43 +02:00
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/*
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* PLB Memory Map (PMM) registers specify which PLB addresses are translated to
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* PCI accesses.
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*/
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2008-12-03 00:53:50 +01:00
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#define PCIL0_PMM0LA 0x0
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#define PCIL0_PMM0MA 0x4
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#define PCIL0_PMM0PCILA 0x8
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#define PCIL0_PMM0PCIHA 0xc
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#define PCIL0_PMM1LA 0x10
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#define PCIL0_PMM1MA 0x14
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#define PCIL0_PMM1PCILA 0x18
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#define PCIL0_PMM1PCIHA 0x1c
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#define PCIL0_PMM2LA 0x20
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#define PCIL0_PMM2MA 0x24
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#define PCIL0_PMM2PCILA 0x28
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#define PCIL0_PMM2PCIHA 0x2c
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2022-08-17 17:08:43 +02:00
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/*
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* PCI Target Map (PTM) registers specify which PCI addresses are translated to
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* PLB accesses.
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*/
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2008-12-03 00:53:50 +01:00
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#define PCIL0_PTM1MS 0x30
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#define PCIL0_PTM1LA 0x34
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#define PCIL0_PTM2MS 0x38
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#define PCIL0_PTM2LA 0x3c
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2012-01-10 19:36:26 +01:00
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#define PCI_REG_BASE 0x800000
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2008-12-03 00:53:50 +01:00
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#define PCI_REG_SIZE 0x40
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2012-01-10 19:36:26 +01:00
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#define PCI_ALL_SIZE (PCI_REG_BASE + PCI_REG_SIZE)
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2008-12-03 00:53:50 +01:00
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2012-10-23 12:30:10 +02:00
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static void ppc4xx_pci_reg_write4(void *opaque, hwaddr offset,
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2011-11-20 10:44:37 +01:00
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uint64_t value, unsigned size)
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2008-12-03 00:53:50 +01:00
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{
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struct PPC4xxPCIState *pci = opaque;
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2022-08-17 17:08:43 +02:00
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/*
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* We ignore all target attempts at PCI configuration, effectively
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* assuming a bidirectional 1:1 mapping of PLB and PCI space.
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*/
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2008-12-03 00:53:50 +01:00
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switch (offset) {
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case PCIL0_PMM0LA:
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pci->pmm[0].la = value;
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break;
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case PCIL0_PMM0MA:
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pci->pmm[0].ma = value;
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break;
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case PCIL0_PMM0PCIHA:
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pci->pmm[0].pciha = value;
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break;
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case PCIL0_PMM0PCILA:
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pci->pmm[0].pcila = value;
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break;
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case PCIL0_PMM1LA:
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pci->pmm[1].la = value;
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break;
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case PCIL0_PMM1MA:
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pci->pmm[1].ma = value;
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break;
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case PCIL0_PMM1PCIHA:
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pci->pmm[1].pciha = value;
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break;
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case PCIL0_PMM1PCILA:
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pci->pmm[1].pcila = value;
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break;
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case PCIL0_PMM2LA:
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pci->pmm[2].la = value;
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break;
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case PCIL0_PMM2MA:
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pci->pmm[2].ma = value;
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break;
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case PCIL0_PMM2PCIHA:
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pci->pmm[2].pciha = value;
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break;
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case PCIL0_PMM2PCILA:
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pci->pmm[2].pcila = value;
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break;
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case PCIL0_PTM1MS:
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pci->ptm[0].ms = value;
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break;
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case PCIL0_PTM1LA:
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pci->ptm[0].la = value;
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break;
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case PCIL0_PTM2MS:
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pci->ptm[1].ms = value;
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break;
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case PCIL0_PTM2LA:
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pci->ptm[1].la = value;
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break;
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default:
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2022-01-04 07:55:34 +01:00
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: unhandled PCI internal register 0x%" HWADDR_PRIx "\n",
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__func__, offset);
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2008-12-03 00:53:50 +01:00
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break;
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}
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}
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2012-10-23 12:30:10 +02:00
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static uint64_t ppc4xx_pci_reg_read4(void *opaque, hwaddr offset,
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2011-11-20 10:44:37 +01:00
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unsigned size)
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2008-12-03 00:53:50 +01:00
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{
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struct PPC4xxPCIState *pci = opaque;
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uint32_t value;
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switch (offset) {
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case PCIL0_PMM0LA:
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value = pci->pmm[0].la;
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break;
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case PCIL0_PMM0MA:
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value = pci->pmm[0].ma;
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break;
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case PCIL0_PMM0PCIHA:
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value = pci->pmm[0].pciha;
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break;
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case PCIL0_PMM0PCILA:
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value = pci->pmm[0].pcila;
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break;
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case PCIL0_PMM1LA:
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value = pci->pmm[1].la;
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break;
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case PCIL0_PMM1MA:
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value = pci->pmm[1].ma;
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break;
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case PCIL0_PMM1PCIHA:
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value = pci->pmm[1].pciha;
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break;
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case PCIL0_PMM1PCILA:
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value = pci->pmm[1].pcila;
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break;
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case PCIL0_PMM2LA:
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value = pci->pmm[2].la;
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break;
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case PCIL0_PMM2MA:
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value = pci->pmm[2].ma;
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break;
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case PCIL0_PMM2PCIHA:
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value = pci->pmm[2].pciha;
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break;
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case PCIL0_PMM2PCILA:
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value = pci->pmm[2].pcila;
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break;
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case PCIL0_PTM1MS:
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value = pci->ptm[0].ms;
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break;
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case PCIL0_PTM1LA:
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value = pci->ptm[0].la;
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break;
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case PCIL0_PTM2MS:
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value = pci->ptm[1].ms;
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break;
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case PCIL0_PTM2LA:
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value = pci->ptm[1].la;
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break;
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default:
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2022-01-04 07:55:34 +01:00
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: invalid PCI internal register 0x%" HWADDR_PRIx "\n",
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__func__, offset);
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2008-12-03 00:53:50 +01:00
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value = 0;
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}
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return value;
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}
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2011-11-20 10:44:37 +01:00
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static const MemoryRegionOps pci_reg_ops = {
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.read = ppc4xx_pci_reg_read4,
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.write = ppc4xx_pci_reg_write4,
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.endianness = DEVICE_LITTLE_ENDIAN,
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2008-12-03 00:53:50 +01:00
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};
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static void ppc4xx_pci_reset(void *opaque)
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{
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struct PPC4xxPCIState *pci = opaque;
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memset(pci->pmm, 0, sizeof(pci->pmm));
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memset(pci->ptm, 0, sizeof(pci->ptm));
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}
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2022-08-17 17:08:43 +02:00
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/*
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* On Bamboo, all pins from each slot are tied to a single board IRQ.
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* This may need further refactoring for other boards.
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*/
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2008-12-03 00:53:50 +01:00
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static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
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{
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2020-10-11 17:04:23 +02:00
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int slot = PCI_SLOT(pci_dev->devfn);
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2008-12-03 00:53:50 +01:00
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2017-02-10 10:27:23 +01:00
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trace_ppc4xx_pci_map_irq(pci_dev->devfn, irq_num, slot);
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2008-12-03 00:53:50 +01:00
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2021-10-19 11:18:17 +02:00
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return slot > 0 ? slot - 1 : PPC4xx_PCI_NUM_DEVS - 1;
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2008-12-03 00:53:50 +01:00
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}
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2009-08-28 15:28:17 +02:00
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static void ppc4xx_pci_set_irq(void *opaque, int irq_num, int level)
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2008-12-03 00:53:50 +01:00
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{
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2009-08-28 15:28:17 +02:00
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qemu_irq *pci_irqs = opaque;
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2017-02-10 10:27:23 +01:00
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trace_ppc4xx_pci_set_irq(irq_num);
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2021-10-19 11:18:17 +02:00
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assert(irq_num >= 0 && irq_num < PPC4xx_PCI_NUM_DEVS);
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2008-12-03 00:53:50 +01:00
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qemu_set_irq(pci_irqs[irq_num], level);
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}
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2010-12-02 17:27:49 +01:00
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static const VMStateDescription vmstate_pci_master_map = {
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.name = "pci_master_map",
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.version_id = 0,
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.minimum_version_id = 0,
|
2014-04-16 15:24:04 +02:00
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.fields = (VMStateField[]) {
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2010-12-02 17:27:49 +01:00
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VMSTATE_UINT32(la, struct PCIMasterMap),
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VMSTATE_UINT32(ma, struct PCIMasterMap),
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VMSTATE_UINT32(pcila, struct PCIMasterMap),
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VMSTATE_UINT32(pciha, struct PCIMasterMap),
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VMSTATE_END_OF_LIST()
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2008-12-03 00:53:50 +01:00
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}
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2010-12-02 17:27:49 +01:00
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};
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2008-12-03 00:53:50 +01:00
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2010-12-02 17:27:49 +01:00
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static const VMStateDescription vmstate_pci_target_map = {
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.name = "pci_target_map",
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.version_id = 0,
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.minimum_version_id = 0,
|
2014-04-16 15:24:04 +02:00
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.fields = (VMStateField[]) {
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2010-12-02 17:27:49 +01:00
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VMSTATE_UINT32(ms, struct PCITargetMap),
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VMSTATE_UINT32(la, struct PCITargetMap),
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VMSTATE_END_OF_LIST()
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2008-12-03 00:53:50 +01:00
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}
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2010-12-02 17:27:49 +01:00
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};
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2008-12-03 00:53:50 +01:00
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2010-12-02 17:27:49 +01:00
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static const VMStateDescription vmstate_ppc4xx_pci = {
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.name = "ppc4xx_pci",
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.version_id = 1,
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.minimum_version_id = 1,
|
2014-04-16 15:24:04 +02:00
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.fields = (VMStateField[]) {
|
2010-12-02 17:27:49 +01:00
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VMSTATE_STRUCT_ARRAY(pmm, PPC4xxPCIState, PPC4xx_PCI_NR_PMMS, 1,
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vmstate_pci_master_map,
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struct PCIMasterMap),
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VMSTATE_STRUCT_ARRAY(ptm, PPC4xxPCIState, PPC4xx_PCI_NR_PTMS, 1,
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vmstate_pci_target_map,
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struct PCITargetMap),
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VMSTATE_END_OF_LIST()
|
2008-12-03 00:53:50 +01:00
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}
|
2010-12-02 17:27:49 +01:00
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|
};
|
2008-12-03 00:53:50 +01:00
|
|
|
|
|
|
|
/* XXX Interrupt acknowledge cycles not supported. */
|
2018-10-01 13:44:21 +02:00
|
|
|
static void ppc4xx_pcihost_realize(DeviceState *dev, Error **errp)
|
2012-01-10 19:36:26 +01:00
|
|
|
{
|
2018-10-01 13:44:21 +02:00
|
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
|
2012-01-10 19:36:26 +01:00
|
|
|
PPC4xxPCIState *s;
|
|
|
|
PCIHostState *h;
|
|
|
|
PCIBus *b;
|
|
|
|
int i;
|
|
|
|
|
2012-08-20 19:08:08 +02:00
|
|
|
h = PCI_HOST_BRIDGE(dev);
|
2012-08-20 19:08:02 +02:00
|
|
|
s = PPC4xx_PCI_HOST_BRIDGE(dev);
|
2012-01-10 19:36:26 +01:00
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
|
2018-10-01 13:44:21 +02:00
|
|
|
sysbus_init_irq(sbd, &s->irq[i]);
|
2012-01-10 19:36:26 +01:00
|
|
|
}
|
|
|
|
|
2018-10-01 13:44:21 +02:00
|
|
|
b = pci_register_root_bus(dev, NULL, ppc4xx_pci_set_irq,
|
2017-11-29 09:46:22 +01:00
|
|
|
ppc4xx_pci_map_irq, s->irq, get_system_memory(),
|
2020-09-01 12:40:41 +02:00
|
|
|
get_system_io(), 0, ARRAY_SIZE(s->irq),
|
|
|
|
TYPE_PCI_BUS);
|
2012-08-20 19:08:02 +02:00
|
|
|
h->bus = b;
|
2012-01-10 19:36:26 +01:00
|
|
|
|
|
|
|
pci_create_simple(b, 0, "ppc4xx-host-bridge");
|
|
|
|
|
|
|
|
/* XXX split into 2 memory regions, one for config space, one for regs */
|
2013-06-07 03:25:08 +02:00
|
|
|
memory_region_init(&s->container, OBJECT(s), "pci-container", PCI_ALL_SIZE);
|
|
|
|
memory_region_init_io(&h->conf_mem, OBJECT(s), &pci_host_conf_le_ops, h,
|
2012-01-10 19:36:26 +01:00
|
|
|
"pci-conf-idx", 4);
|
2013-06-07 03:25:08 +02:00
|
|
|
memory_region_init_io(&h->data_mem, OBJECT(s), &pci_host_data_le_ops, h,
|
2012-01-10 19:36:26 +01:00
|
|
|
"pci-conf-data", 4);
|
2013-06-07 03:25:08 +02:00
|
|
|
memory_region_init_io(&s->iomem, OBJECT(s), &pci_reg_ops, s,
|
2012-01-10 19:36:26 +01:00
|
|
|
"pci.reg", PCI_REG_SIZE);
|
|
|
|
memory_region_add_subregion(&s->container, PCIC0_CFGADDR, &h->conf_mem);
|
|
|
|
memory_region_add_subregion(&s->container, PCIC0_CFGDATA, &h->data_mem);
|
|
|
|
memory_region_add_subregion(&s->container, PCI_REG_BASE, &s->iomem);
|
2018-10-01 13:44:21 +02:00
|
|
|
sysbus_init_mmio(sbd, &s->container);
|
2012-01-10 19:36:26 +01:00
|
|
|
qemu_register_reset(ppc4xx_pci_reset, s);
|
|
|
|
}
|
|
|
|
|
2011-12-04 19:22:06 +01:00
|
|
|
static void ppc4xx_host_bridge_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
2011-12-08 04:34:16 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2011-12-04 19:22:06 +01:00
|
|
|
|
2011-12-08 04:34:16 +01:00
|
|
|
dc->desc = "Host bridge";
|
2011-12-04 19:22:06 +01:00
|
|
|
k->vendor_id = PCI_VENDOR_ID_IBM;
|
|
|
|
k->device_id = PCI_DEVICE_ID_IBM_440GX;
|
|
|
|
k->class_id = PCI_CLASS_BRIDGE_OTHER;
|
pci-host: Consistently set cannot_instantiate_with_device_add_yet
Many PCI host bridges consist of a sysbus device and a PCI device.
You need both for the thing to work. Arguably, these bridges should
be modelled as a single, composite devices instead of pairs of
seemingly independent devices you can only use together, but we're not
there, yet.
Since the sysbus part can't be instantiated with device_add, yet,
permitting it with the PCI part is useless. We shouldn't offer
useless options to the user, so let's set
cannot_instantiate_with_device_add_yet for them.
It's already set for Bonito, Grackle, i440FX and Raven. Document why.
Set it for the others: dec-21154, e500-host-bridge, gt64120_pci, mch,
pbm-pci, ppc4xx-host-bridge, sh_pci_host, u3-agp, uni-north-agp,
uni-north-internal-pci, uni-north-pci, and versatile_pci_host.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Marcel Apfelbaum <marcel.a@redhat.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-11-28 17:26:58 +01:00
|
|
|
/*
|
|
|
|
* PCI-facing part of the host bridge, not usable without the
|
|
|
|
* host-facing part, which can't be device_add'ed, yet.
|
|
|
|
*/
|
2017-05-03 22:35:44 +02:00
|
|
|
dc->user_creatable = false;
|
2011-12-04 19:22:06 +01:00
|
|
|
}
|
|
|
|
|
2012-08-20 19:07:56 +02:00
|
|
|
static const TypeInfo ppc4xx_host_bridge_info = {
|
2011-12-08 04:34:16 +01:00
|
|
|
.name = "ppc4xx-host-bridge",
|
|
|
|
.parent = TYPE_PCI_DEVICE,
|
|
|
|
.instance_size = sizeof(PCIDevice),
|
|
|
|
.class_init = ppc4xx_host_bridge_class_init,
|
2017-09-27 21:56:34 +02:00
|
|
|
.interfaces = (InterfaceInfo[]) {
|
|
|
|
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
|
|
|
|
{ },
|
|
|
|
},
|
2012-01-10 19:36:26 +01:00
|
|
|
};
|
|
|
|
|
2012-01-24 20:12:29 +01:00
|
|
|
static void ppc4xx_pcihost_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
2011-12-08 04:34:16 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2012-01-24 20:12:29 +01:00
|
|
|
|
2018-10-01 13:44:21 +02:00
|
|
|
dc->realize = ppc4xx_pcihost_realize;
|
2011-12-08 04:34:16 +01:00
|
|
|
dc->vmsd = &vmstate_ppc4xx_pci;
|
2012-01-24 20:12:29 +01:00
|
|
|
}
|
|
|
|
|
2012-08-20 19:07:56 +02:00
|
|
|
static const TypeInfo ppc4xx_pcihost_info = {
|
2012-08-20 19:08:02 +02:00
|
|
|
.name = TYPE_PPC4xx_PCI_HOST_BRIDGE,
|
2012-08-20 19:08:08 +02:00
|
|
|
.parent = TYPE_PCI_HOST_BRIDGE,
|
2011-12-08 04:34:16 +01:00
|
|
|
.instance_size = sizeof(PPC4xxPCIState),
|
|
|
|
.class_init = ppc4xx_pcihost_class_init,
|
2012-01-10 19:36:26 +01:00
|
|
|
};
|
|
|
|
|
2012-02-09 15:20:55 +01:00
|
|
|
static void ppc4xx_pci_register_types(void)
|
2008-12-03 00:53:50 +01:00
|
|
|
{
|
2011-12-08 04:34:16 +01:00
|
|
|
type_register_static(&ppc4xx_pcihost_info);
|
|
|
|
type_register_static(&ppc4xx_host_bridge_info);
|
2008-12-03 00:53:50 +01:00
|
|
|
}
|
2012-02-09 15:20:55 +01:00
|
|
|
|
|
|
|
type_init(ppc4xx_pci_register_types)
|