2016-09-06 20:52:17 +02:00
|
|
|
/*
|
|
|
|
* ASPEED SDRAM Memory Controller
|
|
|
|
*
|
|
|
|
* Copyright (C) 2016 IBM Corp.
|
|
|
|
*
|
|
|
|
* This code is licensed under the GPL version 2 or later. See the
|
|
|
|
* COPYING file in the top-level directory.
|
|
|
|
*/
|
|
|
|
#ifndef ASPEED_SDMC_H
|
|
|
|
#define ASPEED_SDMC_H
|
|
|
|
|
|
|
|
#include "hw/sysbus.h"
|
2020-09-03 22:43:22 +02:00
|
|
|
#include "qom/object.h"
|
2016-09-06 20:52:17 +02:00
|
|
|
|
|
|
|
#define TYPE_ASPEED_SDMC "aspeed.sdmc"
|
2020-09-16 20:25:18 +02:00
|
|
|
OBJECT_DECLARE_TYPE(AspeedSDMCState, AspeedSDMCClass, ASPEED_SDMC)
|
2019-09-25 16:32:33 +02:00
|
|
|
#define TYPE_ASPEED_2400_SDMC TYPE_ASPEED_SDMC "-ast2400"
|
|
|
|
#define TYPE_ASPEED_2500_SDMC TYPE_ASPEED_SDMC "-ast2500"
|
2019-09-25 16:32:34 +02:00
|
|
|
#define TYPE_ASPEED_2600_SDMC TYPE_ASPEED_SDMC "-ast2600"
|
2016-09-06 20:52:17 +02:00
|
|
|
|
2020-09-01 14:21:51 +02:00
|
|
|
/*
|
|
|
|
* SDMC has 174 documented registers. In addition the u-boot device tree
|
|
|
|
* describes the following regions:
|
|
|
|
* - PHY status regs at offset 0x400, length 0x200
|
|
|
|
* - PHY setting regs at offset 0x100, length 0x300
|
|
|
|
*
|
|
|
|
* There are two sets of MRS (Mode Registers) configuration in ast2600 memory
|
|
|
|
* system: one is in the SDRAM MC (memory controller) which is used in run
|
|
|
|
* time, and the other is in the DDR-PHY IP which is used during DDR-PHY
|
|
|
|
* training.
|
|
|
|
*/
|
|
|
|
#define ASPEED_SDMC_NR_REGS (0x500 >> 2)
|
2016-09-06 20:52:17 +02:00
|
|
|
|
2020-09-03 22:43:22 +02:00
|
|
|
struct AspeedSDMCState {
|
2016-09-06 20:52:17 +02:00
|
|
|
/*< private >*/
|
|
|
|
SysBusDevice parent_obj;
|
|
|
|
|
|
|
|
/*< public >*/
|
|
|
|
MemoryRegion iomem;
|
|
|
|
|
|
|
|
uint32_t regs[ASPEED_SDMC_NR_REGS];
|
2016-09-22 19:13:06 +02:00
|
|
|
uint64_t ram_size;
|
2018-08-16 15:05:29 +02:00
|
|
|
uint64_t max_ram_size;
|
2020-09-03 22:43:22 +02:00
|
|
|
};
|
2016-09-06 20:52:17 +02:00
|
|
|
|
2019-09-25 16:32:33 +02:00
|
|
|
|
2020-09-03 22:43:22 +02:00
|
|
|
struct AspeedSDMCClass {
|
2019-09-25 16:32:33 +02:00
|
|
|
SysBusDeviceClass parent_class;
|
|
|
|
|
|
|
|
uint64_t max_ram_size;
|
2020-02-19 17:08:43 +01:00
|
|
|
const uint64_t *valid_ram_sizes;
|
2019-09-25 16:32:33 +02:00
|
|
|
uint32_t (*compute_conf)(AspeedSDMCState *s, uint32_t data);
|
|
|
|
void (*write)(AspeedSDMCState *s, uint32_t reg, uint32_t data);
|
2020-09-03 22:43:22 +02:00
|
|
|
};
|
2019-09-25 16:32:33 +02:00
|
|
|
|
2016-09-06 20:52:17 +02:00
|
|
|
#endif /* ASPEED_SDMC_H */
|