2007-10-29 00:42:18 +01:00
|
|
|
/*
|
|
|
|
* PowerMac descriptor-based DMA emulation
|
|
|
|
*
|
|
|
|
* Copyright (c) 2005-2007 Fabrice Bellard
|
|
|
|
* Copyright (c) 2007 Jocelyn Mayer
|
2009-01-30 21:39:32 +01:00
|
|
|
* Copyright (c) 2009 Laurent Vivier
|
|
|
|
*
|
|
|
|
* some parts from linux-2.6.28, arch/powerpc/include/asm/dbdma.h
|
|
|
|
*
|
|
|
|
* Definitions for using the Apple Descriptor-Based DMA controller
|
|
|
|
* in Power Macintosh computers.
|
|
|
|
*
|
|
|
|
* Copyright (C) 1996 Paul Mackerras.
|
|
|
|
*
|
|
|
|
* some parts from mol 0.9.71
|
|
|
|
*
|
|
|
|
* Descriptor based DMA emulation
|
|
|
|
*
|
|
|
|
* Copyright (C) 1998-2004 Samuel Rydh (samuel@ibrium.se)
|
2007-10-29 00:42:18 +01:00
|
|
|
*
|
|
|
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
|
|
|
* of this software and associated documentation files (the "Software"), to deal
|
|
|
|
* in the Software without restriction, including without limitation the rights
|
|
|
|
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
|
|
|
* copies of the Software, and to permit persons to whom the Software is
|
|
|
|
* furnished to do so, subject to the following conditions:
|
|
|
|
*
|
|
|
|
* The above copyright notice and this permission notice shall be included in
|
|
|
|
* all copies or substantial portions of the Software.
|
|
|
|
*
|
|
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
|
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
|
|
|
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
|
|
|
* THE SOFTWARE.
|
|
|
|
*/
|
2016-01-26 19:16:58 +01:00
|
|
|
#include "qemu/osdep.h"
|
2013-02-04 15:40:22 +01:00
|
|
|
#include "hw/hw.h"
|
2013-02-05 17:06:20 +01:00
|
|
|
#include "hw/isa/isa.h"
|
|
|
|
#include "hw/ppc/mac_dbdma.h"
|
2012-12-17 18:20:00 +01:00
|
|
|
#include "qemu/main-loop.h"
|
2015-12-15 13:16:16 +01:00
|
|
|
#include "qemu/log.h"
|
2016-06-06 00:36:43 +02:00
|
|
|
#include "sysemu/dma.h"
|
2007-10-29 00:42:18 +01:00
|
|
|
|
2008-12-24 10:38:16 +01:00
|
|
|
/* debug DBDMA */
|
2016-07-10 20:08:53 +02:00
|
|
|
#define DEBUG_DBDMA 0
|
2016-07-10 20:08:54 +02:00
|
|
|
#define DEBUG_DBDMA_CHANMASK ((1ull << DBDMA_CHANNELS) - 1)
|
2008-12-24 10:38:16 +01:00
|
|
|
|
2016-07-10 20:08:53 +02:00
|
|
|
#define DBDMA_DPRINTF(fmt, ...) do { \
|
|
|
|
if (DEBUG_DBDMA) { \
|
|
|
|
printf("DBDMA: " fmt , ## __VA_ARGS__); \
|
|
|
|
} \
|
maint: Fix macros with broken 'do/while(0); ' usage
The point of writing a macro embedded in a 'do { ... } while (0)'
loop (particularly if the macro has multiple statements or would
otherwise end with an 'if' statement) is so that the macro can be
used as a drop-in statement with the caller supplying the
trailing ';'. Although our coding style frowns on brace-less 'if':
if (cond)
statement;
else
something else;
that is the classic case where failure to use do/while(0) wrapping
would cause the 'else' to pair with any embedded 'if' in the macro
rather than the intended outer 'if'. But conversely, if the macro
includes an embedded ';', then the same brace-less coding style
would now have two statements, making the 'else' a syntax error
rather than pairing with the outer 'if'. Thus, even though our
coding style with required braces is not impacted, ending a macro
with ';' makes our code harder to port to projects that use
brace-less styles.
The change should have no semantic impact. I was not able to
fully compile-test all of the changes (as some of them are
examples of the ugly bit-rotting debug print statements that are
completely elided by default, and I didn't want to recompile
with the necessary -D witnesses - cleaning those up is left as a
bite-sized task for another day); I did, however, audit that for
all files touched, all callers of the changed macros DID supply
a trailing ';' at the callsite, and did not appear to be used
as part of a brace-less conditional.
Found mechanically via: $ git grep -B1 'while (0);' | grep -A1 \\\\
Signed-off-by: Eric Blake <eblake@redhat.com>
Acked-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Message-Id: <20171201232433.25193-7-eblake@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-12-02 00:24:32 +01:00
|
|
|
} while (0)
|
2008-12-24 10:38:16 +01:00
|
|
|
|
2016-07-10 20:08:54 +02:00
|
|
|
#define DBDMA_DPRINTFCH(ch, fmt, ...) do { \
|
|
|
|
if (DEBUG_DBDMA) { \
|
|
|
|
if ((1ul << (ch)->channel) & DEBUG_DBDMA_CHANMASK) { \
|
|
|
|
printf("DBDMA[%02x]: " fmt , (ch)->channel, ## __VA_ARGS__); \
|
|
|
|
} \
|
|
|
|
} \
|
maint: Fix macros with broken 'do/while(0); ' usage
The point of writing a macro embedded in a 'do { ... } while (0)'
loop (particularly if the macro has multiple statements or would
otherwise end with an 'if' statement) is so that the macro can be
used as a drop-in statement with the caller supplying the
trailing ';'. Although our coding style frowns on brace-less 'if':
if (cond)
statement;
else
something else;
that is the classic case where failure to use do/while(0) wrapping
would cause the 'else' to pair with any embedded 'if' in the macro
rather than the intended outer 'if'. But conversely, if the macro
includes an embedded ';', then the same brace-less coding style
would now have two statements, making the 'else' a syntax error
rather than pairing with the outer 'if'. Thus, even though our
coding style with required braces is not impacted, ending a macro
with ';' makes our code harder to port to projects that use
brace-less styles.
The change should have no semantic impact. I was not able to
fully compile-test all of the changes (as some of them are
examples of the ugly bit-rotting debug print statements that are
completely elided by default, and I didn't want to recompile
with the necessary -D witnesses - cleaning those up is left as a
bite-sized task for another day); I did, however, audit that for
all files touched, all callers of the changed macros DID supply
a trailing ';' at the callsite, and did not appear to be used
as part of a brace-less conditional.
Found mechanically via: $ git grep -B1 'while (0);' | grep -A1 \\\\
Signed-off-by: Eric Blake <eblake@redhat.com>
Acked-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Message-Id: <20171201232433.25193-7-eblake@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-12-02 00:24:32 +01:00
|
|
|
} while (0)
|
2016-07-10 20:08:54 +02:00
|
|
|
|
2009-01-30 21:39:32 +01:00
|
|
|
/*
|
|
|
|
*/
|
|
|
|
|
2013-06-30 02:22:41 +02:00
|
|
|
static DBDMAState *dbdma_from_ch(DBDMA_channel *ch)
|
|
|
|
{
|
|
|
|
return container_of(ch, DBDMAState, channels[ch->channel]);
|
|
|
|
}
|
|
|
|
|
2016-07-10 20:08:53 +02:00
|
|
|
#if DEBUG_DBDMA
|
2009-01-30 21:39:32 +01:00
|
|
|
static void dump_dbdma_cmd(dbdma_cmd *cmd)
|
|
|
|
{
|
|
|
|
printf("dbdma_cmd %p\n", cmd);
|
|
|
|
printf(" req_count 0x%04x\n", le16_to_cpu(cmd->req_count));
|
|
|
|
printf(" command 0x%04x\n", le16_to_cpu(cmd->command));
|
|
|
|
printf(" phy_addr 0x%08x\n", le32_to_cpu(cmd->phy_addr));
|
|
|
|
printf(" cmd_dep 0x%08x\n", le32_to_cpu(cmd->cmd_dep));
|
|
|
|
printf(" res_count 0x%04x\n", le16_to_cpu(cmd->res_count));
|
|
|
|
printf(" xfer_status 0x%04x\n", le16_to_cpu(cmd->xfer_status));
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
static void dump_dbdma_cmd(dbdma_cmd *cmd)
|
2007-10-29 00:42:18 +01:00
|
|
|
{
|
2009-01-30 21:39:32 +01:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
static void dbdma_cmdptr_load(DBDMA_channel *ch)
|
|
|
|
{
|
2016-07-10 20:08:54 +02:00
|
|
|
DBDMA_DPRINTFCH(ch, "dbdma_cmdptr_load 0x%08x\n",
|
|
|
|
ch->regs[DBDMA_CMDPTR_LO]);
|
2016-06-06 00:36:43 +02:00
|
|
|
dma_memory_read(&address_space_memory, ch->regs[DBDMA_CMDPTR_LO],
|
|
|
|
&ch->current, sizeof(dbdma_cmd));
|
2007-10-29 00:42:18 +01:00
|
|
|
}
|
|
|
|
|
2009-01-30 21:39:32 +01:00
|
|
|
static void dbdma_cmdptr_save(DBDMA_channel *ch)
|
2007-10-29 00:42:18 +01:00
|
|
|
{
|
2017-09-17 19:15:45 +02:00
|
|
|
DBDMA_DPRINTFCH(ch, "-> update 0x%08x stat=0x%08x, res=0x%04x\n",
|
|
|
|
ch->regs[DBDMA_CMDPTR_LO],
|
2016-07-10 20:08:54 +02:00
|
|
|
le16_to_cpu(ch->current.xfer_status),
|
|
|
|
le16_to_cpu(ch->current.res_count));
|
2016-06-06 00:36:43 +02:00
|
|
|
dma_memory_write(&address_space_memory, ch->regs[DBDMA_CMDPTR_LO],
|
|
|
|
&ch->current, sizeof(dbdma_cmd));
|
2007-10-29 00:42:18 +01:00
|
|
|
}
|
|
|
|
|
2009-01-30 21:39:32 +01:00
|
|
|
static void kill_channel(DBDMA_channel *ch)
|
2007-10-29 00:42:18 +01:00
|
|
|
{
|
2016-07-10 20:08:54 +02:00
|
|
|
DBDMA_DPRINTFCH(ch, "kill_channel\n");
|
2009-01-30 21:39:32 +01:00
|
|
|
|
2009-12-24 01:00:41 +01:00
|
|
|
ch->regs[DBDMA_STATUS] |= DEAD;
|
|
|
|
ch->regs[DBDMA_STATUS] &= ~ACTIVE;
|
2009-01-30 21:39:32 +01:00
|
|
|
|
|
|
|
qemu_irq_raise(ch->irq);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void conditional_interrupt(DBDMA_channel *ch)
|
|
|
|
{
|
|
|
|
dbdma_cmd *current = &ch->current;
|
|
|
|
uint16_t intr;
|
|
|
|
uint16_t sel_mask, sel_value;
|
|
|
|
uint32_t status;
|
|
|
|
int cond;
|
|
|
|
|
2016-07-10 20:08:54 +02:00
|
|
|
DBDMA_DPRINTFCH(ch, "%s\n", __func__);
|
2009-01-30 21:39:32 +01:00
|
|
|
|
2009-03-03 10:14:10 +01:00
|
|
|
intr = le16_to_cpu(current->command) & INTR_MASK;
|
2009-01-30 21:39:32 +01:00
|
|
|
|
|
|
|
switch(intr) {
|
|
|
|
case INTR_NEVER: /* don't interrupt */
|
|
|
|
return;
|
|
|
|
case INTR_ALWAYS: /* always interrupt */
|
|
|
|
qemu_irq_raise(ch->irq);
|
2016-07-10 20:08:54 +02:00
|
|
|
DBDMA_DPRINTFCH(ch, "%s: raise\n", __func__);
|
2009-01-30 21:39:32 +01:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2009-12-24 01:00:41 +01:00
|
|
|
status = ch->regs[DBDMA_STATUS] & DEVSTAT;
|
2009-01-30 21:39:32 +01:00
|
|
|
|
2009-12-24 01:00:41 +01:00
|
|
|
sel_mask = (ch->regs[DBDMA_INTR_SEL] >> 16) & 0x0f;
|
|
|
|
sel_value = ch->regs[DBDMA_INTR_SEL] & 0x0f;
|
2009-01-30 21:39:32 +01:00
|
|
|
|
|
|
|
cond = (status & sel_mask) == (sel_value & sel_mask);
|
|
|
|
|
|
|
|
switch(intr) {
|
|
|
|
case INTR_IFSET: /* intr if condition bit is 1 */
|
2013-06-30 01:23:45 +02:00
|
|
|
if (cond) {
|
2009-01-30 21:39:32 +01:00
|
|
|
qemu_irq_raise(ch->irq);
|
2016-07-10 20:08:54 +02:00
|
|
|
DBDMA_DPRINTFCH(ch, "%s: raise\n", __func__);
|
2013-06-30 01:23:45 +02:00
|
|
|
}
|
2009-01-30 21:39:32 +01:00
|
|
|
return;
|
|
|
|
case INTR_IFCLR: /* intr if condition bit is 0 */
|
2013-06-30 01:23:45 +02:00
|
|
|
if (!cond) {
|
2009-01-30 21:39:32 +01:00
|
|
|
qemu_irq_raise(ch->irq);
|
2016-07-10 20:08:54 +02:00
|
|
|
DBDMA_DPRINTFCH(ch, "%s: raise\n", __func__);
|
2013-06-30 01:23:45 +02:00
|
|
|
}
|
2009-01-30 21:39:32 +01:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int conditional_wait(DBDMA_channel *ch)
|
|
|
|
{
|
|
|
|
dbdma_cmd *current = &ch->current;
|
|
|
|
uint16_t wait;
|
|
|
|
uint16_t sel_mask, sel_value;
|
|
|
|
uint32_t status;
|
|
|
|
int cond;
|
2017-09-17 19:15:45 +02:00
|
|
|
int res = 0;
|
2009-01-30 21:39:32 +01:00
|
|
|
|
2009-03-03 10:14:10 +01:00
|
|
|
wait = le16_to_cpu(current->command) & WAIT_MASK;
|
2009-01-30 21:39:32 +01:00
|
|
|
switch(wait) {
|
|
|
|
case WAIT_NEVER: /* don't wait */
|
|
|
|
return 0;
|
|
|
|
case WAIT_ALWAYS: /* always wait */
|
2017-09-17 19:15:45 +02:00
|
|
|
DBDMA_DPRINTFCH(ch, " [WAIT_ALWAYS]\n");
|
2009-01-30 21:39:32 +01:00
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2009-12-24 01:00:41 +01:00
|
|
|
status = ch->regs[DBDMA_STATUS] & DEVSTAT;
|
2009-01-30 21:39:32 +01:00
|
|
|
|
2009-12-24 01:00:41 +01:00
|
|
|
sel_mask = (ch->regs[DBDMA_WAIT_SEL] >> 16) & 0x0f;
|
|
|
|
sel_value = ch->regs[DBDMA_WAIT_SEL] & 0x0f;
|
2009-01-30 21:39:32 +01:00
|
|
|
|
|
|
|
cond = (status & sel_mask) == (sel_value & sel_mask);
|
|
|
|
|
|
|
|
switch(wait) {
|
|
|
|
case WAIT_IFSET: /* wait if condition bit is 1 */
|
2017-09-17 19:15:45 +02:00
|
|
|
if (cond) {
|
|
|
|
res = 1;
|
|
|
|
}
|
|
|
|
DBDMA_DPRINTFCH(ch, " [WAIT_IFSET=%d]\n", res);
|
|
|
|
break;
|
2009-01-30 21:39:32 +01:00
|
|
|
case WAIT_IFCLR: /* wait if condition bit is 0 */
|
2017-09-17 19:15:45 +02:00
|
|
|
if (!cond) {
|
|
|
|
res = 1;
|
|
|
|
}
|
|
|
|
DBDMA_DPRINTFCH(ch, " [WAIT_IFCLR=%d]\n", res);
|
|
|
|
break;
|
2009-01-30 21:39:32 +01:00
|
|
|
}
|
2017-09-17 19:15:45 +02:00
|
|
|
return res;
|
2009-01-30 21:39:32 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void next(DBDMA_channel *ch)
|
|
|
|
{
|
|
|
|
uint32_t cp;
|
|
|
|
|
2009-12-24 01:00:41 +01:00
|
|
|
ch->regs[DBDMA_STATUS] &= ~BT;
|
2009-01-30 21:39:32 +01:00
|
|
|
|
2009-12-24 01:00:41 +01:00
|
|
|
cp = ch->regs[DBDMA_CMDPTR_LO];
|
|
|
|
ch->regs[DBDMA_CMDPTR_LO] = cp + sizeof(dbdma_cmd);
|
2009-01-30 21:39:32 +01:00
|
|
|
dbdma_cmdptr_load(ch);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void branch(DBDMA_channel *ch)
|
|
|
|
{
|
|
|
|
dbdma_cmd *current = &ch->current;
|
|
|
|
|
2016-07-10 20:08:55 +02:00
|
|
|
ch->regs[DBDMA_CMDPTR_LO] = le32_to_cpu(current->cmd_dep);
|
2009-12-24 01:00:41 +01:00
|
|
|
ch->regs[DBDMA_STATUS] |= BT;
|
2009-01-30 21:39:32 +01:00
|
|
|
dbdma_cmdptr_load(ch);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void conditional_branch(DBDMA_channel *ch)
|
|
|
|
{
|
|
|
|
dbdma_cmd *current = &ch->current;
|
|
|
|
uint16_t br;
|
|
|
|
uint16_t sel_mask, sel_value;
|
|
|
|
uint32_t status;
|
|
|
|
int cond;
|
|
|
|
|
|
|
|
/* check if we must branch */
|
|
|
|
|
2009-03-03 10:14:10 +01:00
|
|
|
br = le16_to_cpu(current->command) & BR_MASK;
|
2009-01-30 21:39:32 +01:00
|
|
|
|
|
|
|
switch(br) {
|
|
|
|
case BR_NEVER: /* don't branch */
|
|
|
|
next(ch);
|
|
|
|
return;
|
|
|
|
case BR_ALWAYS: /* always branch */
|
2017-09-17 19:15:45 +02:00
|
|
|
DBDMA_DPRINTFCH(ch, " [BR_ALWAYS]\n");
|
2009-01-30 21:39:32 +01:00
|
|
|
branch(ch);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2009-12-24 01:00:41 +01:00
|
|
|
status = ch->regs[DBDMA_STATUS] & DEVSTAT;
|
2009-01-30 21:39:32 +01:00
|
|
|
|
2009-12-24 01:00:41 +01:00
|
|
|
sel_mask = (ch->regs[DBDMA_BRANCH_SEL] >> 16) & 0x0f;
|
|
|
|
sel_value = ch->regs[DBDMA_BRANCH_SEL] & 0x0f;
|
2009-01-30 21:39:32 +01:00
|
|
|
|
|
|
|
cond = (status & sel_mask) == (sel_value & sel_mask);
|
|
|
|
|
|
|
|
switch(br) {
|
|
|
|
case BR_IFSET: /* branch if condition bit is 1 */
|
2017-09-17 19:15:45 +02:00
|
|
|
if (cond) {
|
|
|
|
DBDMA_DPRINTFCH(ch, " [BR_IFSET = 1]\n");
|
2009-01-30 21:39:32 +01:00
|
|
|
branch(ch);
|
2017-09-17 19:15:45 +02:00
|
|
|
} else {
|
|
|
|
DBDMA_DPRINTFCH(ch, " [BR_IFSET = 0]\n");
|
2009-01-30 21:39:32 +01:00
|
|
|
next(ch);
|
2017-09-17 19:15:45 +02:00
|
|
|
}
|
2009-01-30 21:39:32 +01:00
|
|
|
return;
|
|
|
|
case BR_IFCLR: /* branch if condition bit is 0 */
|
2017-09-17 19:15:45 +02:00
|
|
|
if (!cond) {
|
|
|
|
DBDMA_DPRINTFCH(ch, " [BR_IFCLR = 1]\n");
|
2009-01-30 21:39:32 +01:00
|
|
|
branch(ch);
|
2017-09-17 19:15:45 +02:00
|
|
|
} else {
|
|
|
|
DBDMA_DPRINTFCH(ch, " [BR_IFCLR = 0]\n");
|
2009-01-30 21:39:32 +01:00
|
|
|
next(ch);
|
2017-09-17 19:15:45 +02:00
|
|
|
}
|
2009-01-30 21:39:32 +01:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-03-03 10:14:10 +01:00
|
|
|
static void channel_run(DBDMA_channel *ch);
|
2009-01-30 21:39:32 +01:00
|
|
|
|
2009-03-03 10:14:10 +01:00
|
|
|
static void dbdma_end(DBDMA_io *io)
|
2009-01-30 21:39:32 +01:00
|
|
|
{
|
|
|
|
DBDMA_channel *ch = io->channel;
|
|
|
|
dbdma_cmd *current = &ch->current;
|
|
|
|
|
2016-07-10 20:08:54 +02:00
|
|
|
DBDMA_DPRINTFCH(ch, "%s\n", __func__);
|
2013-06-30 01:23:45 +02:00
|
|
|
|
2009-03-03 10:14:10 +01:00
|
|
|
if (conditional_wait(ch))
|
|
|
|
goto wait;
|
2009-01-30 21:39:32 +01:00
|
|
|
|
2009-12-24 01:00:41 +01:00
|
|
|
current->xfer_status = cpu_to_le16(ch->regs[DBDMA_STATUS]);
|
|
|
|
current->res_count = cpu_to_le16(io->len);
|
2009-03-03 10:14:10 +01:00
|
|
|
dbdma_cmdptr_save(ch);
|
2009-03-04 08:20:40 +01:00
|
|
|
if (io->is_last)
|
2009-12-24 01:00:41 +01:00
|
|
|
ch->regs[DBDMA_STATUS] &= ~FLUSH;
|
2009-03-03 10:14:10 +01:00
|
|
|
|
|
|
|
conditional_interrupt(ch);
|
|
|
|
conditional_branch(ch);
|
2009-01-30 21:39:32 +01:00
|
|
|
|
2009-03-03 10:14:10 +01:00
|
|
|
wait:
|
2013-06-30 02:47:20 +02:00
|
|
|
/* Indicate that we're ready for a new DMA round */
|
|
|
|
ch->io.processing = false;
|
|
|
|
|
2009-12-24 01:00:41 +01:00
|
|
|
if ((ch->regs[DBDMA_STATUS] & RUN) &&
|
|
|
|
(ch->regs[DBDMA_STATUS] & ACTIVE))
|
2009-03-03 10:14:10 +01:00
|
|
|
channel_run(ch);
|
2009-01-30 21:39:32 +01:00
|
|
|
}
|
|
|
|
|
2009-03-03 10:14:10 +01:00
|
|
|
static void start_output(DBDMA_channel *ch, int key, uint32_t addr,
|
2009-01-30 21:39:32 +01:00
|
|
|
uint16_t req_count, int is_last)
|
|
|
|
{
|
2016-07-10 20:08:54 +02:00
|
|
|
DBDMA_DPRINTFCH(ch, "start_output\n");
|
2009-01-30 21:39:32 +01:00
|
|
|
|
|
|
|
/* KEY_REGS, KEY_DEVICE and KEY_STREAM
|
|
|
|
* are not implemented in the mac-io chip
|
|
|
|
*/
|
|
|
|
|
2016-07-10 20:08:54 +02:00
|
|
|
DBDMA_DPRINTFCH(ch, "addr 0x%x key 0x%x\n", addr, key);
|
2009-01-30 21:39:32 +01:00
|
|
|
if (!addr || key > KEY_STREAM3) {
|
|
|
|
kill_channel(ch);
|
2009-03-03 10:14:10 +01:00
|
|
|
return;
|
2009-01-30 21:39:32 +01:00
|
|
|
}
|
|
|
|
|
2009-03-03 10:14:10 +01:00
|
|
|
ch->io.addr = addr;
|
2009-01-30 21:39:32 +01:00
|
|
|
ch->io.len = req_count;
|
|
|
|
ch->io.is_last = is_last;
|
2009-03-03 10:14:10 +01:00
|
|
|
ch->io.dma_end = dbdma_end;
|
|
|
|
ch->io.is_dma_out = 1;
|
2013-06-30 02:47:20 +02:00
|
|
|
ch->io.processing = true;
|
2010-02-09 17:37:07 +01:00
|
|
|
if (ch->rw) {
|
|
|
|
ch->rw(&ch->io);
|
|
|
|
}
|
2009-01-30 21:39:32 +01:00
|
|
|
}
|
|
|
|
|
2009-03-03 10:14:10 +01:00
|
|
|
static void start_input(DBDMA_channel *ch, int key, uint32_t addr,
|
2009-01-30 21:39:32 +01:00
|
|
|
uint16_t req_count, int is_last)
|
|
|
|
{
|
2016-07-10 20:08:54 +02:00
|
|
|
DBDMA_DPRINTFCH(ch, "start_input\n");
|
2009-01-30 21:39:32 +01:00
|
|
|
|
|
|
|
/* KEY_REGS, KEY_DEVICE and KEY_STREAM
|
|
|
|
* are not implemented in the mac-io chip
|
|
|
|
*/
|
|
|
|
|
2016-07-10 20:08:54 +02:00
|
|
|
DBDMA_DPRINTFCH(ch, "addr 0x%x key 0x%x\n", addr, key);
|
2009-01-30 21:39:32 +01:00
|
|
|
if (!addr || key > KEY_STREAM3) {
|
|
|
|
kill_channel(ch);
|
2009-03-03 10:14:10 +01:00
|
|
|
return;
|
2009-01-30 21:39:32 +01:00
|
|
|
}
|
|
|
|
|
2009-03-03 10:14:10 +01:00
|
|
|
ch->io.addr = addr;
|
2009-01-30 21:39:32 +01:00
|
|
|
ch->io.len = req_count;
|
|
|
|
ch->io.is_last = is_last;
|
2009-03-03 10:14:10 +01:00
|
|
|
ch->io.dma_end = dbdma_end;
|
|
|
|
ch->io.is_dma_out = 0;
|
2013-06-30 02:47:20 +02:00
|
|
|
ch->io.processing = true;
|
2010-02-09 17:37:07 +01:00
|
|
|
if (ch->rw) {
|
|
|
|
ch->rw(&ch->io);
|
|
|
|
}
|
2009-01-30 21:39:32 +01:00
|
|
|
}
|
|
|
|
|
2009-03-03 10:14:10 +01:00
|
|
|
static void load_word(DBDMA_channel *ch, int key, uint32_t addr,
|
2009-01-30 21:39:32 +01:00
|
|
|
uint16_t len)
|
|
|
|
{
|
|
|
|
dbdma_cmd *current = &ch->current;
|
|
|
|
|
2016-07-10 20:08:56 +02:00
|
|
|
DBDMA_DPRINTFCH(ch, "load_word %d bytes, addr=%08x\n", len, addr);
|
2009-01-30 21:39:32 +01:00
|
|
|
|
|
|
|
/* only implements KEY_SYSTEM */
|
|
|
|
|
|
|
|
if (key != KEY_SYSTEM) {
|
|
|
|
printf("DBDMA: LOAD_WORD, unimplemented key %x\n", key);
|
|
|
|
kill_channel(ch);
|
2009-03-03 10:14:10 +01:00
|
|
|
return;
|
2009-01-30 21:39:32 +01:00
|
|
|
}
|
|
|
|
|
2016-07-10 20:08:56 +02:00
|
|
|
dma_memory_read(&address_space_memory, addr, ¤t->cmd_dep, len);
|
2009-01-30 21:39:32 +01:00
|
|
|
|
|
|
|
if (conditional_wait(ch))
|
2009-03-03 10:14:10 +01:00
|
|
|
goto wait;
|
2009-01-30 21:39:32 +01:00
|
|
|
|
2009-12-24 01:00:41 +01:00
|
|
|
current->xfer_status = cpu_to_le16(ch->regs[DBDMA_STATUS]);
|
2009-01-30 21:39:32 +01:00
|
|
|
dbdma_cmdptr_save(ch);
|
2009-12-24 01:00:41 +01:00
|
|
|
ch->regs[DBDMA_STATUS] &= ~FLUSH;
|
2009-01-30 21:39:32 +01:00
|
|
|
|
|
|
|
conditional_interrupt(ch);
|
|
|
|
next(ch);
|
|
|
|
|
2009-03-03 10:14:10 +01:00
|
|
|
wait:
|
2013-06-30 02:22:41 +02:00
|
|
|
DBDMA_kick(dbdma_from_ch(ch));
|
2009-01-30 21:39:32 +01:00
|
|
|
}
|
|
|
|
|
2009-03-03 10:14:10 +01:00
|
|
|
static void store_word(DBDMA_channel *ch, int key, uint32_t addr,
|
2009-01-30 21:39:32 +01:00
|
|
|
uint16_t len)
|
|
|
|
{
|
|
|
|
dbdma_cmd *current = &ch->current;
|
|
|
|
|
2016-07-10 20:08:56 +02:00
|
|
|
DBDMA_DPRINTFCH(ch, "store_word %d bytes, addr=%08x pa=%x\n",
|
|
|
|
len, addr, le32_to_cpu(current->cmd_dep));
|
2009-01-30 21:39:32 +01:00
|
|
|
|
|
|
|
/* only implements KEY_SYSTEM */
|
|
|
|
|
|
|
|
if (key != KEY_SYSTEM) {
|
|
|
|
printf("DBDMA: STORE_WORD, unimplemented key %x\n", key);
|
|
|
|
kill_channel(ch);
|
2009-03-03 10:14:10 +01:00
|
|
|
return;
|
2009-01-30 21:39:32 +01:00
|
|
|
}
|
|
|
|
|
2016-07-10 20:08:56 +02:00
|
|
|
dma_memory_write(&address_space_memory, addr, ¤t->cmd_dep, len);
|
2009-01-30 21:39:32 +01:00
|
|
|
|
|
|
|
if (conditional_wait(ch))
|
2009-03-03 10:14:10 +01:00
|
|
|
goto wait;
|
2009-01-30 21:39:32 +01:00
|
|
|
|
2009-12-24 01:00:41 +01:00
|
|
|
current->xfer_status = cpu_to_le16(ch->regs[DBDMA_STATUS]);
|
2009-01-30 21:39:32 +01:00
|
|
|
dbdma_cmdptr_save(ch);
|
2009-12-24 01:00:41 +01:00
|
|
|
ch->regs[DBDMA_STATUS] &= ~FLUSH;
|
2009-01-30 21:39:32 +01:00
|
|
|
|
|
|
|
conditional_interrupt(ch);
|
|
|
|
next(ch);
|
|
|
|
|
2009-03-03 10:14:10 +01:00
|
|
|
wait:
|
2013-06-30 02:22:41 +02:00
|
|
|
DBDMA_kick(dbdma_from_ch(ch));
|
2009-01-30 21:39:32 +01:00
|
|
|
}
|
|
|
|
|
2009-03-03 10:14:10 +01:00
|
|
|
static void nop(DBDMA_channel *ch)
|
2009-01-30 21:39:32 +01:00
|
|
|
{
|
|
|
|
dbdma_cmd *current = &ch->current;
|
|
|
|
|
|
|
|
if (conditional_wait(ch))
|
2009-03-03 10:14:10 +01:00
|
|
|
goto wait;
|
2009-01-30 21:39:32 +01:00
|
|
|
|
2009-12-24 01:00:41 +01:00
|
|
|
current->xfer_status = cpu_to_le16(ch->regs[DBDMA_STATUS]);
|
2009-01-30 21:39:32 +01:00
|
|
|
dbdma_cmdptr_save(ch);
|
|
|
|
|
|
|
|
conditional_interrupt(ch);
|
|
|
|
conditional_branch(ch);
|
|
|
|
|
2009-03-03 10:14:10 +01:00
|
|
|
wait:
|
2013-06-30 02:22:41 +02:00
|
|
|
DBDMA_kick(dbdma_from_ch(ch));
|
2007-10-29 00:42:18 +01:00
|
|
|
}
|
|
|
|
|
2009-03-03 10:14:10 +01:00
|
|
|
static void stop(DBDMA_channel *ch)
|
2007-10-29 00:42:18 +01:00
|
|
|
{
|
2017-09-17 19:15:45 +02:00
|
|
|
ch->regs[DBDMA_STATUS] &= ~(ACTIVE);
|
2009-01-30 21:39:32 +01:00
|
|
|
|
|
|
|
/* the stop command does not increment command pointer */
|
2007-10-29 00:42:18 +01:00
|
|
|
}
|
|
|
|
|
2009-03-03 10:14:10 +01:00
|
|
|
static void channel_run(DBDMA_channel *ch)
|
2007-10-29 00:42:18 +01:00
|
|
|
{
|
2009-01-30 21:39:32 +01:00
|
|
|
dbdma_cmd *current = &ch->current;
|
|
|
|
uint16_t cmd, key;
|
|
|
|
uint16_t req_count;
|
|
|
|
uint32_t phy_addr;
|
|
|
|
|
2016-07-10 20:08:54 +02:00
|
|
|
DBDMA_DPRINTFCH(ch, "channel_run\n");
|
2009-01-30 21:39:32 +01:00
|
|
|
dump_dbdma_cmd(current);
|
|
|
|
|
|
|
|
/* clear WAKE flag at command fetch */
|
|
|
|
|
2009-12-24 01:00:41 +01:00
|
|
|
ch->regs[DBDMA_STATUS] &= ~WAKE;
|
2009-01-30 21:39:32 +01:00
|
|
|
|
|
|
|
cmd = le16_to_cpu(current->command) & COMMAND_MASK;
|
|
|
|
|
|
|
|
switch (cmd) {
|
|
|
|
case DBDMA_NOP:
|
2009-03-03 10:14:10 +01:00
|
|
|
nop(ch);
|
2013-06-30 01:45:22 +02:00
|
|
|
return;
|
2009-01-30 21:39:32 +01:00
|
|
|
|
|
|
|
case DBDMA_STOP:
|
2009-03-03 10:14:10 +01:00
|
|
|
stop(ch);
|
2013-06-30 01:45:22 +02:00
|
|
|
return;
|
2009-01-30 21:39:32 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
key = le16_to_cpu(current->command) & 0x0700;
|
|
|
|
req_count = le16_to_cpu(current->req_count);
|
|
|
|
phy_addr = le32_to_cpu(current->phy_addr);
|
|
|
|
|
|
|
|
if (key == KEY_STREAM4) {
|
|
|
|
printf("command %x, invalid key 4\n", cmd);
|
|
|
|
kill_channel(ch);
|
2009-03-03 10:14:10 +01:00
|
|
|
return;
|
2009-01-30 21:39:32 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
switch (cmd) {
|
|
|
|
case OUTPUT_MORE:
|
2017-09-17 19:15:45 +02:00
|
|
|
DBDMA_DPRINTFCH(ch, "* OUTPUT_MORE *\n");
|
2009-03-03 10:14:10 +01:00
|
|
|
start_output(ch, key, phy_addr, req_count, 0);
|
2013-06-30 01:45:22 +02:00
|
|
|
return;
|
2009-01-30 21:39:32 +01:00
|
|
|
|
|
|
|
case OUTPUT_LAST:
|
2017-09-17 19:15:45 +02:00
|
|
|
DBDMA_DPRINTFCH(ch, "* OUTPUT_LAST *\n");
|
2009-03-03 10:14:10 +01:00
|
|
|
start_output(ch, key, phy_addr, req_count, 1);
|
2013-06-30 01:45:22 +02:00
|
|
|
return;
|
2009-01-30 21:39:32 +01:00
|
|
|
|
|
|
|
case INPUT_MORE:
|
2017-09-17 19:15:45 +02:00
|
|
|
DBDMA_DPRINTFCH(ch, "* INPUT_MORE *\n");
|
2009-03-03 10:14:10 +01:00
|
|
|
start_input(ch, key, phy_addr, req_count, 0);
|
2013-06-30 01:45:22 +02:00
|
|
|
return;
|
2009-01-30 21:39:32 +01:00
|
|
|
|
|
|
|
case INPUT_LAST:
|
2017-09-17 19:15:45 +02:00
|
|
|
DBDMA_DPRINTFCH(ch, "* INPUT_LAST *\n");
|
2009-03-03 10:14:10 +01:00
|
|
|
start_input(ch, key, phy_addr, req_count, 1);
|
2013-06-30 01:45:22 +02:00
|
|
|
return;
|
2009-01-30 21:39:32 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
if (key < KEY_REGS) {
|
|
|
|
printf("command %x, invalid key %x\n", cmd, key);
|
|
|
|
key = KEY_SYSTEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* for LOAD_WORD and STORE_WORD, req_count is on 3 bits
|
|
|
|
* and BRANCH is invalid
|
|
|
|
*/
|
|
|
|
|
|
|
|
req_count = req_count & 0x0007;
|
|
|
|
if (req_count & 0x4) {
|
|
|
|
req_count = 4;
|
|
|
|
phy_addr &= ~3;
|
|
|
|
} else if (req_count & 0x2) {
|
|
|
|
req_count = 2;
|
|
|
|
phy_addr &= ~1;
|
|
|
|
} else
|
|
|
|
req_count = 1;
|
|
|
|
|
|
|
|
switch (cmd) {
|
|
|
|
case LOAD_WORD:
|
2017-09-17 19:15:45 +02:00
|
|
|
DBDMA_DPRINTFCH(ch, "* LOAD_WORD *\n");
|
2009-03-03 10:14:10 +01:00
|
|
|
load_word(ch, key, phy_addr, req_count);
|
2013-06-30 01:45:22 +02:00
|
|
|
return;
|
2009-01-30 21:39:32 +01:00
|
|
|
|
|
|
|
case STORE_WORD:
|
2017-09-17 19:15:45 +02:00
|
|
|
DBDMA_DPRINTFCH(ch, "* STORE_WORD *\n");
|
2009-03-03 10:14:10 +01:00
|
|
|
store_word(ch, key, phy_addr, req_count);
|
2013-06-30 01:45:22 +02:00
|
|
|
return;
|
2009-01-30 21:39:32 +01:00
|
|
|
}
|
2007-10-29 00:42:18 +01:00
|
|
|
}
|
|
|
|
|
2010-12-03 00:04:02 +01:00
|
|
|
static void DBDMA_run(DBDMAState *s)
|
2009-01-30 21:39:32 +01:00
|
|
|
{
|
|
|
|
int channel;
|
|
|
|
|
2010-12-03 00:04:02 +01:00
|
|
|
for (channel = 0; channel < DBDMA_CHANNELS; channel++) {
|
|
|
|
DBDMA_channel *ch = &s->channels[channel];
|
|
|
|
uint32_t status = ch->regs[DBDMA_STATUS];
|
2013-06-30 02:47:20 +02:00
|
|
|
if (!ch->io.processing && (status & RUN) && (status & ACTIVE)) {
|
2010-12-03 00:04:02 +01:00
|
|
|
channel_run(ch);
|
|
|
|
}
|
2009-01-30 21:39:32 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void DBDMA_run_bh(void *opaque)
|
|
|
|
{
|
2010-12-03 00:04:02 +01:00
|
|
|
DBDMAState *s = opaque;
|
2009-01-30 21:39:32 +01:00
|
|
|
|
2016-07-10 20:08:54 +02:00
|
|
|
DBDMA_DPRINTF("-> DBDMA_run_bh\n");
|
2010-12-03 00:04:02 +01:00
|
|
|
DBDMA_run(s);
|
2016-07-10 20:08:54 +02:00
|
|
|
DBDMA_DPRINTF("<- DBDMA_run_bh\n");
|
2009-01-30 21:39:32 +01:00
|
|
|
}
|
|
|
|
|
2013-06-30 02:18:54 +02:00
|
|
|
void DBDMA_kick(DBDMAState *dbdma)
|
|
|
|
{
|
2013-06-30 02:22:41 +02:00
|
|
|
qemu_bh_schedule(dbdma->bh);
|
2013-06-30 02:18:54 +02:00
|
|
|
}
|
|
|
|
|
2009-01-30 21:39:32 +01:00
|
|
|
void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq,
|
2009-03-04 08:20:40 +01:00
|
|
|
DBDMA_rw rw, DBDMA_flush flush,
|
2009-01-30 21:39:32 +01:00
|
|
|
void *opaque)
|
|
|
|
{
|
2010-12-03 00:04:02 +01:00
|
|
|
DBDMAState *s = dbdma;
|
|
|
|
DBDMA_channel *ch = &s->channels[nchan];
|
2009-01-30 21:39:32 +01:00
|
|
|
|
2016-07-10 20:08:54 +02:00
|
|
|
DBDMA_DPRINTFCH(ch, "DBDMA_register_channel 0x%x\n", nchan);
|
2009-01-30 21:39:32 +01:00
|
|
|
|
2016-02-25 13:02:11 +01:00
|
|
|
assert(rw);
|
|
|
|
assert(flush);
|
|
|
|
|
2009-01-30 21:39:32 +01:00
|
|
|
ch->irq = irq;
|
2009-03-03 10:14:10 +01:00
|
|
|
ch->rw = rw;
|
2009-03-04 08:20:40 +01:00
|
|
|
ch->flush = flush;
|
2009-01-30 21:39:32 +01:00
|
|
|
ch->io.opaque = opaque;
|
|
|
|
}
|
|
|
|
|
2017-09-17 19:15:45 +02:00
|
|
|
static void dbdma_control_write(DBDMA_channel *ch)
|
2009-01-30 21:39:32 +01:00
|
|
|
{
|
|
|
|
uint16_t mask, value;
|
|
|
|
uint32_t status;
|
2017-09-17 19:15:45 +02:00
|
|
|
bool do_flush = false;
|
2009-01-30 21:39:32 +01:00
|
|
|
|
2009-12-24 01:00:41 +01:00
|
|
|
mask = (ch->regs[DBDMA_CONTROL] >> 16) & 0xffff;
|
|
|
|
value = ch->regs[DBDMA_CONTROL] & 0xffff;
|
2009-01-30 21:39:32 +01:00
|
|
|
|
2017-09-17 19:15:45 +02:00
|
|
|
/* This is the status register which we'll update
|
|
|
|
* appropriately and store back
|
|
|
|
*/
|
2009-12-24 01:00:41 +01:00
|
|
|
status = ch->regs[DBDMA_STATUS];
|
2009-01-30 21:39:32 +01:00
|
|
|
|
2017-09-17 19:15:45 +02:00
|
|
|
/* RUN and PAUSE are bits under SW control only
|
|
|
|
* FLUSH and WAKE are set by SW and cleared by HW
|
|
|
|
* DEAD, ACTIVE and BT are only under HW control
|
|
|
|
*
|
|
|
|
* We handle ACTIVE separately at the end of the
|
|
|
|
* logic to ensure all cases are covered.
|
|
|
|
*/
|
2009-01-30 21:39:32 +01:00
|
|
|
|
2017-09-17 19:15:45 +02:00
|
|
|
/* Setting RUN will tentatively activate the channel
|
|
|
|
*/
|
|
|
|
if ((mask & RUN) && (value & RUN)) {
|
|
|
|
status |= RUN;
|
|
|
|
DBDMA_DPRINTFCH(ch, " Setting RUN !\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Clearing RUN 1->0 will stop the channel */
|
|
|
|
if ((mask & RUN) && !(value & RUN)) {
|
|
|
|
/* This has the side effect of clearing the DEAD bit */
|
|
|
|
status &= ~(DEAD | RUN);
|
|
|
|
DBDMA_DPRINTFCH(ch, " Clearing RUN !\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Setting WAKE wakes up an idle channel if it's running
|
|
|
|
*
|
|
|
|
* Note: The doc doesn't say so but assume that only works
|
|
|
|
* on a channel whose RUN bit is set.
|
|
|
|
*
|
|
|
|
* We set WAKE in status, it's not terribly useful as it will
|
|
|
|
* be cleared on the next command fetch but it seems to mimmic
|
|
|
|
* the HW behaviour and is useful for the way we handle
|
|
|
|
* ACTIVE further down.
|
|
|
|
*/
|
|
|
|
if ((mask & WAKE) && (value & WAKE) && (status & RUN)) {
|
|
|
|
status |= WAKE;
|
|
|
|
DBDMA_DPRINTFCH(ch, " Setting WAKE !\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
/* PAUSE being set will deactivate (or prevent activation)
|
|
|
|
* of the channel. We just copy it over for now, ACTIVE will
|
|
|
|
* be re-evaluated later.
|
|
|
|
*/
|
|
|
|
if (mask & PAUSE) {
|
|
|
|
status = (status & ~PAUSE) | (value & PAUSE);
|
|
|
|
DBDMA_DPRINTFCH(ch, " %sing PAUSE !\n",
|
|
|
|
(value & PAUSE) ? "sett" : "clear");
|
|
|
|
}
|
|
|
|
|
|
|
|
/* FLUSH is its own thing */
|
|
|
|
if ((mask & FLUSH) && (value & FLUSH)) {
|
|
|
|
DBDMA_DPRINTFCH(ch, " Setting FLUSH !\n");
|
|
|
|
/* We set flush directly in the status register, we do *NOT*
|
|
|
|
* set it in "status" so that it gets naturally cleared when
|
|
|
|
* we update the status register further down. That way it
|
|
|
|
* will be set only during the HW flush operation so it is
|
|
|
|
* visible to any completions happening during that time.
|
|
|
|
*/
|
|
|
|
ch->regs[DBDMA_STATUS] |= FLUSH;
|
|
|
|
do_flush = true;
|
2009-01-30 21:39:32 +01:00
|
|
|
}
|
2017-09-17 19:15:45 +02:00
|
|
|
|
|
|
|
/* If either RUN or PAUSE is clear, so should ACTIVE be,
|
|
|
|
* otherwise, ACTIVE will be set if we modified RUN, PAUSE or
|
|
|
|
* set WAKE. That means that PAUSE was just cleared, RUN was
|
|
|
|
* just set or WAKE was just set.
|
|
|
|
*/
|
|
|
|
if ((status & PAUSE) || !(status & RUN)) {
|
2009-01-30 21:39:32 +01:00
|
|
|
status &= ~ACTIVE;
|
2017-09-17 19:15:45 +02:00
|
|
|
DBDMA_DPRINTFCH(ch, " -> ACTIVE down !\n");
|
|
|
|
|
|
|
|
/* We stopped processing, we want the underlying HW command
|
|
|
|
* to complete *before* we clear the ACTIVE bit. Otherwise
|
|
|
|
* we can get into a situation where the command status will
|
|
|
|
* have RUN or ACTIVE not set which is going to confuse the
|
|
|
|
* MacOS driver.
|
|
|
|
*/
|
|
|
|
do_flush = true;
|
|
|
|
} else if (mask & (RUN | PAUSE)) {
|
|
|
|
status |= ACTIVE;
|
|
|
|
DBDMA_DPRINTFCH(ch, " -> ACTIVE up !\n");
|
|
|
|
} else if ((mask & WAKE) && (value & WAKE)) {
|
|
|
|
status |= ACTIVE;
|
|
|
|
DBDMA_DPRINTFCH(ch, " -> ACTIVE up !\n");
|
2015-08-23 12:50:55 +02:00
|
|
|
}
|
|
|
|
|
2017-09-17 19:15:45 +02:00
|
|
|
DBDMA_DPRINTFCH(ch, " new status=0x%08x\n", status);
|
|
|
|
|
|
|
|
/* If we need to flush the underlying HW, do it now, this happens
|
|
|
|
* both on FLUSH commands and when stopping the channel for safety.
|
|
|
|
*/
|
|
|
|
if (do_flush && ch->flush) {
|
2015-08-23 12:50:55 +02:00
|
|
|
ch->flush(&ch->io);
|
2009-01-30 21:39:32 +01:00
|
|
|
}
|
|
|
|
|
2017-09-17 19:15:45 +02:00
|
|
|
/* Finally update the status register image */
|
2009-12-24 01:00:41 +01:00
|
|
|
ch->regs[DBDMA_STATUS] = status;
|
2009-01-30 21:39:32 +01:00
|
|
|
|
2017-09-17 19:15:45 +02:00
|
|
|
/* If active, make sure the BH gets to run */
|
2013-06-30 02:22:41 +02:00
|
|
|
if (status & ACTIVE) {
|
|
|
|
DBDMA_kick(dbdma_from_ch(ch));
|
|
|
|
}
|
2009-01-30 21:39:32 +01:00
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static void dbdma_write(void *opaque, hwaddr addr,
|
2011-08-08 15:09:17 +02:00
|
|
|
uint64_t value, unsigned size)
|
2009-01-30 21:39:32 +01:00
|
|
|
{
|
|
|
|
int channel = addr >> DBDMA_CHANNEL_SHIFT;
|
2010-12-03 00:04:02 +01:00
|
|
|
DBDMAState *s = opaque;
|
|
|
|
DBDMA_channel *ch = &s->channels[channel];
|
2009-01-30 21:39:32 +01:00
|
|
|
int reg = (addr - (channel << DBDMA_CHANNEL_SHIFT)) >> 2;
|
|
|
|
|
2016-07-10 20:08:54 +02:00
|
|
|
DBDMA_DPRINTFCH(ch, "writel 0x" TARGET_FMT_plx " <= 0x%08"PRIx64"\n",
|
|
|
|
addr, value);
|
|
|
|
DBDMA_DPRINTFCH(ch, "channel 0x%x reg 0x%x\n",
|
|
|
|
(uint32_t)addr >> DBDMA_CHANNEL_SHIFT, reg);
|
2009-01-30 21:39:32 +01:00
|
|
|
|
2013-06-30 01:53:51 +02:00
|
|
|
/* cmdptr cannot be modified if channel is ACTIVE */
|
2009-01-30 21:39:32 +01:00
|
|
|
|
2013-06-30 01:53:51 +02:00
|
|
|
if (reg == DBDMA_CMDPTR_LO && (ch->regs[DBDMA_STATUS] & ACTIVE)) {
|
2013-06-30 01:45:22 +02:00
|
|
|
return;
|
2013-06-30 01:53:51 +02:00
|
|
|
}
|
2009-01-30 21:39:32 +01:00
|
|
|
|
|
|
|
ch->regs[reg] = value;
|
|
|
|
|
|
|
|
switch(reg) {
|
|
|
|
case DBDMA_CONTROL:
|
|
|
|
dbdma_control_write(ch);
|
|
|
|
break;
|
|
|
|
case DBDMA_CMDPTR_LO:
|
|
|
|
/* 16-byte aligned */
|
2009-12-24 01:00:41 +01:00
|
|
|
ch->regs[DBDMA_CMDPTR_LO] &= ~0xf;
|
2009-01-30 21:39:32 +01:00
|
|
|
dbdma_cmdptr_load(ch);
|
|
|
|
break;
|
|
|
|
case DBDMA_STATUS:
|
|
|
|
case DBDMA_INTR_SEL:
|
|
|
|
case DBDMA_BRANCH_SEL:
|
|
|
|
case DBDMA_WAIT_SEL:
|
|
|
|
/* nothing to do */
|
|
|
|
break;
|
|
|
|
case DBDMA_XFER_MODE:
|
|
|
|
case DBDMA_CMDPTR_HI:
|
|
|
|
case DBDMA_DATA2PTR_HI:
|
|
|
|
case DBDMA_DATA2PTR_LO:
|
|
|
|
case DBDMA_ADDRESS_HI:
|
|
|
|
case DBDMA_BRANCH_ADDR_HI:
|
|
|
|
case DBDMA_RES1:
|
|
|
|
case DBDMA_RES2:
|
|
|
|
case DBDMA_RES3:
|
|
|
|
case DBDMA_RES4:
|
|
|
|
/* unused */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static uint64_t dbdma_read(void *opaque, hwaddr addr,
|
2011-08-08 15:09:17 +02:00
|
|
|
unsigned size)
|
2007-10-29 00:42:18 +01:00
|
|
|
{
|
2009-01-30 21:39:32 +01:00
|
|
|
uint32_t value;
|
|
|
|
int channel = addr >> DBDMA_CHANNEL_SHIFT;
|
2010-12-03 00:04:02 +01:00
|
|
|
DBDMAState *s = opaque;
|
|
|
|
DBDMA_channel *ch = &s->channels[channel];
|
2009-01-30 21:39:32 +01:00
|
|
|
int reg = (addr - (channel << DBDMA_CHANNEL_SHIFT)) >> 2;
|
2008-12-24 10:38:16 +01:00
|
|
|
|
2009-01-30 21:39:32 +01:00
|
|
|
value = ch->regs[reg];
|
|
|
|
|
|
|
|
switch(reg) {
|
|
|
|
case DBDMA_CONTROL:
|
2017-09-17 19:15:45 +02:00
|
|
|
value = ch->regs[DBDMA_STATUS];
|
2009-01-30 21:39:32 +01:00
|
|
|
break;
|
|
|
|
case DBDMA_STATUS:
|
|
|
|
case DBDMA_CMDPTR_LO:
|
|
|
|
case DBDMA_INTR_SEL:
|
|
|
|
case DBDMA_BRANCH_SEL:
|
|
|
|
case DBDMA_WAIT_SEL:
|
|
|
|
/* nothing to do */
|
|
|
|
break;
|
|
|
|
case DBDMA_XFER_MODE:
|
|
|
|
case DBDMA_CMDPTR_HI:
|
|
|
|
case DBDMA_DATA2PTR_HI:
|
|
|
|
case DBDMA_DATA2PTR_LO:
|
|
|
|
case DBDMA_ADDRESS_HI:
|
|
|
|
case DBDMA_BRANCH_ADDR_HI:
|
|
|
|
/* unused */
|
|
|
|
value = 0;
|
|
|
|
break;
|
|
|
|
case DBDMA_RES1:
|
|
|
|
case DBDMA_RES2:
|
|
|
|
case DBDMA_RES3:
|
|
|
|
case DBDMA_RES4:
|
|
|
|
/* reserved */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2017-09-17 19:15:45 +02:00
|
|
|
DBDMA_DPRINTFCH(ch, "readl 0x" TARGET_FMT_plx " => 0x%08x\n", addr, value);
|
|
|
|
DBDMA_DPRINTFCH(ch, "channel 0x%x reg 0x%x\n",
|
|
|
|
(uint32_t)addr >> DBDMA_CHANNEL_SHIFT, reg);
|
|
|
|
|
2009-01-30 21:39:32 +01:00
|
|
|
return value;
|
2007-10-29 00:42:18 +01:00
|
|
|
}
|
|
|
|
|
2011-08-08 15:09:17 +02:00
|
|
|
static const MemoryRegionOps dbdma_ops = {
|
|
|
|
.read = dbdma_read,
|
|
|
|
.write = dbdma_write,
|
|
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
|
|
.valid = {
|
|
|
|
.min_access_size = 4,
|
|
|
|
.max_access_size = 4,
|
|
|
|
},
|
2007-10-29 00:42:18 +01:00
|
|
|
};
|
|
|
|
|
2016-01-06 21:37:25 +01:00
|
|
|
static const VMStateDescription vmstate_dbdma_io = {
|
|
|
|
.name = "dbdma_io",
|
|
|
|
.version_id = 0,
|
|
|
|
.minimum_version_id = 0,
|
|
|
|
.fields = (VMStateField[]) {
|
|
|
|
VMSTATE_UINT64(addr, struct DBDMA_io),
|
|
|
|
VMSTATE_INT32(len, struct DBDMA_io),
|
|
|
|
VMSTATE_INT32(is_last, struct DBDMA_io),
|
|
|
|
VMSTATE_INT32(is_dma_out, struct DBDMA_io),
|
|
|
|
VMSTATE_BOOL(processing, struct DBDMA_io),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
static const VMStateDescription vmstate_dbdma_cmd = {
|
|
|
|
.name = "dbdma_cmd",
|
2010-12-03 00:07:26 +01:00
|
|
|
.version_id = 0,
|
|
|
|
.minimum_version_id = 0,
|
2016-01-06 21:37:25 +01:00
|
|
|
.fields = (VMStateField[]) {
|
|
|
|
VMSTATE_UINT16(req_count, dbdma_cmd),
|
|
|
|
VMSTATE_UINT16(command, dbdma_cmd),
|
|
|
|
VMSTATE_UINT32(phy_addr, dbdma_cmd),
|
|
|
|
VMSTATE_UINT32(cmd_dep, dbdma_cmd),
|
|
|
|
VMSTATE_UINT16(res_count, dbdma_cmd),
|
|
|
|
VMSTATE_UINT16(xfer_status, dbdma_cmd),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
static const VMStateDescription vmstate_dbdma_channel = {
|
|
|
|
.name = "dbdma_channel",
|
|
|
|
.version_id = 1,
|
|
|
|
.minimum_version_id = 1,
|
2014-04-16 16:01:33 +02:00
|
|
|
.fields = (VMStateField[]) {
|
2010-12-03 00:07:26 +01:00
|
|
|
VMSTATE_UINT32_ARRAY(regs, struct DBDMA_channel, DBDMA_REGS),
|
2016-01-06 21:37:25 +01:00
|
|
|
VMSTATE_STRUCT(io, struct DBDMA_channel, 0, vmstate_dbdma_io, DBDMA_io),
|
|
|
|
VMSTATE_STRUCT(current, struct DBDMA_channel, 0, vmstate_dbdma_cmd,
|
|
|
|
dbdma_cmd),
|
2010-12-03 00:07:26 +01:00
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
2009-01-30 21:39:32 +01:00
|
|
|
|
2010-12-03 00:07:26 +01:00
|
|
|
static const VMStateDescription vmstate_dbdma = {
|
|
|
|
.name = "dbdma",
|
2016-01-06 21:37:25 +01:00
|
|
|
.version_id = 3,
|
|
|
|
.minimum_version_id = 3,
|
2014-04-16 16:01:33 +02:00
|
|
|
.fields = (VMStateField[]) {
|
2010-12-03 00:07:26 +01:00
|
|
|
VMSTATE_STRUCT_ARRAY(channels, DBDMAState, DBDMA_CHANNELS, 1,
|
|
|
|
vmstate_dbdma_channel, DBDMA_channel),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
2008-12-30 20:01:19 +01:00
|
|
|
|
2017-09-24 16:47:41 +02:00
|
|
|
static void mac_dbdma_reset(DeviceState *d)
|
2008-12-28 19:27:10 +01:00
|
|
|
{
|
2017-09-24 16:47:41 +02:00
|
|
|
DBDMAState *s = MAC_DBDMA(d);
|
2009-01-30 21:39:32 +01:00
|
|
|
int i;
|
|
|
|
|
2017-09-24 16:47:41 +02:00
|
|
|
for (i = 0; i < DBDMA_CHANNELS; i++) {
|
2010-12-03 00:04:02 +01:00
|
|
|
memset(s->channels[i].regs, 0, DBDMA_SIZE);
|
2017-09-24 16:47:41 +02:00
|
|
|
}
|
2008-12-28 19:27:10 +01:00
|
|
|
}
|
|
|
|
|
2016-02-25 13:02:11 +01:00
|
|
|
static void dbdma_unassigned_rw(DBDMA_io *io)
|
|
|
|
{
|
|
|
|
DBDMA_channel *ch = io->channel;
|
2016-07-10 20:08:57 +02:00
|
|
|
dbdma_cmd *current = &ch->current;
|
|
|
|
uint16_t cmd;
|
2016-02-25 13:02:11 +01:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "%s: use of unassigned channel %d\n",
|
|
|
|
__func__, ch->channel);
|
2017-09-17 19:15:45 +02:00
|
|
|
ch->io.processing = false;
|
2016-07-10 20:08:57 +02:00
|
|
|
|
|
|
|
cmd = le16_to_cpu(current->command) & COMMAND_MASK;
|
|
|
|
if (cmd == OUTPUT_MORE || cmd == OUTPUT_LAST ||
|
|
|
|
cmd == INPUT_MORE || cmd == INPUT_LAST) {
|
2017-09-17 19:15:45 +02:00
|
|
|
current->xfer_status = cpu_to_le16(ch->regs[DBDMA_STATUS]);
|
2016-07-10 20:08:57 +02:00
|
|
|
current->res_count = cpu_to_le16(io->len);
|
|
|
|
dbdma_cmdptr_save(ch);
|
|
|
|
}
|
2016-02-25 13:02:11 +01:00
|
|
|
}
|
|
|
|
|
2017-09-17 19:15:45 +02:00
|
|
|
static void dbdma_unassigned_flush(DBDMA_io *io)
|
|
|
|
{
|
|
|
|
DBDMA_channel *ch = io->channel;
|
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "%s: use of unassigned channel %d\n",
|
|
|
|
__func__, ch->channel);
|
|
|
|
}
|
|
|
|
|
2017-09-24 16:47:41 +02:00
|
|
|
static void mac_dbdma_init(Object *obj)
|
|
|
|
{
|
|
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
|
|
|
|
DBDMAState *s = MAC_DBDMA(obj);
|
|
|
|
int i;
|
2009-01-30 21:39:32 +01:00
|
|
|
|
2014-05-26 10:27:58 +02:00
|
|
|
for (i = 0; i < DBDMA_CHANNELS; i++) {
|
2016-02-25 13:02:11 +01:00
|
|
|
DBDMA_channel *ch = &s->channels[i];
|
|
|
|
|
|
|
|
ch->rw = dbdma_unassigned_rw;
|
|
|
|
ch->flush = dbdma_unassigned_flush;
|
|
|
|
ch->channel = i;
|
|
|
|
ch->io.channel = ch;
|
2014-05-26 10:27:58 +02:00
|
|
|
}
|
|
|
|
|
2017-09-24 16:47:41 +02:00
|
|
|
memory_region_init_io(&s->mem, obj, &dbdma_ops, s, "dbdma", 0x1000);
|
|
|
|
sysbus_init_mmio(sbd, &s->mem);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mac_dbdma_realize(DeviceState *dev, Error **errp)
|
|
|
|
{
|
|
|
|
DBDMAState *s = MAC_DBDMA(dev);
|
2009-01-30 21:39:32 +01:00
|
|
|
|
2013-06-30 02:22:41 +02:00
|
|
|
s->bh = qemu_bh_new(DBDMA_run_bh, s);
|
2017-09-24 16:47:41 +02:00
|
|
|
}
|
2009-01-30 21:39:32 +01:00
|
|
|
|
2017-09-24 16:47:41 +02:00
|
|
|
static void mac_dbdma_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
|
|
|
|
dc->realize = mac_dbdma_realize;
|
|
|
|
dc->reset = mac_dbdma_reset;
|
|
|
|
dc->vmsd = &vmstate_dbdma;
|
2007-10-29 00:42:18 +01:00
|
|
|
}
|
2017-09-24 16:47:41 +02:00
|
|
|
|
|
|
|
static const TypeInfo mac_dbdma_type_info = {
|
|
|
|
.name = TYPE_MAC_DBDMA,
|
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
|
|
.instance_size = sizeof(DBDMAState),
|
|
|
|
.instance_init = mac_dbdma_init,
|
|
|
|
.class_init = mac_dbdma_class_init
|
|
|
|
};
|
|
|
|
|
|
|
|
static void mac_dbdma_register_types(void)
|
|
|
|
{
|
|
|
|
type_register_static(&mac_dbdma_type_info);
|
|
|
|
}
|
|
|
|
|
|
|
|
type_init(mac_dbdma_register_types)
|