Hexagon HVX (target/hexagon) semantics generator
Add HVX support to the semantics generator Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
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@ -44,6 +44,11 @@ int main(int argc, char *argv[])
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* Q6INSN(A2_add,"Rd32=add(Rs32,Rt32)",ATTRIBS(),
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* Q6INSN(A2_add,"Rd32=add(Rs32,Rt32)",ATTRIBS(),
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* "Add 32-bit registers",
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* "Add 32-bit registers",
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* { RdV=RsV+RtV;})
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* { RdV=RsV+RtV;})
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* HVX instructions have the following form
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* EXTINSN(V6_vinsertwr, "Vx32.w=vinsert(Rt32)",
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* ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VX),
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* "Insert Word Scalar into Vector",
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* VxV.uw[0] = RtV;)
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*/
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*/
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#define Q6INSN(TAG, BEH, ATTRIBS, DESCR, SEM) \
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#define Q6INSN(TAG, BEH, ATTRIBS, DESCR, SEM) \
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do { \
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do { \
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@ -59,8 +64,23 @@ int main(int argc, char *argv[])
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")\n", \
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")\n", \
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#TAG, STRINGIZE(ATTRIBS)); \
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#TAG, STRINGIZE(ATTRIBS)); \
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} while (0);
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} while (0);
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#define EXTINSN(TAG, BEH, ATTRIBS, DESCR, SEM) \
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do { \
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fprintf(outfile, "SEMANTICS( \\\n" \
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" \"%s\", \\\n" \
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" %s, \\\n" \
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" \"\"\"%s\"\"\" \\\n" \
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")\n", \
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#TAG, STRINGIZE(BEH), STRINGIZE(SEM)); \
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fprintf(outfile, "ATTRIBUTES( \\\n" \
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" \"%s\", \\\n" \
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" \"%s\" \\\n" \
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")\n", \
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#TAG, STRINGIZE(ATTRIBS)); \
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} while (0);
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#include "imported/allidefs.def"
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#include "imported/allidefs.def"
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#undef Q6INSN
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#undef Q6INSN
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#undef EXTINSN
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/*
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/*
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* Process the macro definitions
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* Process the macro definitions
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@ -81,6 +101,19 @@ int main(int argc, char *argv[])
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")\n", \
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")\n", \
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#MNAME, STRINGIZE(BEH), STRINGIZE(ATTRS));
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#MNAME, STRINGIZE(BEH), STRINGIZE(ATTRS));
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#include "imported/macros.def"
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#include "imported/macros.def"
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#undef DEF_MACRO
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/*
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* Process the macros for HVX
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*/
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#define DEF_MACRO(MNAME, BEH, ATTRS) \
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fprintf(outfile, "MACROATTRIB( \\\n" \
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" \"%s\", \\\n" \
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" \"\"\"%s\"\"\", \\\n" \
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" \"%s\" \\\n" \
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")\n", \
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#MNAME, STRINGIZE(BEH), STRINGIZE(ATTRS));
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#include "imported/allext_macros.def"
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#undef DEF_MACRO
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#undef DEF_MACRO
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fclose(outfile);
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fclose(outfile);
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@ -145,6 +145,9 @@ def compute_tag_immediates(tag):
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## P predicate register
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## P predicate register
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## R GPR register
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## R GPR register
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## M modifier register
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## M modifier register
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## Q HVX predicate vector
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## V HVX vector register
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## O HVX new vector register
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## regid can be one of the following
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## regid can be one of the following
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## d, e destination register
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## d, e destination register
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## dd destination register pair
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## dd destination register pair
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@ -180,6 +183,9 @@ def is_readwrite(regid):
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def is_scalar_reg(regtype):
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def is_scalar_reg(regtype):
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return regtype in "RPC"
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return regtype in "RPC"
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def is_hvx_reg(regtype):
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return regtype in "VQ"
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def is_old_val(regtype, regid, tag):
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def is_old_val(regtype, regid, tag):
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return regtype+regid+'V' in semdict[tag]
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return regtype+regid+'V' in semdict[tag]
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@ -203,6 +209,13 @@ def need_ea(tag):
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def skip_qemu_helper(tag):
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def skip_qemu_helper(tag):
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return tag in overrides.keys()
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return tag in overrides.keys()
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def is_tmp_result(tag):
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return ('A_CVI_TMP' in attribdict[tag] or
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'A_CVI_TMP_DST' in attribdict[tag])
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def is_new_result(tag):
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return ('A_CVI_NEW' in attribdict[tag])
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def imm_name(immlett):
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def imm_name(immlett):
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return "%siV" % immlett
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return "%siV" % immlett
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