ths
6e473128b6
Handle PX/UX status flags correctly, by Aurelien Jarno.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2892 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-28 20:36:48 +00:00
ths
9b9e4393dd
MIPS64 addressing fixes, by Aurelien Jarno.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2888 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-28 17:03:28 +00:00
ths
fd88b6abab
The 24k wants more watch and srsmap registers.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2849 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-23 08:24:25 +00:00
ths
df1561e22d
The previous patch to make breakpoints work was a performance
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disaster, use a similiar hack as ARM does instead.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2848 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-23 08:18:27 +00:00
ths
93b12ccc62
Fix indexed FP load/store instructions.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2837 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-20 01:36:29 +00:00
ths
57fa1fb31c
More MIPS 64-bit FPU support.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2834 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-19 20:29:41 +00:00
ths
f469b9db01
Fix slti/sltiu for MIPS64, by Aurelien Jarno.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2833 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-19 17:45:43 +00:00
ths
fd4a04ebb2
- Move FPU exception handling into helper functions, since they are big.
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- Fix FP-conditional branches.
- Check FPU register mode at runtime, not translation time, as the F64
status bit can change.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2828 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-18 11:55:54 +00:00
ths
34ae7b51f5
Work around the lack of proper handling for self-modifying code.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2827 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-18 01:13:09 +00:00
ths
69d357286d
More generic 64 bit multiplication support, by Aurelien Jarno.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2821 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-16 11:59:40 +00:00
ths
100ce98812
Full MIPS64 MMU implementation, by Aurelien Jarno.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2820 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-13 19:22:13 +00:00
ths
f1b0aa5de7
Fix mfc0 and dmtc0 instructions on MIPS64, by Aurelien Jarno.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2819 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-13 18:39:10 +00:00
ths
7b62f20c08
Delete misleading comment.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2814 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-13 15:29:26 +00:00
ths
f2e9ebef12
MMU code improvements, by Aurelien Jarno.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2811 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-13 14:07:26 +00:00
ths
29929e3490
MIPS TLB style selection at runtime, by Herve Poussineau.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2809 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-13 13:49:44 +00:00
ths
5a1e8ffbe7
Implemented cabs FP instructions, and improve exception handling for
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trunc/floor/ceil/round.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2804 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-11 17:08:26 +00:00
ths
fbcc68286a
Implement FP madd/msub, wire up bc1any[24][ft].
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2802 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-11 09:59:10 +00:00
ths
a6763a5881
Fix MIPS64 address computation specialcase, by Aurelien Jarno.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2793 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-09 09:33:33 +00:00
ths
09c69c5b23
Work around gcc's mips define, spotted by Stefan Weil.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2786 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-08 20:51:26 +00:00
ths
5a5012ecbd
MIPS 64-bit FPU support, plus some collateral bugfixes in the
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conditional branch handling.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2779 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-07 13:55:33 +00:00
ths
fcb4a419f5
Choose number of TLBs at runtime, by Herve Poussineau.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2693 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-17 15:26:47 +00:00
ths
171b31e7c7
Don't use T2 for INS, it conflicts with branch delay slot handling.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2674 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-15 21:26:37 +00:00
ths
80c27194a7
Fix qemu SIGFPE caused by division-by-zero due to underflow.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2673 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-15 21:21:33 +00:00
ths
16c00cb2c2
Restart interrupts after an exception.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2664 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-14 12:56:46 +00:00
ths
e58c8ba5f6
Another fix for CP0 Cause register handling.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2658 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-13 20:17:54 +00:00
ths
534ce69ff0
More Context/Xcontext fixes. Ifdef some 64bit-only ops, they may
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end up empty for 32bit mips, which dyngen trips over.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2648 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-11 02:13:00 +00:00
ths
c090a8f440
Fix CP0_IntCtl handling.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2645 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-09 14:17:31 +00:00
ths
c50da3df61
Proper handling of reserved bits in the context register.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2644 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-09 14:16:30 +00:00
ths
4e7a4a4e84
Mark watchpoint features as unimplemented.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2643 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-09 14:15:41 +00:00
ths
97428a4d84
Fix exception handling cornercase for rdhwr.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2641 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-09 14:13:40 +00:00
ths
f757d6ff29
Fix ins/ext cornercase.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2627 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-07 01:09:17 +00:00
ths
f41c52f170
Save state for all CP0 instructions, they may throw a CPU exception.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2622 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-06 18:46:01 +00:00
ths
5a63bcb2d2
Fix rotr immediate ops, mask shift/rotate arguments to their allowed
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size.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2614 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-05 23:20:05 +00:00
ths
1579a72ec5
Fix RDHWR handling. Code formatting. Don't use *_direct versions to raise
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exceptions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2611 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-05 23:16:25 +00:00
ths
60aa19abef
Actually enable 64bit configuration.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2565 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-01 12:36:18 +00:00
ths
24c7b0e330
Sanitize mips exception handling.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2546 c046a42c-6fe2-441c-8c8c-71466251a162
2007-03-30 16:44:54 +00:00
ths
e397ee3382
Fix enough FPU/R2 support to get 24Kf going.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2528 c046a42c-6fe2-441c-8c8c-71466251a162
2007-03-23 00:43:28 +00:00
ths
39d51eb8bc
Fix BD flag handling, cause register contents, implement some more bits
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for R2 interrupt handling.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2493 c046a42c-6fe2-441c-8c8c-71466251a162
2007-03-18 12:43:40 +00:00
ths
6f5b89a07c
MIPS Userland TLS register emulation, by Daniel Jacobowitz.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2465 c046a42c-6fe2-441c-8c8c-71466251a162
2007-03-02 20:48:00 +00:00
ths
36d2395873
MIPS FPU dynamic activation, part 1, by Herve Poussineau.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2463 c046a42c-6fe2-441c-8c8c-71466251a162
2007-02-28 22:37:42 +00:00
ths
00a709c7b9
Fix mips FPU emulation, 32 bit data types are allowed to use odd registers.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2454 c046a42c-6fe2-441c-8c8c-71466251a162
2007-02-27 19:27:51 +00:00
ths
925fd0f202
Fix sign-extension of VPN field in TLB, by Herve Poussineau.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2433 c046a42c-6fe2-441c-8c8c-71466251a162
2007-02-18 00:19:08 +00:00
ths
b29a0341d7
EBase is limited to KSEG0/KSEG1 even on 64bit CPUs.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2351 c046a42c-6fe2-441c-8c8c-71466251a162
2007-01-24 18:01:23 +00:00
ths
4de9b249d3
Reworking MIPS interrupt handling, by Aurelien Jarno.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2350 c046a42c-6fe2-441c-8c8c-71466251a162
2007-01-24 01:47:51 +00:00
ths
9c2149c8e0
Implementing dmfc/dmtc.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2348 c046a42c-6fe2-441c-8c8c-71466251a162
2007-01-23 22:45:22 +00:00
ths
0feef828e1
Fix bad data type.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2284 c046a42c-6fe2-441c-8c8c-71466251a162
2007-01-01 20:35:21 +00:00
ths
5dc4b74480
Scrap SIGN_EXTEND32.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2251 c046a42c-6fe2-441c-8c8c-71466251a162
2006-12-21 13:48:28 +00:00
ths
c570fd169c
Preliminiary MIPS64 support, disabled by default due to performance impact.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2250 c046a42c-6fe2-441c-8c8c-71466251a162
2006-12-21 01:19:56 +00:00
ths
71fb7241c6
Fix build of MIPS target without FPU support.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2233 c046a42c-6fe2-441c-8c8c-71466251a162
2006-12-07 20:07:37 +00:00
ths
7a387fffce
Add MIPS32R2 instructions, and generally straighten out the instruction
...
decoding. This is also the first percent towards MIPS64 support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2224 c046a42c-6fe2-441c-8c8c-71466251a162
2006-12-06 20:17:30 +00:00