Commit Graph

844 Commits

Author SHA1 Message Date
Richard Henderson 96fbd7de36 tcg-arm: Remove long jump from tcg_out_goto_label
Branches within a TB will always be within 16MB.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27 02:16:45 +02:00
Richard Henderson df5e0ef711 tcg-arm: Convert to CONFIG_QEMU_LDST_OPTIMIZATION
Move the slow path out of line, as the TODO's mention.
This allows the fast path to be unconditional, which can
speed up the fast path as well, depending on the core.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27 02:16:45 +02:00
Richard Henderson 302fdde73f tcg-arm: Use movi32 + blx for calls on v7
Work better with branch predition when we have movw+movt,
as the size of the code is the same.  Perhaps re-evaluate
when we have a proper constant pool.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27 02:16:45 +02:00
Richard Henderson 595b5397cc tcg-arm: Delete the 'S' constraint
After the previous patch, 's' and 'S' are the same.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27 02:16:45 +02:00
Richard Henderson 702b33b1d5 tcg-arm: Improve scheduling of tcg_out_tlb_read
The schedule was fully serial, with no possibility for dual issue.
The old schedule had a minimal issue of 7 cycles; the new schedule
has a minimal issue of 5 cycles.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27 02:16:45 +02:00
Richard Henderson cee87be80a tcg-arm: Split out tcg_out_tlb_read
Share code between qemu_ld and qemu_st to process the tlb.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27 02:16:45 +02:00
Richard Henderson 9feac1d770 tcg-arm: Cleanup most primitive load store subroutines
Use even more primitive helper functions to avoid lots of duplicated code.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27 02:16:44 +02:00
Richard Henderson 34358a12c8 tcg-arm: Cleanup multiply subroutines
Make the code more readable by only having one copy of the magic
numbers, swapping registers as needed prior to that.  Speed the
compiler by not applying the rd == rn avoidance for v6 or later.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27 02:16:44 +02:00
Richard Henderson 13dd6fb962 tcg-arm: Use R12 for the tcg temporary
R12 is call clobbered, while R8 is call saved.  This change
gives tcg one more call saved register for real data.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27 02:16:44 +02:00
Richard Henderson 4346457a47 tcg-arm: Use TCG_REG_TMP name for the tcg temporary
Don't hard-code R8.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27 02:16:44 +02:00
Richard Henderson 0637c56c99 tcg-arm: Implement division instructions
An armv7 extension implements division, present on Cortex A15.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27 02:16:44 +02:00
Richard Henderson b6b24cb031 tcg-arm: Implement deposit for armv7
We have BFI and BFC available for implementing it.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27 02:16:44 +02:00
Richard Henderson e86e0f2807 tcg-arm: Improve constant generation
Try fully rotated arguments to mov and mvn before trying movt
or full decomposition.  Begin decomposition with mvn when it
looks like it'll help.  Examples include

-:        mov   r9, #0x00000fa0
-:        orr   r9, r9, #0x000ee000
-:        orr   r9, r9, #0x0ff00000
-:        orr   r9, r9, #0xf0000000
+:        mvn   r9, #0x0000005f
+:        eor   r9, r9, #0x00011000

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27 02:16:43 +02:00
Richard Henderson 2df3f1ee68 tcg-arm: Handle constant arguments to add2/sub2
We get to re-use the _rIN and _rIK subroutines to handle the various
combinations of add vs sub.  Fold the << 21 into the opcode enum values
so that we can explicitly add TO_CPSR as desired.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27 02:16:43 +02:00
Richard Henderson 5d53b4c93c tcg-arm: Use tcg_out_dat_rIN for compares
This allows us to emit CMN instructions.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27 02:16:43 +02:00
Richard Henderson d9fda57549 tcg-arm: Allow constant first argument to sub
This allows the generation of RSB instructions.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27 02:16:43 +02:00
Richard Henderson a9a86ae95d tcg-arm: Handle negated constant arguments to and/sub
This greatly improves code generation for addition of small
negative constants.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27 02:16:43 +02:00
Richard Henderson 19b62bf414 tcg-arm: Use bic to implement and with constant
This greatly improves the code we can produce for deposit
without armv7 support.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27 02:16:42 +02:00
Richard Henderson d6b64b2b60 tcg: Log the contents of the prologue with -d out_asm
This makes it easier to verify changes to the code
generating the prologue.

[Aurelien: change the format from %i to %zu]

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27 02:15:55 +02:00
Richard Henderson fc4d60ee16 tcg-arm: Fix local stack frame
We were not allocating TCG_STATIC_CALL_ARGS_SIZE, so this meant that
any helper with more than 4 arguments would clobber the saved regs.
Realizing that we're supposed to have this memory pre-allocated means
we can clean up the tcg_out_arg functions, which were trying to do
more stack allocation.

Allocate stack memory for the TCG temporaries while we're at it.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27 01:19:20 +02:00
Aurelien Jarno ed605126a8 tcg: fix deposit_i64 op on 32-bit targets
On 32-bit TCG targets, when emulating deposit_i64 with a mov_i32 +
deposit_i32, care should be taken to not overwrite the low part of
the second argument before the deposit when it is the same the
destination.

This fixes the shld instruction in qemu-system-x86_64, which in turns
fixes booting "system rescue CD version 2.8.0" on this target.

Reported-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-04-27 01:10:18 +02:00
Richard Henderson 39dc85b985 tcg-ppc64: Handle deposit of zero
The TCG optimizer does great work when inserting constants, being able
to fold the open-coded deposit expansion to just an AND or an OR.  Avoid
a bit the regression caused by having the deposit opcode by expanding
deposit of zero as an AND.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15 20:09:55 +02:00
Richard Henderson 6645c147db tcg-ppc64: Implement mulu2/muls2_i64
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15 20:09:54 +02:00
Richard Henderson 6c858762de tcg-ppc64: Implement add2/sub2_i64
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15 20:09:54 +02:00
Richard Henderson 1e6e9aca15 tcg-ppc64: Use getauxval for ISA detection
Glibc 2.16 includes an easy way to get feature bits previously
buried in /proc or the program startup auxiliary vector.  Use it.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15 20:09:54 +02:00
Richard Henderson 027ffea972 tcg-ppc64: Implement movcond
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15 20:09:54 +02:00
Richard Henderson 70fac59a2a tcg-ppc64: Use ISEL for setcond
There are a few simple special cases that should be handled first.
Break these out to subroutines to avoid code duplication.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15 20:09:53 +02:00
Richard Henderson 6995a4a063 tcg-ppc64: Use MFOCRF instead of MFCR
It takes half the cycles to read one CR register instead of all 8.
This is a backward compatible addition to the ISA, so chips prior
to Power 2.00 spec will simply continue to read the entire CR register.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15 20:09:53 +02:00
Richard Henderson 991041a4eb tcg-ppc64: Cleanup i32 constants to tcg_out_cmp
Nothing else in the call chain ensures that these
constants don't have garbage in the high bits.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15 20:09:53 +02:00
Richard Henderson 4c314da6d1 tcg-ppc64: Use TCGType throughout compares
The optimization/bug being fixed is that tcg_out_cmp was not applying the
right type to loading a constant, in the case it can't be implemented
directly.  Rather than recomputing the TCGType enum from the arch64 bool,
pass around the original TCGType throughout.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15 20:09:52 +02:00
Richard Henderson ef809300fc tcg-ppc64: Use I constraint for mul
The mul_i32 pattern was loading non-16-bit constants into a register,
when we can get the middle-end to do that for us.  The mul_i64 pattern
was not considering that MULLI takes 64-bit inputs.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15 20:09:52 +02:00
Richard Henderson 33de9ed223 tcg-ppc64: Implement deposit
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15 20:09:52 +02:00
Richard Henderson 37251b98db tcg-ppc64: Handle constant inputs for some compound logicals
Since we have special code to handle and/or/xor with a constant,
apply the same to andc/orc/eqv with a constant.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15 20:09:51 +02:00
Richard Henderson ce1010d6e3 tcg-ppc64: Implement compound logicals
Mostly copied from the ppc32 port.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15 20:09:51 +02:00
Richard Henderson 68aebd45b1 tcg-ppc64: Implement bswap64
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15 20:09:51 +02:00
Richard Henderson 5d22158200 tcg-ppc64: Implement bswap16 and bswap32
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15 20:09:44 +02:00
Richard Henderson 313d91c778 tcg-ppc64: Implement rotates
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15 19:55:38 +02:00
Richard Henderson 49d9870a54 tcg-ppc64: Streamline qemu_ld/st insn selection
Using a table to look up insns of the right width and sign.
Include support for the Power 2.06 LDBRX and STDBRX insns.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15 19:55:35 +02:00
Richard Henderson 28f2dba6dc tcg-ppc64: Use automatic implementation of ext32u_i64
The enhancements to and immediate obviate this.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15 19:55:31 +02:00
Richard Henderson 637af30c76 tcg-ppc64: Improve and_i64 with constant
Use RLDICL and RLDICR.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15 19:55:27 +02:00
Richard Henderson a9249dff4d tcg-ppc64: Improve and_i32 with constant
Use RLWINM

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15 19:55:27 +02:00
Richard Henderson dce74c57bb tcg-ppc64: Tidy or and xor patterns.
Handle constants in common code; we'll want to reuse that later.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15 19:55:26 +02:00
Richard Henderson 148bdd2373 tcg-ppc64: Allow constant first argument to sub
Using SUBFIC for 16-bit signed constants.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15 19:55:22 +02:00
Richard Henderson ee924fa6b3 tcg-ppc64: Improve constant add and sub ops.
Improve constant addition -- previously we'd emit useless addi with 0.
Use new constraints to force the driver to pull full 64-bit constants
into a register.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15 19:55:15 +02:00
Richard Henderson 3d582c6179 tcg-ppc64: Rearrange integer constant constraints
We'll need a zero, and Z makes more sense for that.  Make sure we
have a full compliment of signed and unsigned 16 and 32-bit tests.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15 19:52:05 +02:00
Richard Henderson 421233a146 tcg-ppc64: Cleanup tcg_out_movi
The test for using movi32 was sub-optimal for TCG_TYPE_I32, comparing
a signed 32-bit quantity against an unsigned 32-bit quantity.

When possible, use addi+oris for 32-bit unsigned constants.  Otherwise,
standardize on addi+oris+ori instead of addis+ori+rldicl.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15 19:52:04 +02:00
Richard Henderson 752c1fdb6d tcg-ppc64: Fix setcond_i32
We weren't ignoring the high 32 bits during a NE comparison.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15 19:51:50 +02:00
Richard Henderson 2fd8eddcab tcg-ppc64: Introduce and use TAI and SAI
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15 19:44:48 +02:00
Richard Henderson 5e916c287e tcg-ppc64: Introduce and use tcg_out_shri64
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15 19:44:46 +02:00
Richard Henderson 0a9564b964 tcg-ppc64: Introduce and use tcg_out_shli64
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15 19:44:44 +02:00