Commit Graph

41 Commits

Author SHA1 Message Date
Max Filippov 6b814719b4 target-xtensa: raise an exception for invalid and reserved opcodes
This includes opcodes from disabled features and those marked reserved in the ISA.
Also end TB on opcodes that definitely generate an exception: illegal
instructions, syscall and privileged instructions.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2011-11-02 05:05:52 +04:00
Max Filippov 0c852e171b target-xtensa: handle cache options in the overlay tool
Cache options must be enabled for the cores that have cache to avoid
illegal instruction exceptions.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2011-11-02 05:05:52 +04:00
Max Filippov 53a72dfda5 target-xtensa: mask out undefined bits of WINDOWSTART SR
According to ISA, table 5-156, bits 32:NAREG/4 of the WINDOWSTART SR
must be zero.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2011-11-02 05:05:38 +04:00
Max Filippov 935f7a2b42 target-xtensa: add fsf core
This is FSF big endian core implemented through linux overlay.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16 10:40:16 +00:00
Max Filippov 53add759be target-xtensa: add dc232b core
This is Diamond 232L Standard Core Rev.B (LE), implemented through
linux/gdb overlay.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16 10:40:02 +00:00
Max Filippov ac8b7db493 target-xtensa: extract core configuration from overlay
Introduce overlay_tool.h that defines core configuration blocks from
data available in the linux architecture variant overlay.

Overlay data is automatically generated in the core configuration
process by Tensilica tools and can be directly converted to qemu xtensa
core description by overlay_tool.h

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16 10:39:52 +00:00
Max Filippov b8929a549f target-xtensa: implement external interrupt mapping
Xtensa cores may have different mapping of external interrupt pins to
internal IRQ numers. Implement API to acquire core IRQ by its external
interrupt number.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16 10:39:41 +00:00
Max Filippov 63f95e4c65 target-xtensa: remove hand-written xtensa cores implementations
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16 10:39:36 +00:00
Max Filippov 7f65f4b059 target-xtensa: increase xtensa options accuracy
- add separate options for each operation in the MISC_OP;
- add an option for MULSH/MULUH;
- put S32C1I under conditional store option.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16 10:39:27 +00:00
Max Filippov 6825b6c33c target-xtensa: implement MAC16 option
See ISA, 4.3.7 for the details.

- add ACC and MR special registers;
- implement MAC16 and all inner MAC* opcode groups.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-15 21:03:40 +00:00
Max Filippov 890c6333b2 target-xtensa: fix guest hang on masked CCOMPARE interrupt
QEMU timer is used to post CCOMPARE interrupt when the core is halted.
If that CCOMPARE interrupt is masked off then the timer must be rearmed
in the callback, otherwise it will be rearmed next time the core goes to
halt by the waiti instruction.

Add test case into timer testsuite.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-15 21:03:03 +00:00
Blue Swirl bccd9ec5f0 softmmu_header: pass CPUState to tlb_fill
Pass CPUState pointer to tlb_fill() instead of architecture local
cpu_single_env hacks.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-01 09:31:26 +00:00
Max Filippov 47d05a8629 target-xtensa: add dc232b core and board
This is Diamond 232L Standard Core Rev.B (LE).

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10 16:57:40 +00:00
Max Filippov 4dd85b6b63 target-xtensa: implement boolean option
See ISA, 4.3.9

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10 16:57:40 +00:00
Max Filippov b67ea0cd74 target-xtensa: implement memory protection options
- TLB opcode group;
- region protection option (ISA, 4.6.3);
- region translation option (ISA, 4.6.4);
- MMU option (ISA, 4.6.5).

Cache control attribute bits are not used by this implementation.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10 16:57:40 +00:00
Max Filippov ccfcaba6fd target-xtensa: add gdb support
Specific xtensa processor overlay for GDB contains register map in
the gdb/xtensa-config.c. This description is used by the GDB to e.g.
parse 'g' response packets and it may be reused in the qemu's gdbstub
(only XTREG definitions for non-pseudoregisters are needed).

Currently mainline GDB does not support operations with privileged SRs
(see http://sourceware.org/ml/gdb/2011-07/msg00075.html). This support
may be enabled, see NUM_CORE_REGS comment in the gdbstub.c

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10 16:57:40 +00:00
Max Filippov 97836ceed3 target-xtensa: implement relocatable vectors
See ISA, 4.4.3 for details.

Vector addresses recorded in core configuration are absolute values that
correspond to default VECBASE value.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10 16:57:40 +00:00
Max Filippov f3df4c04d8 target-xtensa: implement CPENABLE and PRID SRs
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10 16:57:39 +00:00
Max Filippov 772177c194 target-xtensa: implement accurate window check
See ISA, 4.7.1.3 for details.

Window check is inserted before commands that push "used register
watermark" beyond its current level. Used register watermark is reset on
instructions that change WINDOW_BASE/WINDOW_START SRs.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10 16:57:39 +00:00
Max Filippov b994e91b00 target-xtensa: implement interrupt option
See ISA, 4.4.6 (interrupt option), 4.4.7 (high priority interrupt
option) and 4.4.8 (timer interrupt option) for details.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10 16:57:39 +00:00
Max Filippov 1ddeaa5d42 target-xtensa: implement SIMCALL
Tensilica iss provides support for applications running in freestanding
environment through SIMCALL command. It is used by Tensilica libc to
access argc/argv, for file I/O, etc.

Note that simcalls that accept buffer addresses expect virtual addresses.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10 16:57:39 +00:00
Max Filippov 5b4e481b04 target-xtensa: implement unaligned exception option
See ISA, 4.4.4 for details.

Correct (aligned as per ISA) address for unaligned access is generated
in case this option is not enabled.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10 16:57:39 +00:00
Max Filippov 6ad6dbf791 target-xtensa: implement extended L32R
See ISA, 4.3.3 for details.

TB flag XTENSA_TBFLAG_LITBASE is used to track enable bit of LITBASE SR.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10 16:57:39 +00:00
Max Filippov 797d780b13 target-xtensa: implement loop option
See ISA, 4.3.2 for details.

Operations that change LEND SR value invalidate TBs at the old and at
the new LEND. LEND value at TB compilation time is considered constant
and loop instruction is generated based on this value.

Invalidation may be avoided for the TB at the old LEND address, since
looping code verifies actual LEND value.

Invalidation may be avoided for the TB at the new LEND address if
there's a way to associate LEND address with TB at compilation time and
later verify that it doesn't change.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10 16:57:39 +00:00
Max Filippov 553e44f906 target-xtensa: implement windowed registers
See ISA, 4.7.1 for details.

Physical registers and currently visible window are separate fields in
CPUEnv. Only current window is accessible to TCG. On operations that
change window base helpers copy current window to and from physical
registers.

Window overflow check described in 4.7.1.3 is in separate patch.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10 16:57:39 +00:00
Max Filippov f76ebf55cd target-xtensa: implement RST2 group (32 bit mul/div/rem)
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10 16:57:38 +00:00
Max Filippov 40643d7c0f target-xtensa: implement exceptions
- mark privileged opcodes with ring check;
- make debug exception on exception handler entry.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10 16:57:38 +00:00
Max Filippov f0a548b93d target-xtensa: add PS register and access control
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10 16:57:38 +00:00
Max Filippov 8ffc2d0d97 target-xtensa: implement CACHE group
All operations in this group are no-ops, because cache ought to be
transparent to applications. However cache may be abused, then we'll
need to actually implement these opcodes.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10 16:57:38 +00:00
Max Filippov 28067b2288 target-xtensa: implement SYNC group
All operations in this group are no-ops, because there are no delayed
side effects.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10 16:57:38 +00:00
Max Filippov 91a5bb76d4 target-xtensa: mark reserved and TBD opcodes
Reserved opcodes must generate illegal instruction exception. Usually
they signal emulation quality problems.
Not implemented opcodes are good to see.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10 16:57:38 +00:00
Max Filippov 809377aa52 target-xtensa: implement LSAI group
- base + offset load/store operations for 1/2/4 byte values;
- cache operations (not implemented);
- multiprocessor synchronization operations.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10 16:57:38 +00:00
Max Filippov 3580ecad0a target-xtensa: implement shifts (ST1 and RST1 groups)
- ST1: SAR (shift amount special register) manipulation, NSA(U);
- RST1: shifts, 16-bit multiplication.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10 16:57:38 +00:00
Max Filippov b8132eff89 target-xtensa: implement RST3 group
- access to Special Registers (wsr, rsr);
- access to User Registers (wur, rur);
- misc. operations option (value clamp, sign extension, min, max);
- conditional moves.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10 16:57:38 +00:00
Max Filippov 2af3da9183 target-xtensa: add special and user registers
Special Registers hold the majority of the state added to the processor
by the options. See ISA, 5.3 for details.

User Registers hold state added in support of designer's TIE and in some
cases of options that Tensilica provides. See ISA, 5.4 for details.

Only registers mapped in sregnames or uregnames are considered valid.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10 16:57:37 +00:00
Max Filippov 5da4a6a8c5 target-xtensa: implement JX/RET0/CALLX
Group SNM0 (indirect jumps and calls).

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10 16:57:37 +00:00
Max Filippov bd57fb91ae target-xtensa: implement conditional jumps
- BZ (comparison to zero);
- BI0 (comparison to signed immediate);
- BI1 (comparison to unsigned immediate);
- B (two registers comparison, bit sets comparison);
- BEQZ.N/BNEZ.N (narrow comparison to zero).

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10 16:57:37 +00:00
Max Filippov f331fe5e5f target-xtensa: implement RT0 group
NEG and ABS are the only members of RT0 group.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10 16:57:36 +00:00
Max Filippov 67882fd177 target-xtensa: implement narrow instructions
Instructions with op0 >= 8 are 2 bytes long, others are 3 bytes long.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10 16:57:36 +00:00
Max Filippov dedc5eae23 target-xtensa: implement disas_xtensa_insn
Set up disas_xtensa_insn switch structure, mark required options on high
level groups. Implement arithmetic/bit logic/jump/call0.

Implement code generation loop with single step/breakpoint checking.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10 16:57:36 +00:00
Max Filippov 2328826b1d target-xtensa: add target stubs
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10 16:57:36 +00:00