a5f7f32a8f
target: e2k: Move %br parts to %br.
2022-06-10 11:48:11 +03:00
54feb6fbe3
target: e2k: Fix bugs.
2022-06-10 11:48:11 +03:00
24b5d5c7fb
target: e2k: Add loop_end/not_loop_end condition.
2022-06-10 11:48:11 +03:00
37acf287ad
target: e2k: Impl rotated pregs.
2022-06-10 11:48:11 +03:00
2f482cf83c
target: e2k: Remove type from macro GEN_MASK.
2022-06-10 11:48:11 +03:00
3d15ee8026
target: e2k: Add store instrs.
2022-06-10 11:48:11 +03:00
1edcdfc743
target: e2k: Add load instrs.
2022-06-10 11:48:11 +03:00
7c4f2f0a3c
target: e2k: Add getsp instr.
2022-06-10 11:48:11 +03:00
5c48cf014b
target: e2k: Add read/write to %usd.
2022-06-10 11:48:11 +03:00
ee42d330b5
target: e2k: Add merges and merged instrs.
2022-06-10 11:48:11 +03:00
11c6a483fb
target: e2k: Add sxt instr.
2022-06-10 11:48:11 +03:00
15508fb418
target: e2k: Fix crash on conditional syscall.
2022-06-10 11:48:11 +03:00
725d1d5acf
target: e2k: Add basic syscall support.
2022-06-10 11:48:11 +03:00
11c80f0227
target: e2k: Try to impl syscall.
2022-06-10 11:48:11 +03:00
c3dc2f9a68
target: e2k: Add e2k_gen get and set field.
2022-06-10 11:48:11 +03:00
99acf5b5fa
target: e2k: Add disp and ct instrs support.
2022-06-10 11:48:11 +03:00
a3bb35cc9d
target: e2k: Add negated predicate ct condition.
2022-06-10 11:48:11 +03:00
901f3bf981
target: e2k: Reorg control flow.
2022-06-10 11:48:11 +03:00
6f1319b758
target: e2k: Reorg.
2022-06-10 11:48:11 +03:00
01286c3c55
target: e2k: Comment unused vars for future use.
2022-06-10 11:48:11 +03:00
1d5f74624f
target: e2k: Move TCG CPU State to translate.h.
2022-06-10 11:48:11 +03:00
baa5780663
target: e2k: Add cpu state is_jmp.
2022-06-10 11:48:11 +03:00
3cc618ce20
target: e2k: Use win_ptr for regs.
2022-06-10 11:48:11 +03:00
d5f6e9a967
target: e2k: Add window ptr.
2022-06-10 11:48:11 +03:00
4cc727ed58
target: e2k: Commit bundle instrs at the end.
2022-06-10 11:48:11 +03:00
5d463a5827
target: e2k: Simple condition jump.
2022-06-10 11:48:10 +03:00
b8a79c9c2b
target: e2k: fix instructions with speculative mode
2022-06-10 11:48:10 +03:00
bc18b23fda
target: e2k: implement disas_log, doesn't work at all
2022-06-10 11:48:10 +03:00
38497f952b
target: e2k: Basic instruction execution.
2022-06-10 11:48:10 +03:00
ed6b1618db
elf: fix wrong Elbrus elf machine id
2022-06-10 11:48:10 +03:00
ff5127d36a
target: e2k: unpack long instructions.
2022-06-10 11:48:10 +03:00
c42af9ff35
disas: import disassmebler from binutils
2022-06-10 11:48:10 +03:00
8c78e941dd
target: e2k: add cpu definitions
2022-06-10 11:48:10 +03:00
d52c541b62
linux-user: add loading ELFs for e2kg
2022-06-10 11:48:10 +03:00
142e846587
softmmu: add e2k definition
2022-06-10 11:48:10 +03:00
1132f3d8bf
configs: add e2k-linux-user config
2022-06-10 11:48:10 +03:00
28687fb19f
include/elf.h: add MCST Elbrus definitions
2022-06-10 11:48:10 +03:00
Richard Henderson
9cc1bf1ebc
Xen patches
...
- PIIX3-IDE Xen cleanup
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Merge tag 'pull-xen-20220609' of https://xenbits.xen.org/git-http/people/aperard/qemu-dm into staging
Xen patches
- PIIX3-IDE Xen cleanup
# -----BEGIN PGP SIGNATURE-----
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# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 09 Jun 2022 06:56:31 AM PDT
# gpg: using RSA key F80C006308E22CFD8A92E7980CF5572FD7FB55AF
# gpg: Good signature from "Anthony PERARD <anthony.perard@gmail.com>" [unknown]
# gpg: aka "Anthony PERARD <anthony.perard@citrix.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 5379 2F71 024C 600F 778A 7161 D8D5 7199 DF83 42C8
# Subkey fingerprint: F80C 0063 08E2 2CFD 8A92 E798 0CF5 572F D7FB 55AF
* tag 'pull-xen-20220609' of https://xenbits.xen.org/git-http/people/aperard/qemu-dm :
include/hw/ide: Unexport pci_piix3_xen_ide_unplug()
hw/ide/piix: Add some documentation to pci_piix3_xen_ide_unplug()
hw/ide/piix: Remove redundant "piix3-ide-xen" device class
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-09 08:25:17 -07:00
Bernhard Beschow
6a8a8b62bd
include/hw/ide: Unexport pci_piix3_xen_ide_unplug()
...
This function was declared in a generic and public header, implemented
in a device-specific source file but only used in xen_platform. Given its
'aux' parameter, this function is more xen-specific than piix-specific.
Also, the hardcoded magic constants seem to be generic and related to
PCIIDEState and IDEBus rather than piix.
Therefore, move this function to xen_platform, unexport it, and drop the
"piix3" in the function name as well.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Paul Durrant <paul@xen.org>
Acked-by: Anthony PERARD <anthony.perard@citrix.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220513180957.90514-4-shentey@gmail.com>
Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
2022-06-09 14:47:42 +01:00
Bernhard Beschow
3690241746
hw/ide/piix: Add some documentation to pci_piix3_xen_ide_unplug()
...
The comment is based on commit message
ae4d2eb273
'xen-platform: add missing disk
unplug option'. Since it seems to describe design decisions and
limitations that still apply it seems worth having.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Anthony PERARD <anthony.perard@citrix.com>
Message-Id: <20220513180957.90514-3-shentey@gmail.com>
Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
2022-06-09 14:47:42 +01:00
Bernhard Beschow
7851b21a81
hw/ide/piix: Remove redundant "piix3-ide-xen" device class
...
Commit 0f8445820f
'xen: piix reuse pci
generic class init function' already resolved redundant code which in
turn rendered piix3-ide-xen redundant.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Anthony PERARD <anthony.perard@citrix.com>
Message-Id: <20220513180957.90514-2-shentey@gmail.com>
Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
2022-06-09 14:47:42 +01:00
Richard Henderson
028f2361d0
target-arm queue:
...
* target/arm: Declare support for FEAT_RASv1p1
* target/arm: Implement FEAT_DoubleFault
* Fix 'writeable' typos
* xlnx_dp: Implement vblank interrupt
* target/arm: Move page-table-walk code to ptw.c
* target/arm: Preparatory patches for SME support
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=a85M
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Merge tag 'pull-target-arm-20220609' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* target/arm: Declare support for FEAT_RASv1p1
* target/arm: Implement FEAT_DoubleFault
* Fix 'writeable' typos
* xlnx_dp: Implement vblank interrupt
* target/arm: Move page-table-walk code to ptw.c
* target/arm: Preparatory patches for SME support
# -----BEGIN PGP SIGNATURE-----
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# InzNe4cc9Be4TtyamRA1mA==
# =a85M
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 09 Jun 2022 02:04:13 AM PDT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
* tag 'pull-target-arm-20220609' of https://git.linaro.org/people/pmaydell/qemu-arm : (55 commits)
target/arm: Add ID_AA64SMFR0_EL1
target/arm: Add isar_feature_aa64_sme
target/arm: Export bfdotadd from vec_helper.c
target/arm: Move expand_pred_h to vec_internal.h
target/arm: Use expand_pred_b in mve_helper.c
target/arm: Move expand_pred_b to vec_internal.h
target/arm: Export sve contiguous ldst support functions
target/arm: Split out load/store primitives to sve_ldst_internal.h
target/arm: Rename sve_zcr_len_for_el to sve_vqm1_for_el
target/arm: Use uint32_t instead of bitmap for sve vq's
target/arm: Merge aarch64_sve_zcr_get_valid_len into caller
target/arm: Do not use aarch64_sve_zcr_get_valid_len in reset
target/arm: Hoist arm_is_el2_enabled check in sve_exception_el
target/arm: Use el_is_in_host for sve_exception_el
target/arm: Use el_is_in_host for sve_zcr_len_for_el
target/arm: Add el_is_in_host
target/arm: Remove fp checks from sve_exception_el
target/arm: Remove route_to_el2 check from sve_exception_el
linux-user/aarch64: Introduce sve_vq
target/arm: Rename TBFLAG_A64 ZCR_LEN to VL
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-09 06:47:03 -07:00
Richard Henderson
05911658cb
VFIO updates 2022-06-08
...
* Fix spurious alignment warnings for TPM on unmap too (Eric Auger)
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Merge tag 'vfio-updates-20220608.0' of https://gitlab.com/alex.williamson/qemu into staging
VFIO updates 2022-06-08
* Fix spurious alignment warnings for TPM on unmap too (Eric Auger)
# -----BEGIN PGP SIGNATURE-----
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# =VIGl
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 08 Jun 2022 07:45:08 AM PDT
# gpg: using RSA key 42F6C04E540BD1A99E7B8A90239B9B6E3BB08B22
# gpg: issuer "alex.williamson@redhat.com"
# gpg: Good signature from "Alex Williamson <alex.williamson@redhat.com>" [undefined]
# gpg: aka "Alex Williamson <alex@shazbot.org>" [undefined]
# gpg: aka "Alex Williamson <alwillia@redhat.com>" [undefined]
# gpg: aka "Alex Williamson <alex.l.williamson@gmail.com>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 42F6 C04E 540B D1A9 9E7B 8A90 239B 9B6E 3BB0 8B22
* tag 'vfio-updates-20220608.0' of https://gitlab.com/alex.williamson/qemu :
vfio/common: remove spurious warning on vfio_listener_region_del
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-08 13:38:54 -07:00
Richard Henderson
414c54d515
target/arm: Add ID_AA64SMFR0_EL1
...
This register is allocated from the existing block of id registers,
so it is already RES0 for cpus that do not implement SME.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220607203306.657998-21-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08 19:38:59 +01:00
Richard Henderson
f305bf9436
target/arm: Add isar_feature_aa64_sme
...
This will be used for implementing FEAT_SME.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220607203306.657998-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08 19:38:59 +01:00
Richard Henderson
72db2aa353
target/arm: Export bfdotadd from vec_helper.c
...
We will need this over in sme_helper.c.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220607203306.657998-19-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08 19:38:58 +01:00
Richard Henderson
a613cf2d4a
target/arm: Move expand_pred_h to vec_internal.h
...
Move the data to vec_helper.c and the inline to vec_internal.h.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220607203306.657998-18-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08 19:38:58 +01:00
Richard Henderson
05dd14bdfa
target/arm: Use expand_pred_b in mve_helper.c
...
Use the function instead of the array directly.
Because the function performs its own masking, via the uint8_t
parameter, we need to do nothing extra within the users: the bits
above the first 2 (_uh) or 4 (_uw) will be discarded by assignment
to the local bmask variables, and of course _uq uses the entire
uint64_t result.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220607203306.657998-17-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08 19:38:58 +01:00
Richard Henderson
820e0bb9ce
target/arm: Move expand_pred_b to vec_internal.h
...
Put the inline function near the array declaration.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220607203306.657998-16-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08 19:38:58 +01:00
Richard Henderson
0b68112b39
target/arm: Export sve contiguous ldst support functions
...
Export all of the support functions for performing bulk
fault analysis on a set of elements at contiguous addresses
controlled by a predicate.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220607203306.657998-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08 19:38:58 +01:00