Commit Graph

534 Commits

Author SHA1 Message Date
blueswir1
2adab7d6b5 Implement HIOR
A real 970 CPU starts up with HIOR=0xfff00000 and triggers a reset
exception, basically ending up at IP 0xfff001000.

Later on this HIOR has to be set to 0 by the firmware in order to
enable the OS to handle interrupts on its own.

This patch maps HIOR to exec_prefix, which does the same thing
internally in qemu already.

It replaces the previous patch that changed the 970 initialization
constants, as this is the clean solution to the same problem.

Signed-off-by: Alexander Graf <alex@csgraf.de>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6656 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-28 18:39:42 +00:00
blueswir1
a457e7ee3d Fix typo in gen_qemu_ld32s
When the CPU is in little endian mode, it should load values from RAM
in byte swapped manner. This check is in all the ld and st functions,
but misspelled in gen_qemu_ld32s.

This patch fixes the misspelling and makes ppc64 Linux happier.

Signed-off-by: Alexander Graf <alex@csgraf.de>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6654 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-28 08:25:29 +00:00
blueswir1
07c485ce78 Turn MMU off on reset
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6637 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-21 17:29:14 +00:00
blueswir1
5518f3a636 Fix branch debugging
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6629 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-19 20:17:09 +00:00
aurel32
bd5ea51398 target-ppc: Model e500v{1,2} CPUs more accurately
The e500v1 chips only have single-precision floating point; don't say we
support the double-precision floating-point instructions on such chips.
Also add an e500v1 -cpu argument for a generic e500v1.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6576 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-09 16:50:00 +00:00
aurel32
40569b7edc target-ppc: Model SPE floating-point instructions more accurately
Single-precision and double-precision floating-point instructions should
be separated into their own categories, since some chips only support
single-precision instructions.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6575 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-09 16:49:50 +00:00
aurel32
071fc3b1cd target-ppc: Add vrsqrtefp instruction
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6574 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-09 16:49:40 +00:00
aurel32
bdfbac3512 target-ppc: Add vrefp instruction
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6573 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-09 16:49:29 +00:00
aurel32
875b31db7f target-ppc: Add vct{u,s}xs instructions
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6572 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-09 16:49:20 +00:00
aurel32
819ca12127 target-ppc: Add vcmp{eq, ge, gt, b}fp{, .} instructions
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6571 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-09 16:49:10 +00:00
aurel32
35cf7c7e18 target-ppc: Add vmaddfp and vnmsubfp instructions
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6570 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-09 16:48:59 +00:00
aurel32
56fdd213ef target-ppc: Add v{add,sub}fp instructions
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6569 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-09 16:48:51 +00:00
aurel32
1536ff641f target-ppc: Add v{max,min}fp instructions
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6568 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-09 16:48:39 +00:00
blueswir1
3a616592a1 Load 32 bit ELF BIOS images also on PPC64
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6554 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-08 12:50:56 +00:00
aurel32
b580763f86 target-ppc: change instruction name vrlogefp into vlogefp
Thanks to Nathan Froyd for noticing that.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6532 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-05 22:33:36 +00:00
aliguori
0d0266a53b targets: remove error handling from qemu_malloc() callers (Avi Kivity)
Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6530 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-05 22:06:11 +00:00
aurel32
f586ce09e2 target-ppc: add vrlogefp instruction
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6519 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-05 13:42:57 +00:00
aurel32
06f7332ab9 target-ppc: fix previous commit
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6516 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-04 14:08:08 +00:00
aurel32
c609b12e1f target-ppc: use the new float constants
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6515 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-04 13:52:39 +00:00
aurel32
e140632e87 Add vcf{u,s}x instructions
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6513 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-04 13:52:17 +00:00
aurel32
f6b1964548 Add vrfi{m,n,p,z} instructions
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6512 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-04 13:52:03 +00:00
aurel32
34ba2857a0 Add various NaN-handling macros
These simplify the implementation of the floating-point Altivec
instructions and reduce clutter.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6511 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-04 09:05:53 +00:00
aurel32
6e87b7c7bf Make mtvscr use a helper
Do this so we can set float statuses once per mtvscr, rather than once
per Altivec instruction.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6508 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-03 19:56:09 +00:00
aurel32
cf8358c8f7 Add calls to initialize VSCR on appropriate machines
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6507 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-03 19:55:59 +00:00
aurel32
fbd265b681 Rename spe_status to vec_status
Only one of Altivec and SPE will be available on a given chip.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6506 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-03 19:55:51 +00:00
aurel32
0f6fbcbccd Add f field to ppc_avr_t
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6505 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-03 19:55:43 +00:00
aurel32
fce5ecb780 Fix compilation of PPC64 targets with DEBUG_TCGV enabled
The attached patch fixes compilation of PPC64 targets with DEBUG_TCGV
enabled.

Signed-off-by: Stuart Brady <stuart.brady@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6502 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-03 19:55:13 +00:00
aliguori
eca1bdf415 Log reset events (Jan Kiszka)
Original idea&code by Kevin Wolf, split-up in two patches and added more
archs.

This patch introduces a flag to log CPU resets. Useful for tracing
unexpected resets (such as those triggered by x86 triple faults).

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6452 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-26 19:54:31 +00:00
aurel32
ea23bc2022 kvm/powerpc: extern one function for MPC85xx code use
Signed-off-by: Liu Yu <yu.liu@freescale.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6427 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-24 16:35:56 +00:00
aurel32
688890f75e target-ppc: Add SPE register read/write using XML
Don't read/write SPEFSCR until we figure out what to do about exceptions.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6425 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-24 15:08:17 +00:00
aurel32
b4f8d821e5 target-ppc: Add Altivec register read/write using XML
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6424 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-24 15:08:09 +00:00
aurel32
2495152227 target-ppc: Add float register read/write using XML
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6423 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-24 15:08:00 +00:00
aurel32
4e47ea6702 target-ppc: Include gdbstub.h
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6422 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-24 15:07:50 +00:00
aliguori
8fec2b8c45 global s/loglevel & X/qemu_loglevel_mask(X)/ (Eduardo Habkost)
These are references to 'loglevel' that aren't on a simple 'if (loglevel &
X) qemu_log()' statement.

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6340 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-15 22:36:53 +00:00
aliguori
93fcfe39a0 Convert references to logfile/loglevel to use qemu_log*() macros
This is a large patch that changes all occurrences of logfile/loglevel
global variables to use the new qemu_log*() macros.

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6338 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-15 22:34:14 +00:00
aliguori
d12d51d5ba Clean up debugging code #ifdefs (Eduardo Habkost)
Use macros to avoid #ifdefs on debugging code.

This patch doesn't try to merge logging macros from different files,
but just unify the debugging code #ifdefs onto a macro on each file. A
further cleanup can unify the debugging macros on a common header, later

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6332 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-15 21:48:06 +00:00
aliguori
da07cf59b0 powerpc/kvm: enable POWERPC_MMU_BOOKE_FSL when kvm is enabled (Liu Yu)
Signed-off-by: Liu Yu <yu.liu@freescale.com>
Acked-by: Hollis Blanchard <hollisb@us.ibm.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6329 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-15 21:24:24 +00:00
aliguori
57be80f948 powerpc/kvm: Fix a uninitialized bug (Liu Yu)
Signed-off-by: Liu Yu <yu.liu@freescale.com>
Acked-by: Hollis Blanchard <hollisb@us.ibm.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6327 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-15 21:18:42 +00:00
aurel32
1b6e5f9906 target-ppc: fix wrteei instruction
Patch by Andrew May

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6308 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-14 19:40:54 +00:00
aurel32
ae1c1a3d68 target-ppc: add altivec cache instructions
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6275 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-12 21:33:02 +00:00
aurel32
5ab09f3349 Add v{add, sub}{s, u}{b, h, w}s instructions
Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6254 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-08 23:19:50 +00:00
aurel32
c026766b15 Add vspltis{b,h,w} instructions
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6238 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-08 18:54:57 +00:00
aurel32
d9430add63 Add vs{l,r} instructions
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6237 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-08 18:54:48 +00:00
aurel32
1add6e234a Add vcmpequ{b, h, w} and vcmpgt{s, u}{b, h, w} instructions
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6236 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-08 18:54:38 +00:00
aurel32
0cbcd90636 Add GEN_VXRFORM{,1} macros for subsequent instructions
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6235 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-08 18:54:26 +00:00
aurel32
b392e756c1 target-ppc: fix compilation on BigEndian
This fixes BigEndian compilation for target-ppc.

(Michael Buesch)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6193 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-05 21:40:27 +00:00
aurel32
785f451b62 target-ppc: Add m{f,t}vscr instructions.
Based on a patch by Nathan Froyd <froydnj@codesourcery.com>

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6190 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04 22:51:59 +00:00
aurel32
8142cddda2 Add vsumsws, vsum2sws, and vsum4{sbs, shs,ubs} instructions.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6189 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04 22:13:21 +00:00
aurel32
cbfb6ae9b3 Add {l,st}ve{b,h,w}x instructions.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6188 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04 22:13:10 +00:00
aurel32
bcd2ee23ea Add vmladduhm instruction.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6187 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04 22:13:00 +00:00