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Author SHA1 Message Date
AlexChen eed31bc5e2 contrib/rdmacm-mux: Fix error condition in hash_tbl_search_fd_by_ifid() 
When fd is not found according to ifid, the _hash_tbl_search_fd_by_ifid()
returns 0 and assigns the result to *fd, so We have to check that *fd is 0,
not that fd is 0.

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: AlexChen <alex.chen@huawei.com>
Message-Id: <5F9AC6FF.4000301@huawei.com>
Reviewed-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Signed-off-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
 2020-12-18 20:15:42 +02:00
Peter Maydell a05f8ecd88 A collection of RISC-V improvements: 
- Improve the sifive_u DTB generation
  - Add QSPI NOR flash to Microchip PFSoC
  - Fix a bug in the Hypervisor HLVX/HLV/HSV instructions
  - Fix some mstatus mask defines
  - Ibex PLIC improvements
  - OpenTitan memory layout update
  - Initial steps towards support for 32-bit CPUs on 64-bit builds
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Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20201217-1' into staging

A collection of RISC-V improvements:
 - Improve the sifive_u DTB generation
 - Add QSPI NOR flash to Microchip PFSoC
 - Fix a bug in the Hypervisor HLVX/HLV/HSV instructions
 - Fix some mstatus mask defines
 - Ibex PLIC improvements
 - OpenTitan memory layout update
 - Initial steps towards support for 32-bit CPUs on 64-bit builds

# gpg: Signature made Fri 18 Dec 2020 05:59:42 GMT
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20201217-1: (23 commits)
  riscv/opentitan: Update the OpenTitan memory layout
  hw/riscv: Use the CPU to determine if 32-bit
  target/riscv: cpu: Set XLEN independently from target
  target/riscv: csr: Remove compile time XLEN checks
  target/riscv: cpu_helper: Remove compile time XLEN checks
  target/riscv: cpu: Remove compile time XLEN checks
  target/riscv: Specify the XLEN for CPUs
  target/riscv: Add a riscv_cpu_is_32bit() helper function
  target/riscv: fpu_helper: Match function defs in HELPER macros
  hw/riscv: sifive_u: Remove compile time XLEN checks
  hw/riscv: spike: Remove compile time XLEN checks
  hw/riscv: virt: Remove compile time XLEN checks
  hw/riscv: boot: Remove compile time XLEN checks
  riscv: virt: Remove target macro conditionals
  riscv: spike: Remove target macro conditionals
  target/riscv: Add a TYPE_RISCV_CPU_BASE CPU
  hw/riscv: Expand the is 32-bit check to support more CPUs
  intc/ibex_plic: Clear interrupts that occur during claim process
  target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR
  target/riscv: Fix the bug of HLVX/HLV/HSV
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2020-12-18 11:12:35 +00:00
Alistair Francis d31e970a01 riscv/opentitan: Update the OpenTitan memory layout 
OpenTitan is currently only avalible on an FPGA platform and the memory
addresses have changed. Update to use the new memory addresses.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 8eb65314830a75d0fea3fccf77bc45b8ddd01c42.1607982831.git.alistair.francis@wdc.com
 2020-12-17 21:56:44 -08:00
Alistair Francis 3ed2b8ac2d hw/riscv: Use the CPU to determine if 32-bit 
Instead of using string compares to determine if a RISC-V machine is
using 32-bit or 64-bit CPUs we can use the initalised CPUs. This avoids
us having to maintain a list of CPU names to compare against.

This commit also fixes the name of the function to match the
riscv_cpu_is_32bit() function.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 8ab7614e5df93ab5267788b73dcd75f9f5615e82.1608142916.git.alistair.francis@wdc.com
 2020-12-17 21:56:44 -08:00
Alistair Francis 094b072c68 target/riscv: cpu: Set XLEN independently from target 
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-id: 7eddba45b5d223321c031431849fdd42eceb514b.1608142916.git.alistair.francis@wdc.com
 2020-12-17 21:56:44 -08:00
Alistair Francis 8987cdc481 target/riscv: csr: Remove compile time XLEN checks 
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-id: 7371180970b7db310d3a1da21d03d33499c2beb0.1608142916.git.alistair.francis@wdc.com
 2020-12-17 21:56:44 -08:00
Alistair Francis f08c7ff3dc target/riscv: cpu_helper: Remove compile time XLEN checks 
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-id: 872d2dfcd1c7c3914655d677e911b9432eb8f340.1608142916.git.alistair.francis@wdc.com
 2020-12-17 21:56:44 -08:00
Alistair Francis 5c5a47f10c target/riscv: cpu: Remove compile time XLEN checks 
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-id: a426ead44db5065a0790066d43e91245683509d7.1608142916.git.alistair.francis@wdc.com
 2020-12-17 21:56:44 -08:00
Alistair Francis 114baaca51 target/riscv: Specify the XLEN for CPUs 
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-id: c1da66affbb83ec4a2fbeb0194293bd24d65f5dc.1608142916.git.alistair.francis@wdc.com
 2020-12-17 21:56:44 -08:00
Alistair Francis 51ae0cabc6 target/riscv: Add a riscv_cpu_is_32bit() helper function 
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-id: ebd37b237a8cbe457335b948bd57f487b6b31869.1608142916.git.alistair.francis@wdc.com
 2020-12-17 21:56:44 -08:00
Alistair Francis 5b6c291b8d target/riscv: fpu_helper: Match function defs in HELPER macros 
Update the function definitions generated in helper.h to match the
actual function implementations.

Also remove all compile time XLEN checks when building.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 614c369cb0000d070873a647b8aac7e023cba145.1608142916.git.alistair.francis@wdc.com
 2020-12-17 21:56:44 -08:00
Alistair Francis 2206ffa68f hw/riscv: sifive_u: Remove compile time XLEN checks 
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-id: 40d6df4dd05302c566e419be3a1fef7799e57c2e.1608142916.git.alistair.francis@wdc.com
 2020-12-17 21:56:44 -08:00
Alistair Francis bd62c13ea8 hw/riscv: spike: Remove compile time XLEN checks 
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-id: ac75037dd58061486de421a0fcd9ac8a92014607.1608142916.git.alistair.francis@wdc.com
 2020-12-17 21:56:44 -08:00
Alistair Francis 9d01143063 hw/riscv: virt: Remove compile time XLEN checks 
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-id: d7ca1aca672515e6a4aa0d41716238b055f3f25c.1608142916.git.alistair.francis@wdc.com
 2020-12-17 21:56:44 -08:00
Alistair Francis 7893677184 hw/riscv: boot: Remove compile time XLEN checks 
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-id: 51e9842dbed1acceebad7f97bd3aae69aa1ac19e.1608142916.git.alistair.francis@wdc.com
 2020-12-17 21:56:44 -08:00
Alistair Francis 09fe17125e riscv: virt: Remove target macro conditionals 
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-id: aed1174c2efd2f050fa5bd8f524d68795b12c0e4.1608142916.git.alistair.francis@wdc.com
 2020-12-17 21:56:44 -08:00
Alistair Francis dc4d4aaee3 riscv: spike: Remove target macro conditionals 
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-id: 04ac7fba2348c92f296a5e6a9959ac72b77ae4c6.1608142916.git.alistair.francis@wdc.com
 2020-12-17 21:56:44 -08:00
Alistair Francis c0a635f397 target/riscv: Add a TYPE_RISCV_CPU_BASE CPU 
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-id: 86e5ccd9eae2f5d8c2257679c6ccf6078a5d51af.1608142916.git.alistair.francis@wdc.com
 2020-12-17 21:56:44 -08:00
Alistair Francis 617448a46b hw/riscv: Expand the is 32-bit check to support more CPUs 
Currently the riscv_is_32_bit() function only supports the generic rv32
CPUs. Extend the function to support the SiFive and LowRISC CPUs as
well.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-id: 9a13764115ba78688ba61b56526c6de65fc3ef42.1608142916.git.alistair.francis@wdc.com
 2020-12-17 21:56:43 -08:00
Alistair Francis 54a581c228 intc/ibex_plic: Clear interrupts that occur during claim process 
Previously if an interrupt occured during the claim process (after the
interrupt is claimed but before it's completed) it would never be
cleared.
This patch ensures that we also clear the hidden_pending bits as well.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Jackie Ke <jackieke724@hotmail.com>
Message-id: 4e9786084a86f220689123cc8a7837af8fa071cf.1607100423.git.alistair.francis@wdc.com
 2020-12-17 21:56:43 -08:00
Alex Richardson 529577457c target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR 
The TW and TSR fields should be bits 21 and 22 and not 30/29.
This was found while comparing QEMU behaviour against the sail formal
model (https://github.com/rems-project/sail-riscv/).

Signed-off-by: Alex Richardson <Alexander.Richardson@cl.cam.ac.uk>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201130170117.71281-1-Alexander.Richardson@cl.cam.ac.uk
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 2020-12-17 21:56:43 -08:00
Yifei Jiang c63ca4ff7f target/riscv: Fix the bug of HLVX/HLV/HSV 
We found that the hypervisor virtual-machine load and store instructions,
included HLVX/HLV/HSV, couldn't access guest userspace memory.

In the riscv-privileged spec, HLVX/HLV/HSV is defined as follow:
"As usual when V=1, two-stage address translation is applied, and
the HS-level sstatus.SUM is ignored."

But get_physical_address() doesn't ignore sstatus.SUM, when HLVX/HLV/HSV
accesses guest userspace memory. So this patch fixes it.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201130012810.899-1-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 2020-12-17 21:56:43 -08:00
Xinhao Zhang b3d2a4296f hw/core/register.c: Don't use '#' flag of printf format 
Fix code style. Don't use '#' flag of printf format ('%#') in
format strings, use '0x' prefix instead

Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
Signed-off-by: Kai Deng <dengkai1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201116140148.2850128-1-zhangxinhao1@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 2020-12-17 21:56:43 -08:00
Vitaly Wool dfc973ecc1 hw/riscv: microchip_pfsoc: add QSPI NOR flash 
Add QSPI NOR flash definition for Microchip PolarFire SoC.

Signed-off-by: Vitaly Wool <vitaly.wool@konsulko.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Message-id: 20201112074950.33283-1-vitaly.wool@konsulko.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 2020-12-17 21:56:43 -08:00
Anup Patel 10b43754cf hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 
The sifive_u machine emulates two UARTs but we have only UART0 DT
node in the generated DTB so this patch adds UART1 DT node in the
generated DTB.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201111094725.3768755-1-anup.patel@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 2020-12-17 21:56:43 -08:00
Peter Maydell 75ee62ac60 x86 queue, 2020-12-17 
Features:
 * AVX512_FP16 feature (Cathy Zhang)
 
 Cleanups:
 * accel code cleanup (Claudio Fontana)
 * hyperv initialization cleanup (Vitaly Kuznetsov)
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Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging

x86 queue, 2020-12-17

Features:
* AVX512_FP16 feature (Cathy Zhang)

Cleanups:
* accel code cleanup (Claudio Fontana)
* hyperv initialization cleanup (Vitaly Kuznetsov)

# gpg: Signature made Thu 17 Dec 2020 18:44:45 GMT
# gpg:                using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6
# gpg:                issuer "ehabkost@redhat.com"
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full]
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF  D1AA 2807 936F 984D C5A6

* remotes/ehabkost-gl/tags/x86-next-pull-request:
  cpu: Remove unnecessary noop methods
  tcg: Make CPUClass.debug_excp_handler optional
  tcg: make CPUClass.cpu_exec_* optional
  tcg: cpu_exec_{enter,exit} helpers
  i386: tcg: remove inline from cpu_load_eflags
  i386: move TCG cpu class initialization to tcg/
  x86/cpu: Add AVX512_FP16 cpu feature
  i386: move hyperv_limits initialization to x86_cpu_realizefn()
  i386: move hyperv_version_id initialization to x86_cpu_realizefn()
  i386: move hyperv_interface_id initialization to x86_cpu_realizefn()
  i386: move hyperv_vendor_id initialization to x86_cpu_realizefn()
  i386: move cpu dump out of helper.c into cpu-dump.c
  i386: move TCG accel files into tcg/
  i386: hvf: remove stale MAINTAINERS entry for old hvf stubs
  i386: move hax accel files into hax/
  i386: move whpx accel files into whpx/
  i386: move kvm accel files into kvm/

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2020-12-17 18:53:36 +00:00
Eduardo Habkost 9fb75013d8 cpu: Remove unnecessary noop methods 
In the previous commits we made cpu_exec_* and debug_excp_handler
optional, so we can now remove these no-op handlers.

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20201212155530.23098-13-cfontana@suse.de>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
 2020-12-16 15:50:33 -05:00
Eduardo Habkost 710384d042 tcg: Make CPUClass.debug_excp_handler optional 
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20201212155530.23098-12-cfontana@suse.de>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
 2020-12-16 15:50:33 -05:00
Eduardo Habkost 80c4750ba8 tcg: make CPUClass.cpu_exec_* optional 
This will let us simplify the code that initializes CPU class
methods, when we move cpu_exec_*() to a separate struct.

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20201212155530.23098-11-cfontana@suse.de>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
 2020-12-16 15:50:33 -05:00
Eduardo Habkost 035ba06c2e tcg: cpu_exec_{enter,exit} helpers 
Move invocation of CPUClass.cpu_exec_*() to separate helpers,
to make it easier to refactor that code later.

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201212155530.23098-10-cfontana@suse.de>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
 2020-12-16 15:50:33 -05:00
Claudio Fontana 69483f3115 i386: tcg: remove inline from cpu_load_eflags 
make it a regular function.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201212155530.23098-9-cfontana@suse.de>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
 2020-12-16 15:50:33 -05:00
Claudio Fontana ed69e8314d i386: move TCG cpu class initialization to tcg/ 
to do this, we need to take code out of cpu.c and helper.c,
and also move some prototypes from cpu.h, for code that is
needed in tcg/xxx_helper.c, and which in turn is part of the
callbacks registered by the class initialization.

Therefore, do some shuffling of the parts of cpu.h that
are only relevant for tcg/, and put them in tcg/helper-tcg.h

For FT0 and similar macros, put them in tcg/fpu-helper.c
since they are used only there.

Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201212155530.23098-8-cfontana@suse.de>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
 2020-12-16 15:50:33 -05:00
Cathy Zhang 40399ecb69 x86/cpu: Add AVX512_FP16 cpu feature 
AVX512 Half-precision floating point (FP16) has better performance
compared to FP32 if the presicion or magnitude requirements are met.
It's defined as CPUID.(EAX=7,ECX=0):EDX[bit 23].

Refer to
https://software.intel.com/content/www/us/en/develop/download/\
intel-architecture-instruction-set-extensions-programming-reference.html

Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
Message-Id: <20201216224002.32677-1-cathy.zhang@intel.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
 2020-12-16 15:50:33 -05:00
Vitaly Kuznetsov 23eb5d032f i386: move hyperv_limits initialization to x86_cpu_realizefn() 
As a preparation to expanding Hyper-V CPU features early, move
hyperv_limits initialization to x86_cpu_realizefn().

Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Message-Id: <20201119103221.1665171-5-vkuznets@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
 2020-12-16 14:07:33 -05:00
Vitaly Kuznetsov fb7e31aa4f i386: move hyperv_version_id initialization to x86_cpu_realizefn() 
As a preparation to expanding Hyper-V CPU features early, move
hyperv_version_id initialization to x86_cpu_realizefn().

Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Message-Id: <20201119103221.1665171-4-vkuznets@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
 2020-12-16 14:07:33 -05:00
Vitaly Kuznetsov 735db465b0 i386: move hyperv_interface_id initialization to x86_cpu_realizefn() 
As a preparation to expanding Hyper-V CPU features early, move
hyperv_interface_id initialization to x86_cpu_realizefn().

Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Message-Id: <20201119103221.1665171-3-vkuznets@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
 2020-12-16 14:07:33 -05:00
Vitaly Kuznetsov 088567713f i386: move hyperv_vendor_id initialization to x86_cpu_realizefn() 
As a preparation to expanding Hyper-V CPU features early, move
hyperv_vendor_id initialization to x86_cpu_realizefn(). Introduce
x86_cpu_hyperv_realize() to not not pollute x86_cpu_realizefn()
itself.

Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Message-Id: <20201119103221.1665171-2-vkuznets@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
 2020-12-16 14:07:33 -05:00
Claudio Fontana 0c36af8ce8 i386: move cpu dump out of helper.c into cpu-dump.c 
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201212155530.23098-7-cfontana@suse.de>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
 2020-12-16 14:06:53 -05:00
Claudio Fontana 1b248f147e i386: move TCG accel files into tcg/ 
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

[claudio: moved cc_helper_template.h to tcg/ too]

Signed-off-by: Claudio Fontana <cfontana@suse.de>
Message-Id: <20201212155530.23098-6-cfontana@suse.de>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
 2020-12-16 14:06:53 -05:00
Claudio Fontana dbe59a1991 i386: hvf: remove stale MAINTAINERS entry for old hvf stubs 
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20201212155530.23098-5-cfontana@suse.de>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
 2020-12-16 14:06:53 -05:00
Claudio Fontana 7fdef0d4f2 i386: move hax accel files into hax/ 
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201212155530.23098-4-cfontana@suse.de>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
 2020-12-16 14:06:53 -05:00
Claudio Fontana 1fc33bb9f0 i386: move whpx accel files into whpx/ 
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201212155530.23098-3-cfontana@suse.de>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
 2020-12-16 14:06:53 -05:00
Claudio Fontana a9dc68d9b2 i386: move kvm accel files into kvm/ 
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201212155530.23098-2-cfontana@suse.de>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
 2020-12-16 14:06:52 -05:00
Peter Maydell af3f37319c * New -action option and set-action QMP command (Alejandro) 
* More vl.c cleanup (myself with help from Daniel and Igor)
 * Remove deprecated options (Philippe, Thomas)
 * Dirty bitmap fix (Zenghui)
 * icount caching speedup (Pavel)
 * SCSI race fix (Maxim)
 * Remove pre-GCC 4.8 code (Marc-André)
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Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging

* New -action option and set-action QMP command (Alejandro)
* More vl.c cleanup (myself with help from Daniel and Igor)
* Remove deprecated options (Philippe, Thomas)
* Dirty bitmap fix (Zenghui)
* icount caching speedup (Pavel)
* SCSI race fix (Maxim)
* Remove pre-GCC 4.8 code (Marc-André)

# gpg: Signature made Tue 15 Dec 2020 17:53:24 GMT
# gpg:                using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg:                issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg:                 aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4  E2F7 7E15 100C CD36 69B1
#      Subkey fingerprint: F133 3857 4B66 2389 866C  7682 BFFB D25F 78C7 AE83

* remotes/bonzini-gitlab/tags/for-upstream: (45 commits)
  build: -no-pie is no functional linker flag
  scripts/git.orderfile: Keep files with .inc extension sorted
  compiler.h: remove QEMU_GNUC_PREREQ
  linux-user: remove GNUC check
  compiler: remove GNUC check
  xen: remove GNUC check
  poison: remove GNUC check
  compiler.h: explicit case for Clang printf attribute
  virtiofsd: replace _Static_assert with QEMU_BUILD_BUG_ON
  tests: remove GCC < 4 fallbacks
  qemu-plugin.h: remove GCC < 4
  compiler.h: remove GCC < 3 __builtin_expect fallback
  accel/tcg: Remove special case for GCC < 4.6
  qemu/atomic: Drop special case for unsupported compiler
  hw/core: Restrict 'fw-path-provider.c' to system mode emulation
  docs: set CONFDIR when running sphinx
  vl: rename local variable in configure_accelerators
  qemu-option: pass QemuOptsList to opts_accepts_any
  qemu-option: simplify search for end of key
  kvm: Take into account the unaligned section size when preparing bitmap
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

# Conflicts:
#	softmmu/vl.c
 2020-12-15 21:24:31 +00:00
Christian Ehrhardt bbd2d5a812 build: -no-pie is no functional linker flag 
Recent binutils changes dropping unsupported options [1] caused a build
issue in regard to the optionroms.

  ld -m elf_i386 -T /<<PKGBUILDDIR>>/pc-bios/optionrom//flat.lds -no-pie \
    -s -o multiboot.img multiboot.o
  ld.bfd: Error: unable to disambiguate: -no-pie (did you mean --no-pie ?)

This isn't really a regression in ld.bfd, filing the bug upstream
revealed that this never worked as a ld flag [2] - in fact it seems we
were by accident setting --nmagic).

Since it never had the wanted effect this usage of LDFLAGS_NOPIE, should be
droppable without any effect. This also is the only use-case of LDFLAGS_NOPIE
in .mak, therefore we can also remove it from being added there.

[1]: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=983d925d
[2]: https://sourceware.org/bugzilla/show_bug.cgi?id=27050#c5

Signed-off-by: Christian Ehrhardt <christian.ehrhardt@canonical.com>
Message-Id: <20201214150938.1297512-1-christian.ehrhardt@canonical.com>
Cc: qemu-stable@nongnu.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
 2020-12-15 12:53:16 -05:00
Philippe Mathieu-Daudé a1bcbb485c scripts/git.orderfile: Keep files with .inc extension sorted 
Sort .inc files along with the extension including them.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201213205132.243628-1-f4bug@amsat.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
 2020-12-15 12:53:16 -05:00
Marc-André Lureau 07b35a23c3 compiler.h: remove QEMU_GNUC_PREREQ 
When needed, the G_GNUC_CHECK_VERSION() glib macro can be used instead.

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20201210134752.780923-14-marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
 2020-12-15 12:53:15 -05:00
Marc-André Lureau 36c5e0b8ef linux-user: remove GNUC check 
QEMU requires Clang or GCC, that define and support __GNUC__ extensions.

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20201210134752.780923-13-marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
 2020-12-15 12:53:14 -05:00
Marc-André Lureau 4e063f7b29 compiler: remove GNUC check 
QEMU requires Clang or GCC, that define and support __GNUC__ extensions.

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20201210134752.780923-12-marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
 2020-12-15 12:53:14 -05:00
Marc-André Lureau d55e5bd15a xen: remove GNUC check 
QEMU requires Clang or GCC, that define and support __GNUC__ extensions

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Acked-by: Stefano Stabellini <sstabellini@kernel.org>
Message-Id: <20201210134752.780923-11-marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
 2020-12-15 12:53:13 -05:00