Bin Meng a89b91addf hw/misc: zynq_slcr: Correctly compute output clocks in the reset exit phase ... As of today, when booting upstream U-Boot for Xilinx Zynq, the UART does not receive anything. Debugging shows that the UART input clock frequency is zero which prevents the UART from receiving anything as per the logic in uart_receive(). From zynq_slcr_reset_exit() comment, it intends to compute output clocks according to ps_clk and registers. zynq_slcr_compute_clocks() is called to accomplish the task, inside which device_is_in_reset() is called to actually make the attempt in vain. Rework reset_hold() and reset_exit() so that in the reset exit phase, the logic can really compute output clocks in reset_exit(). With this change, upstream U-Boot boots properly again with: $ qemu-system-arm -M xilinx-zynq-a9 -m 1G -display none -serial null -serial stdio \ -device loader,file=u-boot-dtb.bin,addr=0x4000000,cpu-num=0 Fixes: 38867cb7ec ("hw/misc/zynq_slcr: add clock generation for uarts") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20210901124521.30599-2-bmeng.cn@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2021-09-13 16:07:20 +01:00
..
macio	docs: fix references to docs/devel/tracing.rst	2021-06-02 06:51:09 +02:00
a9scu.c
allwinner-cpucfg.c
allwinner-h3-ccu.c
allwinner-h3-dramc.c
allwinner-h3-sysctrl.c
allwinner-sid.c
applesmc.c
arm11scu.c
arm_integrator_debug.c	arm: Update infocenter.arm.com URLs	2021-02-11 11:50:14 +00:00
arm_l2x0.c
arm_sysctl.c
armsse-cpu-pwrctrl.c	hw/misc/sse-cpu-pwrctrl: Implement SSE-300 CPU<N>_PWRCTRL register block	2021-03-08 17:20:02 +00:00
armsse-cpuid.c	hw/arm/mps2: Update old infocenter.arm.com URLs	2021-03-08 11:54:16 +00:00
armsse-mhu.c	hw/arm/mps2: Update old infocenter.arm.com URLs	2021-03-08 11:54:16 +00:00
armv7m_ras.c	arm: Move M-profile RAS register block into its own device	2021-09-01 11:08:18 +01:00
aspeed_hace.c	hw: Model ASPEED's Hash and Crypto Engine	2021-05-01 10:03:51 +02:00
aspeed_lpc.c	hw/misc: Model KCS devices in the Aspeed LPC controller	2021-03-09 12:01:28 +01:00
aspeed_scu.c
aspeed_sdmc.c
aspeed_xdma.c	hw/misc/aspeed_xdma: Add AST2600 support	2021-05-01 10:03:52 +02:00
auxbus.c	hw/i2c: Introduce i2c_start_recv() and i2c_start_send()	2021-07-08 14:15:01 -05:00
avr_power.c
bcm2835_cprman.c	clock: Add ClockEvent parameter to callbacks	2021-03-08 17:20:01 +00:00
bcm2835_mbox.c
bcm2835_mphi.c
bcm2835_powermgt.c	hw/arm: Add basic power management to raspi.	2021-07-02 11:48:36 +01:00
bcm2835_property.c
bcm2835_rng.c
bcm2835_thermal.c
cbus.c
debugexit.c
eccmemctl.c
edu.c
empty_slot.c
exynos4210_clk.c
exynos4210_pmu.c
exynos4210_rng.c
grlib_ahb_apb_pnp.c
imx6_ccm.c
imx6_src.c
imx6ul_ccm.c
imx7_ccm.c
imx7_gpr.c
imx7_snvs.c	hw: Do not include qemu/log.h if it is not necessary	2021-05-02 17:24:50 +02:00
imx25_ccm.c
imx31_ccm.c
imx_ccm.c	hw: Do not include qemu/log.h if it is not necessary	2021-05-02 17:24:50 +02:00
imx_rngc.c	hw: Do not include qemu/log.h if it is not necessary	2021-05-02 17:24:50 +02:00
iotkit-secctl.c	hw/misc/iotkit-secctl.c: Implement SSE-300 PID register values	2021-03-08 17:20:01 +00:00
iotkit-sysctl.c	hw/misc/iotkit-sysctl: Implement SSE-200 and SSE-300 PID register values	2021-03-08 17:20:02 +00:00
iotkit-sysinfo.c	hw/misc/iotkit-sysinfo.c: Implement SYS_CONFIG1 and IIDR	2021-03-08 17:20:01 +00:00
ivshmem.c	softmmu/memory: Pass ram_flags to qemu_ram_alloc_from_fd()	2021-06-15 20:27:38 +02:00
Kconfig	sensor: Move hardware sensors from misc to a sensor directory	2021-06-17 07:10:32 -05:00
led.c	hw: Do not include hw/irq.h if it is not necessary	2021-05-02 17:24:50 +02:00
mac_via.c	mac_via: add qdev gpios for nubus slot interrupts to VIA2	2021-09-08 15:37:41 +02:00
mchp_pfsoc_dmc.c	hw: Remove superfluous includes of hw/hw.h	2021-05-02 17:24:50 +02:00
mchp_pfsoc_ioscb.c	hw: Remove superfluous includes of hw/hw.h	2021-05-02 17:24:50 +02:00
mchp_pfsoc_sysreg.c	hw: Remove superfluous includes of hw/hw.h	2021-05-02 17:24:50 +02:00
meson.build	arm: Move M-profile RAS register block into its own device	2021-09-01 11:08:18 +01:00
mips_cmgcr.c
mips_cpc.c
mips_itu.c	Do not include cpu.h if it's not really necessary	2021-05-02 17:24:51 +02:00
mos6522.c
mps2-fpgaio.c	hw/misc/mps2-fpgaio: Support AN547 DBGCTRL register	2021-03-08 17:20:03 +00:00
mps2-scc.c	hw/misc/mps2-scc: Support using CFG0 bit 0 for remapping	2021-05-10 17:21:54 +01:00
msf2-sysreg.c
mst_fpga.c	hw/arm: Constify VMStateDescription	2021-05-02 17:24:50 +02:00
npcm7xx_clk.c	arm: Consistently use "Cortex-Axx", not "Cortex Axx"	2021-06-03 16:43:25 +01:00
npcm7xx_gcr.c
npcm7xx_mft.c	hw/misc: Add NPCM7XX MFT Module	2021-03-12 12:48:56 +00:00
npcm7xx_pwm.c	hw/misc: Add GPIOs for duty in NPCM7xx PWM	2021-03-12 12:48:56 +00:00
npcm7xx_rng.c
nrf51_rng.c
omap_clk.c
omap_gpmc.c
omap_l4.c
omap_sdrc.c
omap_tap.c
pc-testdev.c
pca9552.c
pci-testdev.c
pvpanic-isa.c	hw: Do not include qemu/log.h if it is not necessary	2021-05-02 17:24:50 +02:00
pvpanic-pci.c	hw: Do not include qemu/log.h if it is not necessary	2021-05-02 17:24:50 +02:00
pvpanic.c
sbsa_ec.c	Fix SPDX-License-Identifier typos	2021-02-20 12:36:19 +01:00
sga.c
sifive_e_prci.c	hw: Remove superfluous includes of hw/hw.h	2021-05-02 17:24:50 +02:00
sifive_test.c	hw: Remove superfluous includes of hw/hw.h	2021-05-02 17:24:50 +02:00
sifive_u_otp.c	hw/misc: sifive_u_otp: Use error_report() when block operation fails	2021-03-04 09:43:29 -05:00
sifive_u_prci.c
slavio_misc.c
stm32f2xx_syscfg.c
stm32f4xx_exti.c
stm32f4xx_syscfg.c
trace-events	docs: fix references to docs/devel/tracing.rst	2021-06-02 06:51:09 +02:00
trace.h
tz-mpc.c
tz-msc.c
tz-ppc.c
unimp.c
virt_ctrl.c	hw: Do not include hw/irq.h if it is not necessary	2021-05-02 17:24:50 +02:00
vmcoreinfo.c
xlnx-versal-xramc.c	hw/misc: versal: Add a model of the XRAM controller	2021-03-12 12:40:09 +00:00
zynq_slcr.c	hw/misc: zynq_slcr: Correctly compute output clocks in the reset exit phase	2021-09-13 16:07:20 +01:00