Anup Patel 188000952c target/riscv: Don't force update priv spec version to latest ... The riscv_cpu_realize() sets priv spec version to v1.12 when it is when "env->priv_ver == 0" (i.e. default v1.10) because the enum value of priv spec v1.10 is zero. Due to above issue, the sifive_u machine will see priv spec v1.12 instead of priv spec v1.10. To fix this issue, we set latest priv spec version (i.e. v1.12) for base rv64/rv32 cpu and riscv_cpu_realize() will override priv spec version only when "cpu->cfg.priv_spec != NULL". Fixes: 7100fe6c24 ("target/riscv: Enable privileged spec version 1.12") Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20220611080107.391981-2-apatel@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2022-07-03 10:03:20 +10:00
..
alpha
arm	semihosting: Split out common-semi-target.h	2022-06-28 04:35:07 +05:30
avr	target/avr: Drop avr_cpu_memory_rw_debug()	2022-06-20 13:11:36 -07:00
cris
hexagon
hppa
i386	Fix 'writeable' typos	2022-06-08 19:38:47 +01:00
loongarch	target/loongarch: Add gdb support.	2022-06-06 18:14:13 +00:00
m68k	target/m68k: Make semihosting system only	2022-06-28 10:13:22 +05:30
microblaze
mips	target/mips: Drop pread and pwrite syscalls from semihosting	2022-06-28 10:15:12 +05:30
nios2	target/nios2: Move nios2-semi.c to nios2_softmmu_ss	2022-06-28 10:18:57 +05:30
openrisc
ppc	target/ppc: cpu_init: Clean up stop state on cpu reset	2022-06-20 08:38:59 -03:00
riscv	target/riscv: Don't force update priv spec version to latest	2022-07-03 10:03:20 +10:00
rx
s390x	Fix 'writeable' typos	2022-06-08 19:38:47 +01:00
sh4
sparc
tricore
xtensa
Kconfig	hw/loongarch: Add support loongson3 virt machine type.	2022-06-06 18:09:03 +00:00
meson.build	target/loongarch: Add target build suport	2022-06-06 18:09:03 +00:00