qemu-e2k/target/riscv
Anup Patel 188000952c target/riscv: Don't force update priv spec version to latest
The riscv_cpu_realize() sets priv spec version to v1.12 when it is
when "env->priv_ver == 0" (i.e. default v1.10) because the enum
value of priv spec v1.10 is zero.

Due to above issue, the sifive_u machine will see priv spec v1.12
instead of priv spec v1.10.

To fix this issue, we set latest priv spec version (i.e. v1.12)
for base rv64/rv32 cpu and riscv_cpu_realize() will override priv
spec version only when "cpu->cfg.priv_spec != NULL".

Fixes: 7100fe6c24 ("target/riscv: Enable privileged spec version 1.12")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220611080107.391981-2-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-07-03 10:03:20 +10:00
..
insn_trans target/riscv: Minimize the calls to decode_save_opc 2022-07-03 10:03:20 +10:00
arch_dump.c
bitmanip_helper.c target/riscv: rvk: add support for zbkx extension 2022-04-29 10:47:45 +10:00
common-semi-target.h semihosting: Split out common-semi-target.h 2022-06-28 04:35:07 +05:30
cpu_bits.h target/riscv: Implement mcountinhibit CSR 2022-07-03 10:03:20 +10:00
cpu_helper.c semihosting: Return void from do_common_semihosting 2022-06-28 04:35:07 +05:30
cpu_user.h
cpu-param.h Normalize header guard symbol definition 2022-05-11 16:50:26 +02:00
cpu.c target/riscv: Don't force update priv spec version to latest 2022-07-03 10:03:20 +10:00
cpu.h target/riscv: Support mcycle/minstret write operation 2022-07-03 10:03:20 +10:00
crypto_helper.c target/riscv: rvk: add support for zksed/zksh extension 2022-04-29 10:47:45 +10:00
csr.c target/riscv: Fixup MSECCFG minimum priv check 2022-07-03 10:03:20 +10:00
debug.c target/riscv/debug.c: keep experimental rv128 support working 2022-06-10 09:31:42 +10:00
debug.h target/riscv: csr: Hook debug CSR read/write 2022-04-22 10:35:16 +10:00
fpu_helper.c target/riscv: add support for zhinx/zhinxmin 2022-03-03 13:14:50 +10:00
gdbstub.c
helper.h target/riscv: rvk: add support for zksed/zksh extension 2022-04-29 10:47:45 +10:00
insn16.decode
insn32.decode target/riscv: rvk: add support for zksed/zksh extension 2022-04-29 10:47:45 +10:00
instmap.h
internals.h target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions 2022-06-10 09:31:42 +10:00
Kconfig
kvm_riscv.h
kvm-stub.c
kvm.c Remove qemu-common.h include from most units 2022-04-06 14:31:55 +02:00
m128_helper.c
machine.c target/riscv: Support mcycle/minstret write operation 2022-07-03 10:03:20 +10:00
meson.build target/riscv: Support mcycle/minstret write operation 2022-07-03 10:03:20 +10:00
monitor.c target/riscv: Fix incorrect PTE merge in walk_pte 2022-04-29 10:47:46 +10:00
op_helper.c target/riscv: rvk: add CSR support for Zkr 2022-04-29 10:47:45 +10:00
pmp.c target/riscv/pmp: guard against PMP ranges with a negative size 2022-07-03 10:03:20 +10:00
pmp.h target/riscv: rvk: add CSR support for Zkr 2022-04-29 10:47:45 +10:00
pmu.c target/riscv: Support mcycle/minstret write operation 2022-07-03 10:03:20 +10:00
pmu.h target/riscv: Support mcycle/minstret write operation 2022-07-03 10:03:20 +10:00
sbi_ecall_interface.h Clean up ill-advised or unusual header guards 2022-05-11 16:50:01 +02:00
trace-events
trace.h
translate.c target/riscv: Minimize the calls to decode_save_opc 2022-07-03 10:03:20 +10:00
vector_helper.c target/riscv: rvv: Add tail agnostic for vector permutation instructions 2022-06-10 09:31:42 +10:00
XVentanaCondOps.decode target/riscv: Add XVentanaCondOps custom extension 2022-02-16 12:24:18 +10:00