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qemu-e2k/target/riscv
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Alistair Francis 07314158f6 target/riscv: trans_rvv: Avoid assert for RV32 and e64 
When running a 32-bit guest, with a e64 vmv.v.x and vl_eq_vlmax set to
true the `tcg_debug_assert(vece <= MO_32)` will be triggered inside
tcg_gen_gvec_dup_i32().

This patch checks that condition and instead uses tcg_gen_gvec_dup_i64()
is required.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1028
Suggested-by: Robert Bu <robert.bu@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220608234701.369536-1-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 		2022-06-10 09:42:12 +10:00
..
insn_trans target/riscv: trans_rvv: Avoid assert for RV32 and e64 2022-06-10 09:42:12 +10:00
Kconfig meson: Introduce target-specific Kconfig 2021-07-09 18:21:34 +02:00
XVentanaCondOps.decode target/riscv: Add XVentanaCondOps custom extension 2022-02-16 12:24:18 +10:00
arch_dump.c target-riscv: support QMP dump-guest-memory 2021-03-04 09:43:29 -05:00
bitmanip_helper.c target/riscv: rvk: add support for zbkx extension 2022-04-29 10:47:45 +10:00
cpu-param.h Normalize header guard symbol definition 2022-05-11 16:50:26 +02:00
cpu.c target/riscv: Don't expose the CPU properties on names CPUs 2022-06-10 09:31:43 +10:00
cpu.h target/riscv: rvv: Add tail agnostic for vv instructions 2022-06-10 09:31:42 +10:00
cpu_bits.h target/riscv: rvk: add CSR support for Zkr 2022-04-29 10:47:45 +10:00
cpu_helper.c target/riscv: rvv: Add tail agnostic for vv instructions 2022-06-10 09:31:42 +10:00
cpu_user.h Supply missing header guards 2019-06-12 13:20:21 +02:00
crypto_helper.c target/riscv: rvk: add support for zksed/zksh extension 2022-04-29 10:47:45 +10:00
csr.c target/riscv: Fix csr number based privilege checking 2022-05-24 10:38:50 +10:00
debug.c target/riscv/debug.c: keep experimental rv128 support working 2022-06-10 09:31:42 +10:00
debug.h target/riscv: csr: Hook debug CSR read/write 2022-04-22 10:35:16 +10:00
fpu_helper.c target/riscv: add support for zhinx/zhinxmin 2022-03-03 13:14:50 +10:00
gdbstub.c target/riscv: correct "code should not be reached" for x-rv128 2022-02-16 12:24:18 +10:00
helper.h target/riscv: rvk: add support for zksed/zksh extension 2022-04-29 10:47:45 +10:00
insn16.decode target/riscv: accessors to registers upper part and 128-bit load/store 2022-01-08 15:46:10 +10:00
insn32.decode target/riscv: rvk: add support for zksed/zksh extension 2022-04-29 10:47:45 +10:00
instmap.h target/riscv: progressively load the instruction during decode 2020-02-25 20:20:23 +00:00
internals.h target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions 2022-06-10 09:31:42 +10:00
kvm-stub.c target/riscv: Support setting external interrupt by KVM 2022-01-21 15:52:56 +10:00
kvm.c Remove qemu-common.h include from most units 2022-04-06 14:31:55 +02:00
kvm_riscv.h target/riscv: Support setting external interrupt by KVM 2022-01-21 15:52:56 +10:00
m128_helper.c target/riscv: support for 128-bit M extension 2022-01-08 15:46:10 +10:00
machine.c target/riscv: machine: Add debug state description 2022-04-22 10:35:16 +10:00
meson.build target/riscv: rvk: add support for zknd/zkne extension in RV32 2022-04-29 10:47:45 +10:00
monitor.c target/riscv: Fix incorrect PTE merge in walk_pte 2022-04-29 10:47:46 +10:00
op_helper.c target/riscv: rvk: add CSR support for Zkr 2022-04-29 10:47:45 +10:00
pmp.c target/riscv/pmp: fix NAPOT range computation overflow 2022-04-22 10:35:16 +10:00
pmp.h target/riscv: rvk: add CSR support for Zkr 2022-04-29 10:47:45 +10:00
sbi_ecall_interface.h Clean up ill-advised or unusual header guards 2022-05-11 16:50:01 +02:00
trace-events target/riscv: Add ePMP CSR access functions 2021-05-11 20:02:06 +10:00
trace.h trace: switch position of headers to what Meson requires 2020-08-21 06:18:24 -04:00
translate.c target/riscv: rvv: Add tail agnostic for vector load / store instructions 2022-06-10 09:31:42 +10:00
vector_helper.c target/riscv: rvv: Add tail agnostic for vector permutation instructions 2022-06-10 09:31:42 +10:00