qemu-e2k/target/tricore
Bastian Koppelmann 19a18edd88 target/tricore: Honour privilege changes on PSW write
the CPU can change the privilege level by writing the corresponding bits
in PSW. If this happens all instructions after this 'mtcr' in the TB are
translated with the wrong privilege level. So we have to exit to the
cpu_loop() and start translating again with the new privilege level.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230621142302.1648383-8-kbastian@mail.uni-paderborn.de>
2023-06-21 18:09:54 +02:00
..
cpu-param.h target/tricore: Remove NB_MMU_MODES define 2023-03-13 06:44:37 -07:00
cpu-qom.h target/tricore: Convert to 3-phase reset 2022-12-16 15:58:16 +00:00
cpu.c target/tricore: Introduce ISA 1.6.2 feature 2023-06-21 17:56:45 +02:00
cpu.h target/tricore: Introduce priv tb flag 2023-06-21 18:09:54 +02:00
csfr.h.inc target/tricore: Rename csfr.def -> csfr.h.inc 2022-11-05 20:35:45 +01:00
fpu_helper.c
gdbstub.c gdbstub: move register helpers into standalone include 2023-03-07 20:44:08 +00:00
helper.c target/tricore: Remove pointless CONFIG_SOFTMMU guard 2023-06-20 10:01:30 +02:00
helper.h target/tricore: Add shuffle insn 2023-06-21 18:09:48 +02:00
Kconfig
meson.build meson: Replace softmmu_ss -> system_ss 2023-06-20 10:01:30 +02:00
op_helper.c target/tricore: Fix helper_ret() not correctly restoring PSW 2023-06-21 18:09:54 +02:00
translate.c target/tricore: Honour privilege changes on PSW write 2023-06-21 18:09:54 +02:00
tricore-defs.h
tricore-opcodes.h target/tricore: Add DISABLE insn variant 2023-06-21 18:09:54 +02:00