Yueh-Ting (eop) Chen 265ecd4c62 target/riscv: rvv: Add mask agnostic for vector load / store instructions ... Signed-off-by: eop Chen <eop.chen@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <165570784143.17634.35095816584573691-2@git.sr.ht> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2022-09-07 09:18:33 +02:00
..
insn_trans	target/riscv: rvv: Add mask agnostic for vector load / store instructions	2022-09-07 09:18:33 +02:00
arch_dump.c
bitmanip_helper.c	target/riscv: rvk: add support for zbkx extension	2022-04-29 10:47:45 +10:00
common-semi-target.h	semihosting: Split out common-semi-target.h	2022-06-28 04:35:07 +05:30
cpu_bits.h	target/riscv: Update default priority table for local interrupts	2022-07-03 10:03:20 +10:00
cpu_helper.c	target/riscv: rvv: Add mask agnostic for vv instructions	2022-09-07 09:18:32 +02:00
cpu_user.h
cpu-param.h	Normalize header guard symbol definition	2022-05-11 16:50:26 +02:00
cpu.c	target/riscv: Fix checks in hmode/hmode32	2022-09-07 09:18:32 +02:00
cpu.h	target/riscv: rvv: Add mask agnostic for vv instructions	2022-09-07 09:18:32 +02:00
crypto_helper.c	target/riscv: rvk: add support for zksed/zksh extension	2022-04-29 10:47:45 +10:00
csr.c	target/riscv: Simplify the check in hmode to reuse the check in riscv_csrrw_check	2022-09-07 09:18:32 +02:00
debug.c	target/riscv/debug.c: keep experimental rv128 support working	2022-06-10 09:31:42 +10:00
debug.h	target/riscv: csr: Hook debug CSR read/write	2022-04-22 10:35:16 +10:00
fpu_helper.c	target/riscv: add support for zhinx/zhinxmin	2022-03-03 13:14:50 +10:00
gdbstub.c
helper.h	target/riscv: rvk: add support for zksed/zksh extension	2022-04-29 10:47:45 +10:00
insn16.decode	target/riscv: fix shifts shamt value for rv128c	2022-09-07 09:18:32 +02:00
insn32.decode	target/riscv: rvk: add support for zksed/zksh extension	2022-04-29 10:47:45 +10:00
instmap.h	target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()	2022-09-07 09:18:32 +02:00
internals.h	target/riscv: rvv: Add mask agnostic for vv instructions	2022-09-07 09:18:32 +02:00
Kconfig
kvm_riscv.h
kvm-stub.c
kvm.c	Remove qemu-common.h include from most units	2022-04-06 14:31:55 +02:00
m128_helper.c
machine.c	target/riscv: Support mcycle/minstret write operation	2022-07-03 10:03:20 +10:00
meson.build	meson: remove dead code	2022-09-01 07:42:37 +02:00
monitor.c	target/riscv: Fix incorrect PTE merge in walk_pte	2022-04-29 10:47:46 +10:00
op_helper.c	target/riscv: rvk: add CSR support for Zkr	2022-04-29 10:47:45 +10:00
pmp.c	target/riscv/pmp: guard against PMP ranges with a negative size	2022-07-03 10:03:20 +10:00
pmp.h	target/riscv: rvk: add CSR support for Zkr	2022-04-29 10:47:45 +10:00
pmu.c	target/riscv: Support mcycle/minstret write operation	2022-07-03 10:03:20 +10:00
pmu.h	target/riscv: Support mcycle/minstret write operation	2022-07-03 10:03:20 +10:00
sbi_ecall_interface.h	Clean up ill-advised or unusual header guards	2022-05-11 16:50:01 +02:00
trace-events
trace.h
translate.c	target/riscv: rvv: Add mask agnostic for vv instructions	2022-09-07 09:18:32 +02:00
vector_helper.c	target/riscv: rvv: Add mask agnostic for vector load / store instructions	2022-09-07 09:18:33 +02:00
XVentanaCondOps.decode