Alistair Francis c30a0757f0 target/riscv: Fix the RV64H decode comment ... BugLink: https://gitlab.com/qemu-project/qemu/-/issues/47 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 024ce841221c1d15c74b253512428c4baca7e4ba.1619234854.git.alistair.francis@wdc.com		2021-05-11 20:02:07 +10:00
..
insn_trans	target/riscv: Consolidate RV32/64 16-bit instructions	2021-05-11 20:02:07 +10:00
arch_dump.c	target-riscv: support QMP dump-guest-memory	2021-03-04 09:43:29 -05:00
cpu_bits.h	target/riscv: Remove the unused HSTATUS_WPRI macro	2021-05-11 20:02:07 +10:00
cpu_helper.c	target/riscv: Remove the hardcoded SATP_MODE macro	2021-05-11 20:02:07 +10:00
cpu_user.h
cpu-param.h	target/riscv: Add a virtualised MMU Mode	2020-11-09 15:08:45 -08:00
cpu.c	target/riscv: Remove the hardcoded RVXLEN macro	2021-05-11 20:02:07 +10:00
cpu.h	target/riscv: Remove the hardcoded RVXLEN macro	2021-05-11 20:02:07 +10:00
csr.c	target/riscv: Remove the hardcoded SATP_MODE macro	2021-05-11 20:02:07 +10:00
fpu_helper.c	target/riscv: Consolidate RV32/64 32-bit instructions	2021-05-11 20:02:07 +10:00
gdbstub.c	target/riscv: Use RISCVException enum for CSR access	2021-05-11 20:02:06 +10:00
helper.h	target/riscv: Consolidate RV32/64 32-bit instructions	2021-05-11 20:02:07 +10:00
insn16.decode	target/riscv: Consolidate RV32/64 16-bit instructions	2021-05-11 20:02:07 +10:00
insn32.decode	target/riscv: Fix the RV64H decode comment	2021-05-11 20:02:07 +10:00
instmap.h
internals.h
machine.c	target/riscv: Remove privilege v1.9 specific CSR related code	2021-05-11 20:01:10 +10:00
meson.build	target/riscv: Consolidate RV32/64 16-bit instructions	2021-05-11 20:02:07 +10:00
monitor.c	target/riscv: Remove the hardcoded SATP_MODE macro	2021-05-11 20:02:07 +10:00
op_helper.c	target/riscv: Use RISCVException enum for CSR access	2021-05-11 20:02:06 +10:00
pmp.c	target/riscv/pmp: Remove outdated comment	2021-05-11 20:02:06 +10:00
pmp.h	target/riscv: Add ePMP CSR access functions	2021-05-11 20:02:06 +10:00
trace-events	target/riscv: Add ePMP CSR access functions	2021-05-11 20:02:06 +10:00
trace.h
translate.c	target/riscv: Consolidate RV32/64 32-bit instructions	2021-05-11 20:02:07 +10:00
vector_helper.c	target/riscv: Consolidate RV32/64 32-bit instructions	2021-05-11 20:02:07 +10:00