qemu-e2k/target/riscv
LIU Zhiwei 42967f4073 target/riscv: Add a general status enum for extensions
The pointer masking is the only extension that directly use status.
The vector or float extension uses the status in an indirect way.

Replace the pointer masking extension special status fields with
the general status.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-Id: <20230324143031.1093-3-zhiwei_liu@linux.alibaba.com>
[rth: Add a typedef for the enum]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-3-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-3-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05 10:49:50 +10:00
..
insn_trans target/riscv: remove cpu->cfg.ext_e 2023-05-05 10:49:50 +10:00
arch_dump.c target/riscv: Fix format for comments 2023-05-05 10:49:50 +10:00
bitmanip_helper.c target/riscv: rvk: add support for zbkx extension 2022-04-29 10:47:45 +10:00
common-semi-target.h semihosting: Split out common-semi-target.h 2022-06-28 04:35:07 +05:30
cpu_bits.h target/riscv: Add a general status enum for extensions 2023-05-05 10:49:50 +10:00
cpu_helper.c target/riscv: Extract virt enabled state from tb flags 2023-05-05 10:49:50 +10:00
cpu_user.h
cpu_vendorid.h RISC-V: Add initial support for T-Head C906 2023-02-07 08:19:23 +10:00
cpu-param.h target/riscv: Remove NB_MMU_MODES define 2023-03-13 06:44:37 -07:00
cpu.c target/riscv: Add a general status enum for extensions 2023-05-05 10:49:50 +10:00
cpu.h target/riscv: Add a general status enum for extensions 2023-05-05 10:49:50 +10:00
crypto_helper.c target/riscv: rvk: add support for zksed/zksh extension 2022-04-29 10:47:45 +10:00
csr.c target/riscv: Add a general status enum for extensions 2023-05-05 10:49:50 +10:00
debug.c target/riscv: Fix lines with over 80 characters 2023-05-05 10:49:50 +10:00
debug.h target/riscv: Add itrigger support when icount is enabled 2023-01-06 10:42:55 +10:00
fpu_helper.c target/riscv: Fix format for indentation 2023-05-05 10:49:50 +10:00
gdbstub.c target/riscv: Use PRV_RESERVED instead of PRV_H 2023-05-05 10:49:50 +10:00
helper.h target/riscv: add support for Zcmt extension 2023-05-05 10:49:50 +10:00
insn16.decode target/riscv: add support for Zcmt extension 2023-05-05 10:49:50 +10:00
insn32.decode target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholder 2023-03-05 11:49:43 -08:00
instmap.h target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() 2022-09-07 09:18:32 +02:00
internals.h target/riscv: rvv: Add mask agnostic for vv instructions 2022-09-07 09:18:32 +02:00
Kconfig
kvm_riscv.h
kvm-stub.c
kvm.c target/riscv: fix SBI getchar handler for KVM 2023-02-07 08:19:23 +10:00
m128_helper.c target/riscv: Fix format for indentation 2023-05-05 10:49:50 +10:00
machine.c target/riscv: Fix format for indentation 2023-05-05 10:49:50 +10:00
meson.build target/riscv: add support for Zcmt extension 2023-05-05 10:49:50 +10:00
monitor.c target/riscv: remove RISCV_FEATURE_MMU 2023-03-01 13:47:15 -08:00
op_helper.c target/riscv: fix H extension TVM trap 2023-05-05 10:49:50 +10:00
pmp.c target/riscv: Fix lines with over 80 characters 2023-05-05 10:49:50 +10:00
pmp.h target/riscv: Fix format for indentation 2023-05-05 10:49:50 +10:00
pmu.c target/riscv: Fix lines with over 80 characters 2023-05-05 10:49:50 +10:00
pmu.h riscv: Clean up includes 2023-02-08 07:28:05 +01:00
sbi_ecall_interface.h target/riscv: Fix format for comments 2023-05-05 10:49:50 +10:00
time_helper.c target/riscv: Simplify type conversion for CPURISCVState 2023-05-05 10:49:49 +10:00
time_helper.h target/riscv: Simplify type conversion for CPURISCVState 2023-05-05 10:49:49 +10:00
trace-events
trace.h
translate.c target/riscv: Extract virt enabled state from tb flags 2023-05-05 10:49:50 +10:00
vector_helper.c target/riscv: Fix lines with over 80 characters 2023-05-05 10:49:50 +10:00
xthead.decode RISC-V: Adding XTheadFmv ISA extension 2023-02-07 08:19:23 +10:00
XVentanaCondOps.decode
zce_helper.c target/riscv: add support for Zcmt extension 2023-05-05 10:49:50 +10:00