qemu-e2k/target/riscv
Fei Wu 47debc7280 target/riscv: Separate priv from mmu_idx
Currently it's assumed the 2 low bits of mmu_idx map to privilege mode,
this assumption won't last as we are about to add more mmu_idx. Here an
individual priv field is added into TB_FLAGS.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Fei Wu <fei2.wu@intel.com>
Message-Id: <20230324054154.414846-2-fei2.wu@intel.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-7-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-7-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05 10:49:50 +10:00
..
insn_trans target/riscv: Separate priv from mmu_idx 2023-05-05 10:49:50 +10:00
arch_dump.c target/riscv: Fix format for comments 2023-05-05 10:49:50 +10:00
bitmanip_helper.c
common-semi-target.h
cpu_bits.h target/riscv: Add a general status enum for extensions 2023-05-05 10:49:50 +10:00
cpu_helper.c target/riscv: Separate priv from mmu_idx 2023-05-05 10:49:50 +10:00
cpu_user.h
cpu_vendorid.h RISC-V: Add initial support for T-Head C906 2023-02-07 08:19:23 +10:00
cpu-param.h target/riscv: Remove NB_MMU_MODES define 2023-03-13 06:44:37 -07:00
cpu.c target/riscv: Add a general status enum for extensions 2023-05-05 10:49:50 +10:00
cpu.h target/riscv: Separate priv from mmu_idx 2023-05-05 10:49:50 +10:00
crypto_helper.c
csr.c target/riscv: Add a general status enum for extensions 2023-05-05 10:49:50 +10:00
debug.c target/riscv: Fix lines with over 80 characters 2023-05-05 10:49:50 +10:00
debug.h target/riscv: Add itrigger support when icount is enabled 2023-01-06 10:42:55 +10:00
fpu_helper.c target/riscv: Fix format for indentation 2023-05-05 10:49:50 +10:00
gdbstub.c target/riscv: Use PRV_RESERVED instead of PRV_H 2023-05-05 10:49:50 +10:00
helper.h target/riscv: add support for Zcmt extension 2023-05-05 10:49:50 +10:00
insn16.decode target/riscv: add support for Zcmt extension 2023-05-05 10:49:50 +10:00
insn32.decode target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholder 2023-03-05 11:49:43 -08:00
instmap.h
internals.h
Kconfig
kvm_riscv.h
kvm-stub.c
kvm.c target/riscv: fix SBI getchar handler for KVM 2023-02-07 08:19:23 +10:00
m128_helper.c target/riscv: Fix format for indentation 2023-05-05 10:49:50 +10:00
machine.c target/riscv: Fix format for indentation 2023-05-05 10:49:50 +10:00
meson.build target/riscv: add support for Zcmt extension 2023-05-05 10:49:50 +10:00
monitor.c target/riscv: remove RISCV_FEATURE_MMU 2023-03-01 13:47:15 -08:00
op_helper.c target/riscv: fix H extension TVM trap 2023-05-05 10:49:50 +10:00
pmp.c target/riscv: Fix lines with over 80 characters 2023-05-05 10:49:50 +10:00
pmp.h target/riscv: Fix format for indentation 2023-05-05 10:49:50 +10:00
pmu.c target/riscv: Fix lines with over 80 characters 2023-05-05 10:49:50 +10:00
pmu.h riscv: Clean up includes 2023-02-08 07:28:05 +01:00
sbi_ecall_interface.h target/riscv: Fix format for comments 2023-05-05 10:49:50 +10:00
time_helper.c target/riscv: Simplify type conversion for CPURISCVState 2023-05-05 10:49:49 +10:00
time_helper.h target/riscv: Simplify type conversion for CPURISCVState 2023-05-05 10:49:49 +10:00
trace-events
trace.h
translate.c target/riscv: Separate priv from mmu_idx 2023-05-05 10:49:50 +10:00
vector_helper.c target/riscv: Fix lines with over 80 characters 2023-05-05 10:49:50 +10:00
xthead.decode RISC-V: Adding XTheadFmv ISA extension 2023-02-07 08:19:23 +10:00
XVentanaCondOps.decode
zce_helper.c target/riscv: add support for Zcmt extension 2023-05-05 10:49:50 +10:00