qemu-e2k/target
Frederic Barrat 609b1c8669 target/ppc: cpu_init: Clean up stop state on cpu reset
The 'resume_as_sreset' attribute of a cpu is set when a thread is
entering a stop state on ppc books. It causes the thread to be
re-routed to vector 0x100 when woken up by an exception. So it must be
cleared on reset or a thread might be re-routed unexpectedly after a
reset, when it was not in a stop state and/or when the appropriate
exception handler isn't set up yet.

Using skiboot, it can be tested by resetting the system when it is
quiet and most threads are idle and in stop state.

After the reset occurs, skiboot elects a primary thread and all the
others wait in secondary_wait. The primary thread does all the system
initialization from main_cpu_entry() and at some point, the
decrementer interrupt starts ticking. The exception vector for the
decrementer interrupt is in place, so that shouldn't be a
problem. However, if that primary thread was in stop state prior to
the reset, and because the resume_as_sreset parameters is still set,
it is re-routed to exception vector 0x100. Which, at that time, is
still defined as the entry point for BML. So that primary thread
restarts as new and ends up being treated like any other secondary
thread. All threads are now waiting in secondary_wait.

It results in a full system hang with no message on the console, as
the uart hasn't been init'ed yet. It's actually not obvious to realise
what's happening if not tracing reset (-d cpu_reset). The fix is
simply to clear the 'resume_as_sreset' attribute on reset.

Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220617095222.612212-1-fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-06-20 08:38:59 -03:00
..
alpha Normalize header guard symbol definition 2022-05-11 16:50:26 +02:00
arm target/arm: SCR_EL3.RW is RAO/WI without AArch32 EL[12] 2022-06-10 14:32:35 +01:00
avr Clean up decorations and whitespace around header guards 2022-05-11 16:50:32 +02:00
cris Normalize header guard symbol definition 2022-05-11 16:50:26 +02:00
hexagon Clean up decorations and whitespace around header guards 2022-05-11 16:50:32 +02:00
hppa Normalize header guard symbol definition 2022-05-11 16:50:26 +02:00
i386 Fix 'writeable' typos 2022-06-08 19:38:47 +01:00
loongarch target/loongarch: Add gdb support. 2022-06-06 18:14:13 +00:00
m68k target/m68k: Mark helper_raise_exception as noreturn 2022-06-02 09:35:03 +02:00
microblaze Normalize header guard symbol definition 2022-05-11 16:50:26 +02:00
mips target/mips: Add missing default cases for some nanoMIPS pools 2022-06-11 11:36:01 +02:00
nios2 Normalize header guard symbol definition 2022-05-11 16:50:26 +02:00
openrisc OpenRISC Fixes for 7.0 2022-05-15 16:56:27 -07:00
ppc target/ppc: cpu_init: Clean up stop state on cpu reset 2022-06-20 08:38:59 -03:00
riscv target/riscv: trans_rvv: Avoid assert for RV32 and e64 2022-06-10 09:42:12 +10:00
rx Fix usp/isp swapping upon clrpsw/setpsw. 2022-04-21 16:45:41 -07:00
s390x Fix 'writeable' typos 2022-06-08 19:38:47 +01:00
sh4 Normalize header guard symbol definition 2022-05-11 16:50:26 +02:00
sparc Normalize header guard symbol definition 2022-05-11 16:50:26 +02:00
tricore Normalize header guard symbol definition 2022-05-11 16:50:26 +02:00
xtensa Clean up decorations and whitespace around header guards 2022-05-11 16:50:32 +02:00
Kconfig hw/loongarch: Add support loongson3 virt machine type. 2022-06-06 18:09:03 +00:00
meson.build target/loongarch: Add target build suport 2022-06-06 18:09:03 +00:00