qemu-e2k/target/riscv
Jason Chien 60ef34a48c target/riscv: Set the correct exception for implict G-stage translation fail
The privileged spec states:
For a memory access made to support VS-stage address translation (such as
to read/write a VS-level page table), permissions are checked as though
for a load or store, not for the original access type. However, any
exception is always reported for the original access type (instruction,
load, or store/AMO).

The current implementation converts the access type to LOAD if implicit
G-stage translation fails which results in only reporting "Load guest-page
fault". This commit removes the convertion of access type, so the reported
exception conforms to the spec.

Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230627074915.7686-1-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-07-10 22:29:15 +10:00
..
insn_trans target/riscv: Add support for Zvfbfwma extension 2023-07-10 22:29:15 +10:00
arch_dump.c target/riscv: Fix format for comments 2023-05-05 10:49:50 +10:00
bitmanip_helper.c
common-semi-target.h
cpu_bits.h riscv: Make sure an exception is raised if a pte is malformed 2023-05-05 10:49:50 +10:00
cpu_cfg.h target/riscv: Add properties for BF16 extensions 2023-07-10 22:29:15 +10:00
cpu_helper.c target/riscv: Set the correct exception for implict G-stage translation fail 2023-07-10 22:29:15 +10:00
cpu_user.h
cpu_vendorid.h target/riscv: add Ventana's Veyron V1 CPU 2023-05-05 10:49:50 +10:00
cpu-param.h
cpu-qom.h target/riscv: add Ventana's Veyron V1 CPU 2023-05-05 10:49:50 +10:00
cpu.c target/riscv: Expose properties for BF16 extensions 2023-07-10 22:29:15 +10:00
cpu.h target/riscv: Add additional xlen for address when MPRV=1 2023-07-10 22:29:14 +10:00
crypto_helper.c target/riscv: Use aesdec_ISB_ISR_IMC_AK 2023-07-09 13:47:17 +01:00
csr.c target/riscv: update cur_pmbase/pmmask based on mode affected by MPRV 2023-07-10 22:29:14 +10:00
debug.c target/riscv: Fix lines with over 80 characters 2023-05-05 10:49:50 +10:00
debug.h
fpu_helper.c target/riscv: Add support for Zfbfmin extension 2023-07-10 22:29:15 +10:00
gdbstub.c target/riscv: Use PRV_RESERVED instead of PRV_H 2023-05-05 10:49:50 +10:00
helper.h target/riscv: Add support for Zvfbfwma extension 2023-07-10 22:29:15 +10:00
insn16.decode
insn32.decode target/riscv: Add support for Zvfbfwma extension 2023-07-10 22:29:15 +10:00
instmap.h
internals.h target/riscv: Introduce mmuidx_2stage 2023-05-05 10:49:50 +10:00
Kconfig
kvm_riscv.h
kvm-stub.c
kvm.c
m128_helper.c target/riscv: Fix format for indentation 2023-05-05 10:49:50 +10:00
machine.c target/riscv: Restrict KVM-specific fields from ArchCPU 2023-06-28 14:27:59 +02:00
meson.build meson: Replace softmmu_ss -> system_ss 2023-06-20 10:01:30 +02:00
monitor.c
op_helper.c target/riscv: Make MPV only work when MPP != PRV_M 2023-07-10 22:29:14 +10:00
pmp.c target/riscv: Smepmp: Return error when access permission not allowed in PMP 2023-06-13 17:45:30 +10:00
pmp.h target/riscv: Change the return type of pmp_hart_has_privs() to bool 2023-06-13 17:09:13 +10:00
pmu.c target/riscv: Fix lines with over 80 characters 2023-05-05 10:49:50 +10:00
pmu.h
riscv-qmp-cmds.c target/riscv: add TYPE_RISCV_DYNAMIC_CPU 2023-05-05 10:49:50 +10:00
sbi_ecall_interface.h target/riscv: Fix format for comments 2023-05-05 10:49:50 +10:00
time_helper.c
time_helper.h
trace-events
trace.h
translate.c target/riscv: Add support for Zfbfmin extension 2023-07-10 22:29:15 +10:00
vector_helper.c target/riscv: Add support for Zvfbfwma extension 2023-07-10 22:29:15 +10:00
xthead.decode
XVentanaCondOps.decode
zce_helper.c