00f05c02f9
An option on real hardware when embedding a DMA engine into a peripheral is to make the peripheral control the engine through a custom DMA control (hardware) interface between the two. Software drivers in this scenario configure and trigger DMA operations through the controlling peripheral's register API (for example, writing a specific bit in a register could propagate down to a transfer start signal on the DMA control interface). At the same time the status, results and interrupts for the transfer might still be intended to be read and caught through the DMA engine's register API (and signals). This patch adds a class 'read' method for allowing to start read transfers from peripherals embedding and controlling the Xilinx CSU DMA engine as in above scenario. Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20220121161141.14389-6-francisco.iglesias@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
||
|---|---|---|
| .. | ||
| bcm2835_dma.h | ||
| i8257.h | ||
| pl080.h | ||
| sifive_pdma.h | ||
| xlnx_csu_dma.h | ||
| xlnx_dpdma.h | ||
| xlnx-zdma.h | ||
| xlnx-zynq-devcfg.h | ||