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qemu-e2k/target/riscv
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Frank Chang 6b85975e11 target/riscv: rvv-1.0: whole register move instructions 
Add the following instructions:

* vmv1r.v
* vmv2r.v
* vmv4r.v
* vmv8r.v

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-40-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20 14:51:36 +10:00
..
insn_trans
target/riscv: rvv-1.0: whole register move instructions
2021-12-20 14:51:36 +10:00
arch_dump.c
target-riscv: support QMP dump-guest-memory
2021-03-04 09:43:29 -05:00
bitmanip_helper.c
target/riscv: Add rev8 instruction, removing grev/grevi
2021-10-07 08:41:33 +10:00
cpu_bits.h
target/riscv: rvv-1.0: add vlenb register
2021-12-20 14:51:36 +10:00
cpu_helper.c
target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation
2021-12-20 14:51:36 +10:00
cpu_user.h
…
cpu-param.h
target/riscv: Add a virtualised MMU Mode
2020-11-09 15:08:45 -08:00
cpu.c
target/riscv: drop vector 0.7.1 and add 1.0 support
2021-12-20 14:51:36 +10:00
cpu.h
target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation
2021-12-20 14:51:36 +10:00
csr.c
target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers
2021-12-20 14:51:36 +10:00
fpu_helper.c
target/riscv: zfh: half-precision floating-point classify
2021-12-20 14:51:36 +10:00
gdbstub.c
target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
2021-10-22 07:47:51 +10:00
helper.h
target/riscv: rvv-1.0: register gather instructions
2021-12-20 14:51:36 +10:00
insn16.decode
target/riscv: Consolidate RV32/64 16-bit instructions
2021-05-11 20:02:07 +10:00
insn32.decode
target/riscv: rvv-1.0: whole register move instructions
2021-12-20 14:51:36 +10:00
instmap.h
target/riscv: progressively load the instruction during decode
2020-02-25 20:20:23 +00:00
internals.h
target/riscv: rvv-1.0: floating-point scalar move instructions
2021-12-20 14:51:36 +10:00
Kconfig
meson: Introduce target-specific Kconfig
2021-07-09 18:21:34 +02:00
machine.c
target/riscv: machine: Sort the .subsections
2021-11-17 19:18:22 +10:00
meson.build
target/riscv: rvb: generalized reverse
2021-06-08 09:59:45 +10:00
monitor.c
target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
2021-10-22 07:47:51 +10:00
op_helper.c
target/riscv: Reorg csr instructions
2021-09-01 11:59:12 +10:00
pmp.c
target/riscv: pmp: Fix some typos
2021-07-15 08:56:00 +10:00
pmp.h
target/riscv: Add ePMP CSR access functions
2021-05-11 20:02:06 +10:00
trace-events
target/riscv: Add ePMP CSR access functions
2021-05-11 20:02:06 +10:00
trace.h
trace: switch position of headers to what Meson requires
2020-08-21 06:18:24 -04:00
translate.c
target/riscv: rvv-1.0: add fractional LMUL
2021-12-20 14:51:36 +10:00
vector_helper.c
target/riscv: rvv-1.0: register gather instructions
2021-12-20 14:51:36 +10:00