Frédéric Pétrot 76a361066f target/riscv: moving some insns close to similar insns ... lwu and ld are functionally close to the other loads, but were after the stores in the source file. Similarly, xor was away from or and and by two arithmetic functions, while the immediate versions were nicely put together. This patch moves the aforementioned loads after lhu, and xor above or, where they more logically belong. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-9-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2022-01-08 15:46:10 +10:00
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insn_trans	target/riscv: moving some insns close to similar insns	2022-01-08 15:46:10 +10:00
Kconfig	meson: Introduce target-specific Kconfig	2021-07-09 18:21:34 +02:00
arch_dump.c	target-riscv: support QMP dump-guest-memory	2021-03-04 09:43:29 -05:00
bitmanip_helper.c	target/riscv: Add rev8 instruction, removing grev/grevi	2021-10-07 08:41:33 +10:00
cpu-param.h	target/riscv: Add a virtualised MMU Mode	2020-11-09 15:08:45 -08:00
cpu.c	target/riscv: setup everything for rv64 to support rv128 execution	2022-01-08 15:46:10 +10:00
cpu.h	target/riscv: setup everything for rv64 to support rv128 execution	2022-01-08 15:46:10 +10:00
cpu_bits.h	target/riscv: rvv-1.0: add vlenb register	2021-12-20 14:51:36 +10:00
cpu_helper.c	target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation	2021-12-20 14:51:36 +10:00
cpu_user.h	Supply missing header guards	2019-06-12 13:20:21 +02:00
csr.c	target/riscv: rvv-1.0: implement vstart CSR	2021-12-20 14:53:31 +10:00
fpu_helper.c	target/riscv: add "set round to odd" rounding mode helper function	2021-12-20 14:53:31 +10:00
gdbstub.c	target/riscv: setup everything for rv64 to support rv128 execution	2022-01-08 15:46:10 +10:00
helper.h	target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm	2021-12-20 14:53:31 +10:00
insn16.decode	target/riscv: Consolidate RV32/64 16-bit instructions	2021-05-11 20:02:07 +10:00
insn32.decode	target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm	2021-12-20 14:53:31 +10:00
instmap.h	target/riscv: progressively load the instruction during decode	2020-02-25 20:20:23 +00:00
internals.h	target/riscv: add "set round to odd" rounding mode helper function	2021-12-20 14:53:31 +10:00
machine.c	target/riscv: array for the 64 upper bits of 128-bit registers	2022-01-08 15:46:10 +10:00
meson.build	target/riscv: rvb: generalized reverse	2021-06-08 09:59:45 +10:00
monitor.c	target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl	2021-10-22 07:47:51 +10:00
op_helper.c	target/riscv/pmp: fix no pmp illegal intrs	2022-01-08 15:46:09 +10:00
pmp.c	target/riscv: pmp: Fix some typos	2021-07-15 08:56:00 +10:00
pmp.h	target/riscv: Add ePMP CSR access functions	2021-05-11 20:02:06 +10:00
trace-events	target/riscv: Add ePMP CSR access functions	2021-05-11 20:02:06 +10:00
trace.h	trace: switch position of headers to what Meson requires	2020-08-21 06:18:24 -04:00
translate.c	target/riscv: array for the 64 upper bits of 128-bit registers	2022-01-08 15:46:10 +10:00
vector_helper.c	target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm	2021-12-20 14:53:31 +10:00