Richard Henderson 7dbfafc157 target/arm: Implement REVD
This is an SVE instruction that operates using the SVE vector
length but that it is present only if SME is implemented.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-30-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11 13:43:51 +01:00
..
2022-07-11 13:43:51 +01:00
2022-06-08 19:38:47 +01:00
2022-05-15 16:56:27 -07:00