OpenE2K/qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity
8b045ff454
qemu-e2k/target/riscv
History
Max Chou 8b045ff454 target/riscv: Add Zvksed ISA extension support 
This commit adds support for the Zvksed vector-crypto extension, which
consists of the following instructions:

* vsm4k.vi
* vsm4r.[vv,vs]

Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
[lawrence.hunter@codethink.co.uk: Moved SM4 functions from
crypto_helper.c to vcrypto_helper.c]
[nazar.kazakov@codethink.co.uk: Added alignment checks, refactored code to
use macros, and minor style changes]
Signed-off-by: Max Chou <max.chou@sifive.com>
Message-ID: <20230711165917.2629866-16-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-09-11 11:45:55 +10:00
..
insn_trans target/riscv: Add Zvksed ISA extension support 2023-09-11 11:45:55 +10:00
arch_dump.c
bitmanip_helper.c
common-semi-target.h
cpu_bits.h riscv: spelling fixes 2023-09-08 13:08:52 +03:00
cpu_cfg.h target/riscv: Add Zvksed ISA extension support 2023-09-11 11:45:55 +10:00
cpu_helper.c target/riscv: Set the correct exception for implict G-stage translation fail 2023-07-10 22:29:15 +10:00
cpu_user.h
cpu_vendorid.h
cpu-param.h
cpu-qom.h
cpu.c target/riscv: Add Zvksed ISA extension support 2023-09-11 11:45:55 +10:00
cpu.h riscv: spelling fixes 2023-09-08 13:08:52 +03:00
crypto_helper.c target/riscv: Use existing lookup tables for MixColumns 2023-09-11 11:45:54 +10:00
csr.c riscv: spelling fixes 2023-09-08 13:08:52 +03:00
debug.c riscv: spelling fixes 2023-09-08 13:08:52 +03:00
debug.h
fpu_helper.c riscv: Add support for the Zfa extension 2023-07-10 22:29:20 +10:00
gdbstub.c
helper.h target/riscv: Add Zvksed ISA extension support 2023-09-11 11:45:55 +10:00
insn16.decode
insn32.decode target/riscv: Add Zvksed ISA extension support 2023-09-11 11:45:55 +10:00
instmap.h
internals.h
Kconfig
kvm_riscv.h target/riscv: use KVM scratch CPUs to init KVM properties 2023-07-10 22:29:15 +10:00
kvm-stub.c
kvm.c kvm: Introduce kvm_arch_get_default_type hook 2023-08-22 17:31:02 +01:00
m128_helper.c target/helpers: Remove unnecessary 'qemu/main-loop.h' header 2023-08-31 19:47:43 +02:00
machine.c
meson.build target/riscv: Add Zvbc ISA extension support 2023-09-11 11:45:55 +10:00
monitor.c riscv: spelling fixes 2023-09-08 13:08:52 +03:00
op_helper.c target/helpers: Remove unnecessary 'qemu/main-loop.h' header 2023-08-31 19:47:43 +02:00
pmp.c
pmp.h
pmu.c target/riscv/pmu: Restrict 'qemu/log.h' include to source 2023-08-31 19:47:43 +02:00
pmu.h target/helpers: Remove unnecessary 'qemu/main-loop.h' header 2023-08-31 19:47:43 +02:00
riscv-qmp-cmds.c
sbi_ecall_interface.h
time_helper.c
time_helper.h
trace-events
trace.h
translate.c target/riscv: Add Zvbc ISA extension support 2023-09-11 11:45:55 +10:00
vcrypto_helper.c target/riscv: Add Zvksed ISA extension support 2023-09-11 11:45:55 +10:00
vector_helper.c target/riscv: Refactor some of the generic vector functionality 2023-09-11 11:45:55 +10:00
vector_internals.c target/riscv: Refactor some of the generic vector functionality 2023-09-11 11:45:54 +10:00
vector_internals.h target/riscv: Refactor some of the generic vector functionality 2023-09-11 11:45:55 +10:00
xthead.decode
XVentanaCondOps.decode
zce_helper.c