Richard Henderson 8d6a00cdc0 target/riscv: Hoist pbmte and hade out of the level loop ... These values are constant for every level of pte lookup. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230325105429.1142530-20-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-20-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2023-05-05 10:49:50 +10:00
..
insn_trans	target/riscv: Handle HLV, HSV via helpers	2023-05-05 10:49:50 +10:00
arch_dump.c	target/riscv: Fix format for comments	2023-05-05 10:49:50 +10:00
bitmanip_helper.c
common-semi-target.h
cpu_bits.h	target/riscv: Add a general status enum for extensions	2023-05-05 10:49:50 +10:00
cpu_helper.c	target/riscv: Hoist pbmte and hade out of the level loop	2023-05-05 10:49:50 +10:00
cpu_user.h
cpu_vendorid.h
cpu-param.h	target/riscv: Remove NB_MMU_MODES define	2023-03-13 06:44:37 -07:00
cpu.c	target/riscv: Add a general status enum for extensions	2023-05-05 10:49:50 +10:00
cpu.h	target/riscv: Introduce mmuidx_2stage	2023-05-05 10:49:50 +10:00
crypto_helper.c
csr.c	target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index	2023-05-05 10:49:50 +10:00
debug.c	target/riscv: Fix lines with over 80 characters	2023-05-05 10:49:50 +10:00
debug.h
fpu_helper.c	target/riscv: Fix format for indentation	2023-05-05 10:49:50 +10:00
gdbstub.c	target/riscv: Use PRV_RESERVED instead of PRV_H	2023-05-05 10:49:50 +10:00
helper.h	target/riscv: Handle HLV, HSV via helpers	2023-05-05 10:49:50 +10:00
insn16.decode	target/riscv: add support for Zcmt extension	2023-05-05 10:49:50 +10:00
insn32.decode	target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholder	2023-03-05 11:49:43 -08:00
instmap.h
internals.h	target/riscv: Introduce mmuidx_2stage	2023-05-05 10:49:50 +10:00
Kconfig
kvm_riscv.h
kvm-stub.c
kvm.c
m128_helper.c	target/riscv: Fix format for indentation	2023-05-05 10:49:50 +10:00
machine.c	target/riscv: Fix format for indentation	2023-05-05 10:49:50 +10:00
meson.build	target/riscv: add support for Zcmt extension	2023-05-05 10:49:50 +10:00
monitor.c	target/riscv: remove RISCV_FEATURE_MMU	2023-03-01 13:47:15 -08:00
op_helper.c	target/riscv: Check SUM in the correct register	2023-05-05 10:49:50 +10:00
pmp.c	target/riscv: Fix lines with over 80 characters	2023-05-05 10:49:50 +10:00
pmp.h	target/riscv: Fix format for indentation	2023-05-05 10:49:50 +10:00
pmu.c	target/riscv: Fix lines with over 80 characters	2023-05-05 10:49:50 +10:00
pmu.h
sbi_ecall_interface.h	target/riscv: Fix format for comments	2023-05-05 10:49:50 +10:00
time_helper.c	target/riscv: Simplify type conversion for CPURISCVState	2023-05-05 10:49:49 +10:00
time_helper.h	target/riscv: Simplify type conversion for CPURISCVState	2023-05-05 10:49:49 +10:00
trace-events
trace.h
translate.c	target/riscv: Handle HLV, HSV via helpers	2023-05-05 10:49:50 +10:00
vector_helper.c	target/riscv: Fix lines with over 80 characters	2023-05-05 10:49:50 +10:00
xthead.decode
XVentanaCondOps.decode
zce_helper.c	target/riscv: add support for Zcmt extension	2023-05-05 10:49:50 +10:00