OpenE2K/qemu-e2k
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qemu-e2k/hw/intc
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Cédric Le Goater b68147b7a5 ppc/xive: Add support for the PC MMIOs 
The XIVE interrupt contoller maintains various fields on interrupt
targets in a structure called NVT. Each unit has a NVT cache, backed
by RAM.

When the NVT structure is not local (in RAM) to the chip, the XIVE
interrupt controller forwards the memory operation to the owning chip
using the PC MMIO region configured for this purpose. QEMU does not
need to be so precise since software shouldn't perform any of these
operations. The model implementation is simplified to return the RAM
address of the NVT structure which is then used by pnv_xive_vst_write
or read to perform the operation in RAM.

Remove the last use of pnv_xive_get_remote().

Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-09-06 11:19:33 +02:00
..
allwinner-a10-pic.c hw/intc/allwinner-a10-pic: Handle IRQ levels other than 0 or 1 2023-06-19 11:24:21 +01:00
apic_common.c accel: Remove HAX accelerator 2023-08-31 19:46:43 +02:00
apic.c apic: disable reentrancy detection for apic-msi 2023-04-28 11:31:54 +02:00
arm_gic_common.c hw/intc/arm_gic: Rename 'first_cpu' argument 2023-06-28 14:27:59 +02:00
arm_gic_kvm.c hw/intc: Convert TYPE_ARM_GIC_KVM to 3-phase reset 2022-12-15 11:18:20 +00:00
arm_gic.c arm: spelling fixes 2023-07-25 17:13:53 +03:00
arm_gicv2m.c
arm_gicv3_common.c hw/intc/arm_gic: Un-inline GIC*/ITS class_name() helpers 2023-06-28 14:27:59 +02:00
arm_gicv3_cpuif_common.c
arm_gicv3_cpuif.c target/arm: Mark up sysregs for HFGRTR bits 36..63 2023-02-03 12:59:23 +00:00
arm_gicv3_dist.c bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plx 2023-01-18 11:14:34 +01:00
arm_gicv3_its_common.c hw/intc/arm_gic: Un-inline GIC*/ITS class_name() helpers 2023-06-28 14:27:59 +02:00
arm_gicv3_its_kvm.c hw/intc: Convert TYPE_KVM_ARM_ITS to 3-phase reset 2022-12-15 11:18:20 +00:00
arm_gicv3_its.c bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plx 2023-01-18 11:14:34 +01:00
arm_gicv3_kvm.c hw/intc: Convert TYPE_KVM_ARM_GICV3 to 3-phase reset 2022-12-15 11:18:20 +00:00
arm_gicv3_redist.c arm: spelling fixes 2023-07-25 17:13:53 +03:00
arm_gicv3.c
armv7m_nvic.c arm: spelling fixes 2023-07-25 17:13:53 +03:00
aspeed_vic.c
bcm2835_ic.c
bcm2836_control.c
etraxfs_pic.c
exynos4210_combiner.c bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plx 2023-01-18 11:14:34 +01:00
exynos4210_gic.c
gic_internal.h
gicv3_internal.h
goldfish_pic.c
grlib_irqmp.c
heathrow_pic.c hw/ppc/mac.h: Rename to include/hw/nvram/mac_nvram.h 2022-10-31 18:48:23 +00:00
i8259_common.c hw/intc/i8259: Implement legacy LTIM Edge/Level Bank Select 2023-03-08 00:37:48 +01:00
i8259.c hw/intc/i8259: Implement legacy LTIM Edge/Level Bank Select 2023-03-08 00:37:48 +01:00
imx_avic.c
imx_gpcv2.c
intc.c
ioapic_common.c hw: Move ioapic*.h to intc/ 2023-02-27 22:29:01 +01:00
ioapic_internal.h hw: Move ioapic*.h to intc/ 2023-02-27 22:29:01 +01:00
ioapic.c hw/intc/ioapic: Update KVM routes before redelivering IRQ, on RTE update 2023-03-15 11:52:25 +01:00
Kconfig s390x: Fix QEMU abort by selecting S390_FLIC_KVM 2023-07-18 09:36:27 +02:00
kvm_irqcount.c hw/intc: Extract the IRQ counting functions into a separate file 2023-01-13 16:22:57 +01:00
loongarch_extioi.c bulk: Remove pointless QOM casts 2023-06-05 20:48:34 +02:00
loongarch_ipi.c hw/intc: Set physical cpuid route for LoongArch ipi device 2023-06-16 17:58:46 +08:00
loongarch_pch_msi.c hw/intc/loongarch_pch_msi: add irq number property 2023-01-06 10:54:20 +08:00
loongarch_pch_pic.c hw/intc/loongarch_pch: fix edge triggered irq handling 2023-08-24 11:17:59 +08:00
loongson_liointc.c
m68k_irqc.c
meson.build meson: Replace softmmu_ss -> system_ss 2023-06-20 10:01:30 +02:00
mips_gic.c hw/mips: Declare all length properties as unsigned 2023-03-08 00:37:48 +01:00
nios2_vic.c
omap_intc.c hw/intc/omap_intc: Use CamelCase for TYPE_OMAP_INTC type name 2023-01-12 17:15:09 +00:00
ompic.c
openpic_kvm.c
openpic.c hw/ppc/mac.h: Rename to include/hw/nvram/mac_nvram.h 2022-10-31 18:48:23 +00:00
pl190.c
pnv_xive2_regs.h pnv/xive2: Add definition for the ESB cache configuration register 2023-06-10 10:19:24 -03:00
pnv_xive2.c ppc/xive: Use address_space routines to access the machine RAM 2023-09-06 11:19:33 +02:00
pnv_xive_regs.h ppc/xive: Handle END triggers between chips with MMIOs 2023-09-06 11:19:33 +02:00
pnv_xive.c ppc/xive: Add support for the PC MMIOs 2023-09-06 11:19:33 +02:00
ppc-uic.c hw/intc/ppc-uic: Convert ppc-uic to a PPC4xx DCR device 2022-08-31 14:08:06 -03:00
realview_gic.c
riscv_aclint.c hw: intc: Use cpu_by_arch_id to fetch CPU state 2023-03-05 15:33:40 -08:00
riscv_aplic.c hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only. 2023-06-14 10:04:30 +10:00
riscv_imsic.c hw: intc: Use cpu_by_arch_id to fetch CPU state 2023-03-05 15:33:40 -08:00
rx_icu.c
s390_flic_kvm.c s390x: spelling fixes 2023-07-25 17:13:45 +03:00
s390_flic.c
sh_intc.c
sifive_plic.c hw/intc: sifive_plic: Fix the pending register range check 2023-01-06 10:42:55 +10:00
slavio_intctl.c
spapr_xive_kvm.c
spapr_xive.c pnv/xive2: Add a get_config() method on the presenter class 2023-06-25 22:41:30 +02:00
trace-events pnv/xive: Print CPU target in all TIMA traces 2023-07-07 04:46:12 -03:00
trace.h
vgic_common.h
xics_kvm.c
xics_pnv.c
xics_spapr.c
xics.c hw/intc/xics: Convert TYPE_ICS to 3-phase reset 2022-12-16 15:59:07 +00:00
xilinx_intc.c hw/intc/xilinx_intc: Use 'XpsIntc' typedef instead of 'struct xlx_pic' 2023-01-12 17:15:09 +00:00
xive2.c pnv/xive: Allow mmio operations of any size on the ESB CI pages 2023-07-07 04:46:12 -03:00
xive.c ppc/xive: Introduce a new XiveRouter end_notify() handler 2023-09-06 11:19:33 +02:00
xlnx-pmu-iomod-intc.c
xlnx-zynqmp-ipi.c