qemu-e2k/target/riscv
Vineet Gupta 0643c12e4b target/riscv: Enable bitmanip Zb[abcs] instructions
The bitmanip extension has now been ratified [1] and upstream tooling
(gcc/binutils) support it too, so move them out of experimental and also
enable by default (for better test exposure/coverage)

[1] https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions

Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211216051844.3921088-1-vineetg@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20 14:53:31 +10:00
..
insn_trans target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions 2021-12-20 14:53:31 +10:00
Kconfig meson: Introduce target-specific Kconfig 2021-07-09 18:21:34 +02:00
arch_dump.c target-riscv: support QMP dump-guest-memory 2021-03-04 09:43:29 -05:00
bitmanip_helper.c target/riscv: Add rev8 instruction, removing grev/grevi 2021-10-07 08:41:33 +10:00
cpu-param.h target/riscv: Add a virtualised MMU Mode 2020-11-09 15:08:45 -08:00
cpu.c target/riscv: Enable bitmanip Zb[abcs] instructions 2021-12-20 14:53:31 +10:00
cpu.h target/riscv: gdb: support vector registers for rv64 & rv32 2021-12-20 14:53:31 +10:00
cpu_bits.h target/riscv: rvv-1.0: add vlenb register 2021-12-20 14:51:36 +10:00
cpu_helper.c target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation 2021-12-20 14:51:36 +10:00
cpu_user.h Supply missing header guards 2019-06-12 13:20:21 +02:00
csr.c target/riscv: rvv-1.0: implement vstart CSR 2021-12-20 14:53:31 +10:00
fpu_helper.c target/riscv: add "set round to odd" rounding mode helper function 2021-12-20 14:53:31 +10:00
gdbstub.c target/riscv: gdb: support vector registers for rv64 & rv32 2021-12-20 14:53:31 +10:00
helper.h target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm 2021-12-20 14:53:31 +10:00
insn16.decode target/riscv: Consolidate RV32/64 16-bit instructions 2021-05-11 20:02:07 +10:00
insn32.decode target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm 2021-12-20 14:53:31 +10:00
instmap.h target/riscv: progressively load the instruction during decode 2020-02-25 20:20:23 +00:00
internals.h target/riscv: add "set round to odd" rounding mode helper function 2021-12-20 14:53:31 +10:00
machine.c target/riscv: machine: Sort the .subsections 2021-11-17 19:18:22 +10:00
meson.build target/riscv: rvb: generalized reverse 2021-06-08 09:59:45 +10:00
monitor.c target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl 2021-10-22 07:47:51 +10:00
op_helper.c target/riscv: Reorg csr instructions 2021-09-01 11:59:12 +10:00
pmp.c target/riscv: pmp: Fix some typos 2021-07-15 08:56:00 +10:00
pmp.h target/riscv: Add ePMP CSR access functions 2021-05-11 20:02:06 +10:00
trace-events target/riscv: Add ePMP CSR access functions 2021-05-11 20:02:06 +10:00
trace.h trace: switch position of headers to what Meson requires 2020-08-21 06:18:24 -04:00
translate.c target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions 2021-12-20 14:53:31 +10:00
vector_helper.c target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm 2021-12-20 14:53:31 +10:00