qemu-e2k/target-mips
James Hogan 240ce26a05 target-mips: fix branch in likely delay slot tcg assert
When a branch delay slot contains another branch instruction, the code
generated raises an exception, however since is_branch==1,
handle_delay_slot() doesn't get called immediately. This means
ctx->bstate isn't set to BS_BRANCH, and the decoder continues decoding
until a non-branch instruction is found.

If the first branch was a branch likely instruction then each
instruction after it generates code for the unlikely case, to go to the
next tb starting after the delay slot. This results in multiple goto_tb
tcg ops being generated with the same exit number. When debug is enabled
this hits:

tcg-op.h:2589: tcg_gen_goto_tb: Assertion `(tcg_ctx.goto_tb_issue_mask & (1 << idx)) == 0' failed.

This is fixed by removing is_branch entirely, and calling
handle_delay_slot() if (ctx.hflags & MIPS_HFLAG_BMASK) was set prior to
the current instruction being decoded. This still prevents
handle_delay_slot() being called immediately after a branch but allows
it to still be called after a branch within a delay slot.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-07-28 18:33:44 +02:00
..
Makefile.objs cpu: Introduce CPUClass::gdb_{read,write}_register() 2013-07-27 00:04:17 +02:00
TODO target-mips: Change TODO file 2012-10-31 21:37:24 +01:00
cpu-qom.h cpu: Introduce CPUClass::gdb_{read,write}_register() 2013-07-27 00:04:17 +02:00
cpu.c cpu: Introduce CPUClass::gdb_{read,write}_register() 2013-07-27 00:04:17 +02:00
cpu.h cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb() 2013-07-23 02:41:32 +02:00
dsp_helper.c target-mips: fix multiplication in mipsdsp_rndq15_mul_q15_q15 2013-07-28 18:26:36 +02:00
gdbstub.c cpu: Introduce CPUClass::gdb_{read,write}_register() 2013-07-27 00:04:17 +02:00
helper.c cpu: Turn cpu_get_phys_page_debug() into a CPUClass hook 2013-07-23 02:41:33 +02:00
helper.h target-mips: Use mul[us]2 in [D]MULT[U] insns 2013-02-23 17:25:29 +00:00
lmi_helper.c target-mips: Implement Loongson Multimedia Instructions 2012-09-19 21:40:48 +02:00
machine.c target-mips: Don't overuse CPUState 2012-03-14 22:20:25 +01:00
mips-defs.h MIPS: Initial support of fulong mini pc (CPU definition) 2010-06-29 23:07:52 +02:00
op_helper.c cpu: Make first_cpu and next_cpu CPUState 2013-07-09 21:32:54 +02:00
translate.c target-mips: fix branch in likely delay slot tcg assert 2013-07-28 18:33:44 +02:00
translate_init.c target-mips: Add ASE DSP processors 2012-10-31 21:37:20 +01:00