qemu-e2k/target/arm
Zhuojia Shen bc6bd20ee3 target/arm: align exposed ID registers with Linux
In CPUID registers exposed to userspace, some registers were missing
and some fields were not exposed.  This patch aligns exposed ID
registers and their fields with what the upstream kernel currently
exposes.

Specifically, the following new ID registers/fields are exposed to
userspace:

ID_AA64PFR1_EL1.BT:       bits 3-0
ID_AA64PFR1_EL1.MTE:      bits 11-8
ID_AA64PFR1_EL1.SME:      bits 27-24

ID_AA64ZFR0_EL1.SVEver:   bits 3-0
ID_AA64ZFR0_EL1.AES:      bits 7-4
ID_AA64ZFR0_EL1.BitPerm:  bits 19-16
ID_AA64ZFR0_EL1.BF16:     bits 23-20
ID_AA64ZFR0_EL1.SHA3:     bits 35-32
ID_AA64ZFR0_EL1.SM4:      bits 43-40
ID_AA64ZFR0_EL1.I8MM:     bits 47-44
ID_AA64ZFR0_EL1.F32MM:    bits 55-52
ID_AA64ZFR0_EL1.F64MM:    bits 59-56

ID_AA64SMFR0_EL1.F32F32:  bit 32
ID_AA64SMFR0_EL1.B16F32:  bit 34
ID_AA64SMFR0_EL1.F16F32:  bit 35
ID_AA64SMFR0_EL1.I8I32:   bits 39-36
ID_AA64SMFR0_EL1.F64F64:  bit 48
ID_AA64SMFR0_EL1.I16I64:  bits 55-52
ID_AA64SMFR0_EL1.FA64:    bit 63

ID_AA64MMFR0_EL1.ECV:     bits 63-60

ID_AA64MMFR1_EL1.AFP:     bits 47-44

ID_AA64MMFR2_EL1.AT:      bits 35-32

ID_AA64ISAR0_EL1.RNDR:    bits 63-60

ID_AA64ISAR1_EL1.FRINTTS: bits 35-32
ID_AA64ISAR1_EL1.BF16:    bits 47-44
ID_AA64ISAR1_EL1.DGH:     bits 51-48
ID_AA64ISAR1_EL1.I8MM:    bits 55-52

ID_AA64ISAR2_EL1.WFxT:    bits 3-0
ID_AA64ISAR2_EL1.RPRES:   bits 7-4
ID_AA64ISAR2_EL1.GPA3:    bits 11-8
ID_AA64ISAR2_EL1.APA3:    bits 15-12

The code is also refactored to use symbolic names for ID register fields
for better readability and maintainability.

The test case in tests/tcg/aarch64/sysregs.c is also updated to match
the intended behavior.

Signed-off-by: Zhuojia Shen <chaosdefinition@hotmail.com>
Message-id: DS7PR12MB6309FB585E10772928F14271ACE79@DS7PR12MB6309.namprd12.prod.outlook.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: use Sn_n_Cn_Cn_n syntax to work with older assemblers
that don't recognize id_aa64isar2_el1 and id_aa64mmfr2_el1]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05 14:12:34 +00:00
..
hvf
a32-uncond.decode
a32.decode
arch_dump.c dump: Replace opaque DumpState pointer with a typed one 2022-10-06 19:30:43 +04:00
arm_ldst.h
arm-powerctl.c
arm-powerctl.h
common-semi-target.h
cpregs.h
cpu64.c target/arm: cleanup cpu includes 2023-01-05 12:28:37 +00:00
cpu_tcg.c target/arm: Add ARM Cortex-R52 CPU 2023-01-05 11:51:09 +00:00
cpu-param.h target/arm: Enable TARGET_TB_PCREL 2022-10-20 11:28:29 +01:00
cpu-qom.h target/arm: Convert to 3-phase reset 2022-12-16 15:58:15 +00:00
cpu.c target/arm: cleanup cpu includes 2023-01-05 12:28:37 +00:00
cpu.h target/arm: Add PMSAv8r registers 2023-01-05 11:51:09 +00:00
crypto_helper.c
debug_helper.c target/arm: Enable TTBCR_EAE for ARMv8-R AArch32 2023-01-05 11:51:09 +00:00
gdbstub64.c
gdbstub.c
helper-a64.c
helper-a64.h
helper-mve.h
helper-sme.h
helper-sve.h
helper.c target/arm: align exposed ID registers with Linux 2023-01-05 14:12:34 +00:00
helper.h
hvf_arm.h
idau.h
internals.h target/arm: Enable TTBCR_EAE for ARMv8-R AArch32 2023-01-05 11:51:09 +00:00
iwmmxt_helper.c
Kconfig
kvm64.c
kvm_arm.h
kvm-consts.h hw/misc: Move some arm-related files from specific_ss into softmmu_ss 2022-12-15 17:37:47 +00:00
kvm-stub.c
kvm.c * scsi-disk: support setting CD-ROM block size via device options 2022-10-13 13:55:03 -04:00
m_helper.c target/arm: Remove unused includes from m_helper.c 2023-01-05 12:28:37 +00:00
m-nocp.decode
machine.c target/arm: Add PMSAv8r registers 2023-01-05 11:51:09 +00:00
meson.build
monitor.c qapi machine: Elide redundant has_FOO in generated C 2022-12-14 20:04:47 +01:00
mte_helper.c accel/tcg: Simplify page_get/alloc_target_data 2022-10-26 11:11:28 +10:00
mve_helper.c
mve.decode
neon_helper.c
neon-dp.decode
neon-ls.decode
neon-shared.decode
op_addsub.h
op_helper.c accel/tcg: Remove will_exit argument from cpu_restore_state 2022-11-01 08:31:41 +11:00
pauth_helper.c
psci.c
ptw.c target/arm: Add PMSAv8r functionality 2023-01-05 11:51:09 +00:00
sme_helper.c
sme-fa64.decode
sme.decode
sve_helper.c target/arm: Copy the entire vector in DO_ZIP 2022-11-04 10:58:58 +00:00
sve_ldst_internal.h target/arm: Use probe_access_full for MTE 2022-10-20 11:27:49 +01:00
sve.decode
syndrome.h
t16.decode
t32.decode
tlb_helper.c target/arm: Enable TTBCR_EAE for ARMv8-R AArch32 2023-01-05 11:51:09 +00:00
trace-events
trace.h
translate-a32.h target/arm: Change gen_*set_pc_im to gen_*update_pc 2022-10-20 11:27:52 +01:00
translate-a64.c target/arm: Enable TARGET_TB_PCREL 2022-10-20 11:28:29 +01:00
translate-a64.h
translate-m-nocp.c target/arm: Enable TARGET_TB_PCREL 2022-10-20 11:28:29 +01:00
translate-mve.c target/arm: Change gen_exception_insn* to work on displacements 2022-10-20 11:27:52 +01:00
translate-neon.c
translate-sme.c
translate-sve.c
translate-vfp.c target/arm: Change gen_exception_insn* to work on displacements 2022-10-20 11:27:52 +01:00
translate.c target/arm: fix handling of HLT semihosting in system mode 2023-01-05 11:53:14 +00:00
translate.h target/arm: Enable TARGET_TB_PCREL 2022-10-20 11:28:29 +01:00
vec_helper.c
vec_internal.h
vfp_helper.c
vfp-uncond.decode
vfp.decode