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qemu-e2k/target/riscv
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Daniel Henrique Barboza b933720be2 target/riscv: add riscv_cpu_get_name() 
We'll introduce generic errors that will output a CPU type name via its
RISCVCPU pointer. Create a helper for that.

Use the helper in tcg_cpu_realizefn() instead of hardcoding the 'host'
CPU name.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230926183109.165878-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-10-12 12:30:16 +10:00
..
insn_trans
tcg: Rename cpu_env to tcg_env
2023-10-03 08:01:02 -07:00
kvm
target/riscv/kvm: do not use riscv_cpu_add_misa_properties()
2023-10-12 12:21:37 +10:00
tcg
target/riscv: add riscv_cpu_get_name()
2023-10-12 12:30:16 +10:00
arch_dump.c
…
bitmanip_helper.c
…
common-semi-target.h
…
cpu_bits.h
target/riscv: Update CSR bits name for svadu extension
2023-09-11 11:45:55 +10:00
cpu_cfg.h
target/riscv: Add Zihintntl extension ISA string to DTS
2023-09-11 11:45:55 +10:00
cpu_helper.c
target/riscv: Update CSR bits name for svadu extension
2023-09-11 11:45:55 +10:00
cpu_user.h
…
cpu_vendorid.h
target/riscv: add Ventana's Veyron V1 CPU
2023-05-05 10:49:50 +10:00
cpu-param.h
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cpu-qom.h
target/riscv: add 'max' CPU type
2023-10-12 11:39:33 +10:00
cpu.c
target/riscv: add riscv_cpu_get_name()
2023-10-12 12:30:16 +10:00
cpu.h
target/riscv: add riscv_cpu_get_name()
2023-10-12 12:30:16 +10:00
crypto_helper.c
target/riscv: Use accelerated helper for AES64KS1I
2023-09-11 11:45:55 +10:00
csr.c
target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c
2023-10-12 11:57:46 +10:00
debug.c
target/riscv: Allocate itrigger timers only once
2023-09-11 11:45:55 +10:00
debug.h
target/riscv: Allocate itrigger timers only once
2023-09-11 11:45:55 +10:00
fpu_helper.c
riscv: Add support for the Zfa extension
2023-07-10 22:29:20 +10:00
gdbstub.c
…
helper.h
target/riscv: Add Zvksed ISA extension support
2023-09-11 11:45:55 +10:00
insn16.decode
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insn32.decode
target/riscv: Add Zvksed ISA extension support
2023-09-11 11:45:55 +10:00
instmap.h
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internals.h
…
Kconfig
…
m128_helper.c
target/helpers: Remove unnecessary 'qemu/main-loop.h' header
2023-08-31 19:47:43 +02:00
machine.c
target/riscv: Restrict KVM-specific fields from ArchCPU
2023-06-28 14:27:59 +02:00
meson.build
target/riscv: move KVM only files to kvm subdir
2023-10-12 12:20:24 +10:00
monitor.c
riscv: spelling fixes
2023-09-08 13:08:52 +03:00
op_helper.c
target/helpers: Remove unnecessary 'qemu/main-loop.h' header
2023-08-31 19:47:43 +02:00
pmp.c
target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes
2023-09-11 11:45:55 +10:00
pmp.h
target/riscv: Change the return type of pmp_hart_has_privs() to bool
2023-06-13 17:09:13 +10:00
pmu.c
target/riscv/pmu: Restrict 'qemu/log.h' include to source
2023-08-31 19:47:43 +02:00
pmu.h
target/helpers: Remove unnecessary 'qemu/main-loop.h' header
2023-08-31 19:47:43 +02:00
riscv-qmp-cmds.c
…
sbi_ecall_interface.h
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time_helper.c
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time_helper.h
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trace-events
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trace.h
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translate.c
accel/tcg: Replace CPUState.env_ptr with cpu_env()
2023-10-04 11:03:54 -07:00
vcrypto_helper.c
target/riscv: Add Zvksed ISA extension support
2023-09-11 11:45:55 +10:00
vector_helper.c
tcg: Correct invalid mentions of 'softmmu' by 'system-mode'
2023-10-07 19:02:33 +02:00
vector_internals.c
target/riscv: Refactor some of the generic vector functionality
2023-09-11 11:45:54 +10:00
vector_internals.h
target/riscv: Refactor some of the generic vector functionality
2023-09-11 11:45:55 +10:00
xthead.decode
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XVentanaCondOps.decode
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zce_helper.c
…