Akihiko Odaki eb37086fb0 gdbstub: Add members to identify registers to GDBFeature ... These members will be used to help plugins to identify registers. The added members in instances of GDBFeature dynamically generated by CPUs will be filled in later changes. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20231213-gdb-v17-10-777047380591@daynix.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240227144335.1196131-15-alex.bennee@linaro.org>		2024-02-28 09:10:11 +00:00
..
insn_trans	target/riscv: Enable xtheadsync under user mode	2024-02-09 20:43:14 +10:00
kvm	target/riscv: Move misa_mxl_max to class	2024-02-09 20:43:14 +10:00
tcg	target/riscv: Validate misa_mxl_max only once	2024-02-09 20:43:14 +10:00
arch_dump.c
bitmanip_helper.c
common-semi-target.h
cpu_bits.h	target/riscv: FCSR doesn't contain vxrm and vxsat	2024-02-09 20:43:14 +10:00
cpu_cfg.h	target/riscv: Add Zaamo and Zalrsc extension infrastructure	2024-02-09 20:43:14 +10:00
cpu_helper.c	target/riscv: change vext_get_vlmax() arguments	2024-02-09 20:43:14 +10:00
cpu_user.h
cpu_vendorid.h
cpu-param.h
cpu-qom.h	target/riscv: add rv32i, rv32e and rv64e CPUs	2024-02-09 20:49:41 +10:00
cpu.c	hw/core/cpu: Remove gdb_get_dynamic_xml member	2024-02-28 09:10:06 +00:00
cpu.h	target/riscv: Use GDBFeature for dynamic XML	2024-02-28 09:09:29 +00:00
crypto_helper.c	target/riscv: Use accelerated helper for AES64KS1I	2023-09-11 11:45:55 +10:00
csr.c	target/riscv: Use RISCVException as return type for all csr ops	2024-02-09 20:43:14 +10:00
debug.c	target/riscv: Implement optional CSR mcontext of debug Sdtrig extension	2024-02-09 20:40:32 +10:00
debug.h	target/riscv: Allocate itrigger timers only once	2023-09-11 11:45:55 +10:00
fpu_helper.c
gdbstub.c	gdbstub: Add members to identify registers to GDBFeature	2024-02-28 09:10:11 +00:00
helper.h	target/riscv: Add Zvksed ISA extension support	2023-09-11 11:45:55 +10:00
insn16.decode
insn32.decode	target/riscv: Add support for Zacas extension	2024-01-10 18:47:47 +10:00
instmap.h
internals.h	target/riscv: Use env_archcpu() in [check_]nanbox()	2023-11-07 12:13:27 +01:00
Kconfig	kconfig: use "select" to enable semihosting	2024-02-09 17:52:30 +00:00
m128_helper.c
machine.c	target/riscv: Move misa_mxl_max to class	2024-02-09 20:43:14 +10:00
meson.build	target/riscv: move KVM only files to kvm subdir	2023-10-12 12:20:24 +10:00
monitor.c	riscv: spelling fixes	2023-09-08 13:08:52 +03:00
op_helper.c	target/riscv: Replace cpu_mmu_index with riscv_env_mmu_index	2024-02-03 16:46:10 +10:00
pmp.c	target/riscv: pmp: Ignore writes when RW=01 and MML=0	2024-01-10 18:47:47 +10:00
pmp.h	target/riscv/pmp: Use hwaddr instead of target_ulong for RV32	2024-01-10 18:47:46 +10:00
pmu.c	target/riscv: Add "pmu-mask" property to replace "pmu-num"	2023-11-07 11:06:02 +10:00
pmu.h	target/riscv: Use existing PMU counter mask in FDT generation	2023-11-07 11:06:02 +10:00
riscv-qmp-cmds.c	riscv-qmp-cmds.c: add profile flags in cpu-model-expansion	2024-01-10 18:47:47 +10:00
sbi_ecall_interface.h
time_helper.c
time_helper.h
trace-events
trace.h
translate.c	target/riscv: Move misa_mxl_max to class	2024-02-09 20:43:14 +10:00
vcrypto_helper.c	target/riscv: Add Zvksed ISA extension support	2023-09-11 11:45:55 +10:00
vector_helper.c	target/riscv: change vext_get_vlmax() arguments	2024-02-09 20:43:14 +10:00
vector_internals.c	riscv: Clean up includes	2024-01-30 21:20:20 +03:00
vector_internals.h	riscv: Clean up includes	2024-01-30 21:20:20 +03:00
xthead.decode
XVentanaCondOps.decode
zce_helper.c