qemu-e2k/hw/riscv
Michael Clark 25fa194b7b
RISC-V Build Infrastructure
This adds RISC-V into the build system enabling the following targets:

- riscv32-softmmu
- riscv64-softmmu
- riscv32-linux-user
- riscv64-linux-user

This adds defaults configs for RISC-V, enables the build for the RISC-V
CPU core, hardware, and Linux User Emulation. The 'qemu-binfmt-conf.sh'
script is updated to add the RISC-V ELF magic.

Expected checkpatch errors for consistency reasons:

ERROR: line over 90 characters
FILE: scripts/qemu-binfmt-conf.sh

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu>
Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07 08:30:28 +13:00
..
Makefile.objs RISC-V Build Infrastructure 2018-03-07 08:30:28 +13:00
riscv_hart.c
riscv_htif.c
sifive_clint.c SiFive RISC-V CLINT Block 2018-03-07 08:30:28 +13:00
sifive_e.c SiFive Freedom E Series RISC-V Machine 2018-03-07 08:30:28 +13:00
sifive_plic.c SiFive RISC-V PLIC Block 2018-03-07 08:30:28 +13:00
sifive_prci.c SiFive RISC-V PRCI Block 2018-03-07 08:30:28 +13:00
sifive_test.c SiFive RISC-V Test Finisher 2018-03-07 08:30:28 +13:00
sifive_u.c SiFive Freedom U Series RISC-V Machine 2018-03-07 08:30:28 +13:00
sifive_uart.c SiFive RISC-V UART Device 2018-03-07 08:30:28 +13:00
spike.c RISC-V Spike Machines 2018-03-07 08:30:28 +13:00
virt.c RISC-V VirtIO Machine 2018-03-07 08:30:28 +13:00