20303e42d4
Xtensa cores have configurable interrupt vectors and endiannes. This information is needed to link executable images correctly for a specific core configuration. Instead of hard-coding dc232 defaults pull endianness, number of high-priority interrupts and location of vectors from the core configuration and pass it through the C preprocessor. While at it clean up tabs and align the initial stack on 16 bytes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> |
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| .. | ||
| alpha | ||
| cris | ||
| lm32 | ||
| mips | ||
| openrisc | ||
| xtensa | ||
| hello-arm.c | ||
| hello-i386.c | ||
| hello-mips.c | ||
| linux-test.c | ||
| Makefile | ||
| pi_10.com | ||
| runcom.c | ||
| sha1.c | ||
| test_path.c | ||
| test-arm-iwmmxt.s | ||
| test-i386-code16.S | ||
| test-i386-fprem.c | ||
| test-i386-muldiv.h | ||
| test-i386-shift.h | ||
| test-i386-ssse3.c | ||
| test-i386-vm86.S | ||
| test-i386.c | ||
| test-i386.h | ||
| test-mmap.c | ||
| testthread.c | ||