eac92d3163
* Correctly initialize MDCR_EL2.HPMN * versal: Use nr_apu_cpus in favor of hard coding 2 * accel/tcg: Add URL of clang bug to comment about our workaround * Add support for FEAT_DIT, Data Independent Timing * Remove GPIO from unimplemented NPCM7XX * Fix SCR RES1 handling * Don't migrate CPUARMState.features -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmAli/gZHHBldGVyLm1h eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3jarEACMMPvwnWYxY3m/aDMHmgoV jTjdyutBKSqIDPXPZNIDIonutsaE521MdGjSAsMtoSBN4C30qd4HX3gqEitVGVSF KlF9MWbLMbe6UQUU5NfRfbFKwCazHqNiAffO45677LiJHH9v2q1sAsUW/KTNGpAv PDOSNfpkIUeYfZapv+dIs1rkjEKPHo1/M/KvJGSkIi0DKQeJKjKAB4rP+Fwf+iBu XH0mXrUqO348u+LOl4hhCRzRzZ6FKwv40IqrtB1WBqCmfdASX7MtD4GPh5rwC63C 8gkq1Zb3xUIQA2oCppT8UBq4+D/gBgDjGCg0irC6/SL1+N4ThAZxdz/evCbowLip 27B1ANfxgmQF1tLXYXIWfoyrBt97pHFH6Koh/xdnbiznNNkL8TnuC6mTe+9xCp2m UGolv/7Lgb5mtXwjyHesR/LxQugzC38kUcAzbDw9zIT8C9l19K4/u9UXBlyDZ0WE l9aGRWulk9EtJ05biPSUbuHZROPg0KiupfgbjF2jVwW3ehMNYC/CYHhWLrnt4g8m Dx2+ZioAMUmAgyzmcc6kgLzyoEbUsja5c6JQKTkaxsdJiyvH3hN2msvCH3uEgqVp J6h01HaIE7Fv2WwXNKqbqG4d47I1ryOymCPQ99h2wJzbDIJWV8Tbp3JcqJCDqzp3 Us8I+DB40vE+3WbVQ9lvlw== =3Ptb -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210211-1' into staging target-arm queue: * Correctly initialize MDCR_EL2.HPMN * versal: Use nr_apu_cpus in favor of hard coding 2 * accel/tcg: Add URL of clang bug to comment about our workaround * Add support for FEAT_DIT, Data Independent Timing * Remove GPIO from unimplemented NPCM7XX * Fix SCR RES1 handling * Don't migrate CPUARMState.features # gpg: Signature made Thu 11 Feb 2021 19:56:40 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20210211-1: target/arm: Correctly initialize MDCR_EL2.HPMN hw/arm: versal: Use nr_apu_cpus in favor of hard coding 2 accel/tcg: Add URL of clang bug to comment about our workaround arm: Update infocenter.arm.com URLs target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate target/arm: Add support for FEAT_DIT, Data Independent Timing hw/arm: Remove GPIO from unimplemented NPCM7XX target/arm: Fix SCR RES1 handling target/arm: Don't migrate CPUARMState.features Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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.. | ||
9pfs | ||
acpi | ||
adc | ||
alpha | ||
arm | ||
audio | ||
avr | ||
block | ||
char | ||
core | ||
cpu | ||
cris | ||
display | ||
dma | ||
gpio | ||
hppa | ||
hyperv | ||
i2c | ||
i386 | ||
ide | ||
input | ||
intc | ||
ipack | ||
ipmi | ||
isa | ||
lm32 | ||
m68k | ||
mem | ||
microblaze | ||
mips | ||
misc | ||
moxie | ||
net | ||
nios2 | ||
nubus | ||
nvram | ||
openrisc | ||
pci | ||
pci-bridge | ||
pci-host | ||
pcmcia | ||
ppc | ||
rdma | ||
remote | ||
riscv | ||
rtc | ||
rx | ||
s390x | ||
scsi | ||
sd | ||
semihosting | ||
sh4 | ||
smbios | ||
sparc | ||
sparc64 | ||
ssi | ||
timer | ||
tpm | ||
tricore | ||
unicore32 | ||
usb | ||
vfio | ||
virtio | ||
watchdog | ||
xen | ||
xenpv | ||
xtensa | ||
Kconfig | ||
meson.build |