c96292036a
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABAgAGBQJb0HIuAAoJENSXKoln91plGcUH/3Lje5KF8kkShQ5dIrH9e8Xz bvK6lXOLNnndEyrWqJNLaJs7eJKEV2N+E2sBmdIjKnWXVHW6gOW3QBMuVGPTT4rg C6cntrh2HpnxibgJqrR+3RmjQHAI1Ktixhker9LWimF3ZZhcy4H6mFHwW9z7eBK4 +n/pbnk8fq4FlGHJ2teHhctVIma6slmd8lkMa9vdwVQwpAyzpP82XjrsoTeeYhmG uuTvX3TFnXKGa9mYGxybpwKd4i+397l9fTQ4egx1KlZMR8OHuQItCBDOFdiQpHOg yljCeG3jHEhNzVf+xW7JU692Lz097otWDbzWDJibYGJkdkhKfyHJ9PvCYaPiK6M= =Sg8J -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-oct-2018-part-2-v2' into staging MIPS queue for October 2018 - part 2 - v2 # gpg: Signature made Wed 24 Oct 2018 14:22:54 BST # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-oct-2018-part-2-v2: (33 commits) target/mips: Fix decoding of ALIGN and DALIGN instructions target/mips: Fix the title of translate.c linux-user/mips: Recognize the R5900 CPU model target/mips: Define the R5900 CPU tests/tcg/mips: Add tests for R5900 DIVU1 tests/tcg/mips: Add tests for R5900 DIV1 tests/tcg/mips: Add tests for R5900 MTLO1 and MTHI1 tests/tcg/mips: Add tests for R5900 MFLO1 and MFHI1 tests/tcg/mips: Add tests for R5900 three-operand MULTU1 tests/tcg/mips: Add tests for R5900 three-operand MULT1 tests/tcg/mips: Add tests for R5900 three-operand MULTU tests/tcg/mips: Add tests for R5900 three-operand MULT target/mips: Make R5900 DMULT[U], DDIV[U], LL[D] and SC[D] user only target/mips: Support R5900 MOVN, MOVZ and PREF instructions from MIPS IV target/mips: Support R5900 DIV1 and DIVU1 instructions target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructions target/mips: Support R5900 three-operand MULT1 and MULTU1 instructions target/mips: Support R5900 three-operand MULT and MULTU instructions target/mips: Add a placeholder for R5900 MMI3 instruction subclass target/mips: Add a placeholder for R5900 MMI2 instruction subclass ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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alpha | ||
arm | ||
cris | ||
hppa | ||
i386 | ||
lm32 | ||
m68k | ||
microblaze | ||
mips | ||
moxie | ||
nios2 | ||
openrisc | ||
ppc | ||
riscv | ||
s390x | ||
sh4 | ||
sparc | ||
tilegx | ||
tricore | ||
unicore32 | ||
xtensa |