qemu-e2k/hw/i2c
Peter Delevoryas 1c5d909f88 hw/i2c/aspeed: Add new-registers DMA slave mode RX support
This commit adds support for DMA RX in slave mode while using the new
register set in the AST2600 and AST1030. This patch also pretty much
assumes packet mode is enabled, I'm not sure if this will work in DMA
step mode.

This is particularly useful for testing IPMB exchanges between Zephyr
and external devices, which requires multi-master I2C support and DMA in
the new register mode, because the Zephyr drivers from Aspeed use DMA in
the new mode by default. The Zephyr drivers are also using packet mode.

The typical sequence of events for receiving data in DMA slave + packet
mode is that the Zephyr firmware will configure the slave address
register with an address to receive on and configure the bus's function
control register to enable master mode and slave mode simultaneously at
startup, before any transfers are initiated.

RX DMA is enabled in the slave mode command register, and the slave RX
DMA buffer address and slave RX DMA buffer length are set. TX DMA is not
covered in this patch.

When the Aspeed I2C controller receives data from some other I2C master,
it will reset the I2CS_DMA_LEN RX_LEN value to zero, then buffer
incoming data in the RX DMA buffer while incrementing the I2CC_DMA_ADDR
address counter and decrementing the I2CC_DMA_LEN counter. It will also
update the I2CS_DMA_LEN RX_LEN value along the way.

Once all the data has been received, the bus controller will raise an
interrupt indicating a packet command was completed, the slave address
matched, a normal stop condition was seen, and the transfer was an RX
operation.

If the master sent a NACK instead of a normal stop condition, or the
transfer timed out, then a slightly different set of interrupt status
values would be set. Those conditions are not handled in this commit.

The Zephyr firmware then collects data from the RX DMA buffer and clears
the status register by writing the PKT_MODE_EN bit to the status
register. In packet mode, clearing the packet mode interrupt enable bit
also clears most of the other interrupt bits automatically (except for a
few bits above it).

Note: if the master transmit or receive functions were in use
simultaneously with the slave mode receive functionality, then the
master mode functions may have raised the interrupt line for the bus
before the DMA slave transfer is complete. It's important to have the
slave's interrupt status register clear throughout the receive
operation, and if the slave attempts to raise the interrupt before the
master interrupt status is cleared, then it needs to re-raise the
interrupt once the master interrupt status is cleared. (And vice-versa).
That's why in this commit, when the master interrupt status is cleared
and the interrupt line is lowered, we call the slave interrupt _raise_
function, to see if the interrupt was pending. (And again, vice-versa).

Signed-off-by: Peter Delevoryas <pdel@fb.com>
Message-Id: <20220630045133.32251-8-me@pjd.dev>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-30 09:21:14 +02:00
..
Kconfig Kconfig: Add I2C_DEVICES device group 2022-02-21 13:30:20 +00:00
aspeed_i2c.c hw/i2c/aspeed: Add new-registers DMA slave mode RX support 2022-06-30 09:21:14 +02:00
bitbang_i2c.c Use OBJECT_DECLARE_SIMPLE_TYPE when possible 2020-09-18 14:12:32 -04:00
core.c hw/i2c: add asynchronous send 2022-06-30 09:21:14 +02:00
exynos4210_i2c.c Use OBJECT_DECLARE_SIMPLE_TYPE when possible 2020-09-18 14:12:32 -04:00
i2c_mux_pca954x.c Use g_new() & friends where that makes obvious sense 2022-03-21 15:44:44 +01:00
imx_i2c.c hw/i2c: Rename i2c_set_slave_address() -> i2c_slave_set_address() 2021-07-08 14:15:01 -05:00
meson.build hw/i2c: add support for PMBus 2021-07-08 14:15:45 -05:00
microbit_i2c.c microbit_i2c: Fix coredump when dump-vmstate 2020-10-20 16:12:00 +01:00
mpc_i2c.c hw: Do not include qemu/log.h if it is not necessary 2021-05-02 17:24:50 +02:00
npcm7xx_smbus.c hw/i2c/npcm7xx_smbus: Simplify npcm7xx_smbus_init() 2021-03-05 15:17:34 +00:00
omap_i2c.c qdev: set properties with device_class_set_props() 2020-01-24 20:59:15 +01:00
pm_smbus.c hw/i2c: Introduce i2c_start_recv() and i2c_start_send() 2021-07-08 14:15:01 -05:00
pmbus_device.c hw/i2c: pmbus: Page #255 is valid page for read requests. 2022-06-30 09:21:13 +02:00
ppc4xx_i2c.c hw/i2c/ppc4xx_i2c: Replace i2c_send_recv() by i2c_recv() & i2c_send() 2021-07-08 14:15:01 -05:00
smbus_eeprom.c i2c/smbus_eeprom: Add feature bit to SPD data 2021-07-29 10:59:49 +10:00
smbus_ich9.c acpi: ich9-smb: add support for AcpiDevAmlIf interface 2022-06-09 19:32:48 -04:00
smbus_master.c hw/i2c: Introduce i2c_start_recv() and i2c_start_send() 2021-07-08 14:15:01 -05:00
smbus_slave.c hw/i2c: add asynchronous send 2022-06-30 09:21:14 +02:00
trace-events hw/i2c: add asynchronous send 2022-06-30 09:21:14 +02:00
trace.h trace: switch position of headers to what Meson requires 2020-08-21 06:18:24 -04:00
versatile_i2c.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00