646c39b220
Add separate macro EXTIOI_CPUS for extioi interrupt controller, extioi only supports 4 cpu. And set macro LOONGARCH_MAX_CPUS as 256 so that loongarch virt machine supports more cpus. Interrupts from external devices can only be routed cpu 0-3 because of extioi limits, cpu internal interrupt such as timer/ipi can be triggered on all cpus. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230512100421.1867848-3-gaosong@loongson.cn> |
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allwinner-a10-pic.h | ||
arm_gic_common.h | ||
arm_gic.h | ||
arm_gicv3_common.h | ||
arm_gicv3_its_common.h | ||
arm_gicv3.h | ||
armv7m_nvic.h | ||
aspeed_vic.h | ||
bcm2835_ic.h | ||
bcm2836_control.h | ||
exynos4210_combiner.h | ||
exynos4210_gic.h | ||
goldfish_pic.h | ||
heathrow_pic.h | ||
i8259.h | ||
imx_avic.h | ||
imx_gpcv2.h | ||
intc.h | ||
ioapic.h | ||
kvm_irqcount.h | ||
loongarch_extioi.h | ||
loongarch_ipi.h | ||
loongarch_pch_msi.h | ||
loongarch_pch_pic.h | ||
loongson_liointc.h | ||
m68k_irqc.h | ||
mips_gic.h | ||
nios2_vic.h | ||
ppc-uic.h | ||
realview_gic.h | ||
riscv_aclint.h | ||
riscv_aplic.h | ||
riscv_imsic.h | ||
rx_icu.h | ||
sifive_plic.h | ||
xlnx-pmu-iomod-intc.h | ||
xlnx-zynqmp-ipi.h |