2004-01-09 03:34:04 +01:00
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@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000, 2001,
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@c 2002, 2003, 2004
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2001-03-09 00:24:26 +01:00
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@c Free Software Foundation, Inc.
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1999-05-03 09:29:11 +02:00
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@c This is part of the GAS manual.
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@c For copying conditions, see the file as.texinfo.
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@ifset GENERIC
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@page
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@node MIPS-Dependent
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@chapter MIPS Dependent Features
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@end ifset
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@ifclear GENERIC
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@node Machine Dependencies
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@chapter MIPS Dependent Features
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@end ifclear
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@cindex MIPS processor
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@sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several
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2000-12-02 01:55:22 +01:00
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different @sc{mips} processors, and MIPS ISA levels I through V, MIPS32,
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2000-12-12 20:36:32 +01:00
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and MIPS64. For information about the @sc{mips} instruction set, see
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@cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall).
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For an overview of @sc{mips} assembly conventions, see ``Appendix D:
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Assembly Language Programming'' in the same work.
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1999-05-03 09:29:11 +02:00
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@menu
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* MIPS Opts:: Assembler options
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* MIPS Object:: ECOFF object code
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* MIPS Stabs:: Directives for debugging information
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* MIPS ISA:: Directives to override the ISA level
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2005-03-04 10:51:11 +01:00
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* MIPS symbol sizes:: Directives to override the size of symbols
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1999-05-03 09:29:11 +02:00
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* MIPS autoextend:: Directives for extending MIPS 16 bit instructions
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* MIPS insn:: Directive to mark data as an instruction
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* MIPS option stack:: Directives to save and restore options
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2002-03-16 11:00:43 +01:00
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* MIPS ASE instruction generation overrides:: Directives to control
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generation of MIPS ASE instructions
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1999-05-03 09:29:11 +02:00
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@end menu
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@node MIPS Opts
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@section Assembler options
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The @sc{mips} configurations of @sc{gnu} @code{@value{AS}} support these
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special options:
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@table @code
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@cindex @code{-G} option (MIPS)
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@item -G @var{num}
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This option sets the largest size of an object that can be referenced
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implicitly with the @code{gp} register. It is only accepted for targets
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that use @sc{ecoff} format. The default value is 8.
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@cindex @code{-EB} option (MIPS)
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@cindex @code{-EL} option (MIPS)
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@cindex MIPS big-endian output
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@cindex MIPS little-endian output
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@cindex big-endian output, MIPS
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@cindex little-endian output, MIPS
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@item -EB
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@itemx -EL
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Any @sc{mips} configuration of @code{@value{AS}} can select big-endian or
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little-endian output at run time (unlike the other @sc{gnu} development
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tools, which must be configured for one or the other). Use @samp{-EB}
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to select big-endian output, and @samp{-EL} for little-endian.
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@cindex MIPS architecture options
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@item -mips1
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@itemx -mips2
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@itemx -mips3
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@itemx -mips4
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2000-12-02 01:55:22 +01:00
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@itemx -mips5
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2000-12-01 22:35:38 +01:00
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@itemx -mips32
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[ bfd/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case.
* archures.c (bfd_mach_mipsisa32r2): New define.
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_mipsisa32r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa32r2.
* elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2.
(_bfd_mips_elf_final_write_processing): Add
bfd_mach_mipsisa32r2 case.
(_bfd_mips_elf_merge_private_bfd_data): Handle merging of
binaries marked as using MIPS32 Release 2.
[ binutils/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* doc/binutils.texi (objdump): Note MIPS HWR (Hardware Register)
changes in MIPS -M options.
[ gas/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* configure.in: Recognize mipsisa32r2, mipsisa32r2el, and
CPU variants.
* configure: Regenerate.
* config/tc-mips.c (ISA_HAS_DROR, ISA_HAS_ROR): New defines.
(macro_build): Handle "K" operand.
(macro2): Use ISA_HAS_DROR and ISA_HAS_ROR in the places where
CPU_HAS_DROR and CPU_HAS_ROR are currently used.
(mips_ip): New variable "lastpos", and implement "+A", "+B",
and "+C" operands for MIPS32 Release 2 ins/ext instructions.
Implement "K" operand for MIPS32 Release 2 rdhwr instruction.
(validate_mips_insn): Implement "+" as a way to extend the
allowed operands, and implement "K", "+A", "+B", and "+C"
operands.
(OPTION_MIPS32R2): New define.
(md_longopts): Add entry for OPTION_MIPS32R2.
(OPTION_ELF_BASE): Adjust to accomodate OPTIONS_MIPS32R2.
(md_parse_option): Handle OPTION_MIPS32R2.
(s_mipsset): Reimplement handling of ".set mipsN" options
and add support for ".set mips32r2".
(mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2).
(md_show_usage): Document "-mips32r2" option.
* doc/as.texinfo: Document "-mips32r2" option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips32r2.d: New test.
* gas/mips/hwr-names-mips32r2.d: New test.
* gas/mips/hwr-names-numeric.d: New test.
* gas/mips/hwr-names.s: New test source file.
* gas/mips/mips32r2.d: New test.
* gas/mips/mips32r2.s: New test source file.
* gas/mips/mips32r2-ill.l: New test.
* gas/mips/mips32r2-ill.s: New test source file.
* gas/mips/mips.exp: Add mips32r2 architecture data array
entry. Run new tests mentioned above.
[ include/elf/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_32R2): New define.
[ include/opcode/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document "+" as the start of two-character operand
type names, and add new "K", "+A", "+B", and "+C" operand types.
(OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
(OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
defines.
[ opcodes/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
(mips_hwr_names_mips3264r2): New arrays.
(mips_arch_choice): New "hwr_names" member.
(mips_arch_choices): Adjust for structure change, and add a new
entry for "mips32r2" ISA.
(mips_hwr_names): New variable.
(set_default_mips_dis_options): Set mips_hwr_names.
(parse_mips_dis_option): New "hwr-names" option which sets
mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
(print_insn_arg): Change return type to "int"
and use that to indicate number of characters consumed.
Add support for "+" operand extension character, "+A", "+B",
"+C", and "K" operands.
(print_insn_mips): Adjust for changes to print_insn_arg.
(print_mips_disassembler_options): Adjust for "hwr-names"
addition and "reg-names" change.
* mips-opc (I33): New define (shorthand for INSN_ISA32R2).
(mips_builtin_opcodes): Note that "nop" and "ssnop" are special
forms of "sll". Add new MIPS32 Release 2 instructions: ehb,
di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
Note that hardware rotate instructions (ror, rorv) can be
used on MIPS32 Release 2, and add the official mnemonics
for them (rotr, rotrv) and the similar "rotl" mnemonic for
left-rotate.
2002-12-31 08:29:29 +01:00
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@itemx -mips32r2
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2000-12-02 01:55:22 +01:00
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@itemx -mips64
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[ bfd/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* archures.c (bfd_mach_mipsisa64r2): New define.
* bfd-in2.h: Regenerate.
* aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2.
* cpu-mips.c (I_mipsisa64r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa64r2.
* elfxx-mips.c (_bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2.
(mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case.
(mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2.
[ binutils/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* readelf.c (get_machine_flags): Handle E_MIPS_ARCH_64R2.
[ gas/Changelog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa64r2, mipsisa64r2el, mipsisa64r2*): New CPUs.
* configure: Regenerate.
* config/tc-mips.c (imm2_expr): New variable.
(md_assemble, mips16_ip): Initialize imm2_expr.
(ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Add ISA_MIPS64R2.
(macro_build): Handle +A, +B, +C, +E, +F, +G, and +H format operands.
(macro): Handle M_DEXT and M_DINS.
(validate_mips_insn): Handle +E, +F, +G, +H, and +I format operands.
(mips_ip): Likewise.
(OPTION_MIPS64R2): New define.
(md_longopts): New entry for -mips64r2 (OPTION_MIPS64R2).
OPTION_ASE_BASE): Increase to compensate for OPTION_MIPS64R2.
(md_parse_option): Handle OPTION_MIPS64R2.
(s_mipsset): Handle setting "mips64r2" ISA.
(mips_cpu_info_table): Add mips64r2.
(md_show_usage): Document -mips64r2 option.
* doc/as.texinfo: Docuemnt -mips64r2 option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips64r2.d: New file.
* gas/mips/cp0sel-names-mips64r2.d: New file.
* gas/mips/elf_arch_mips64r2.d: New file.
* gas/mips/hwr-names-mips64r2.d: New file.
* gas/mips/mips32r2-ill-fp64.l: New file.
* gas/mips/mips32r2-ill-fp64.s: New file.
* gas/mips/mips64r2-ill.l: New file.
* gas/mips/mips64r2-ill.s: New file.
* gas/mips/mips64r2.d: New file.
* gas/mips/mips64r2.s: New file.
* gas/mips/mips.exp: Define "mips64r2" arch, and run new tests.
[ include/elf/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_64R2): New define.
[ include/opcode/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document +E, +F, +G, +H, and +I operand types.
Update documentation of I, +B and +C operand types.
(INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines.
(M_DEXT, M_DINS): New enum values.
[ ld/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ldmain.c (get_emulation): Ignore "-mips64r2".
[ ld/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ld-mips-elf/mips-elf-flags.exp: Add tests for combinations
with MIPS64r2.
[ opcodes/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_arch_choices): Add entry for "mips64r2"
(print_insn_args): Add handing for +E, +F, +G, and +H.
* mips-opc.c (I65): New define for MIPS64r2.
(mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins",
"dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh",
and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to
be supported on MIPS64r2.
2003-09-30 18:17:15 +02:00
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@itemx -mips64r2
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1999-05-03 09:29:11 +02:00
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Generate code for a particular MIPS Instruction Set Architecture level.
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@samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
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@samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the
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2000-12-02 01:55:22 +01:00
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@sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and
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[ bfd/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* archures.c (bfd_mach_mipsisa64r2): New define.
* bfd-in2.h: Regenerate.
* aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2.
* cpu-mips.c (I_mipsisa64r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa64r2.
* elfxx-mips.c (_bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2.
(mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case.
(mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2.
[ binutils/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* readelf.c (get_machine_flags): Handle E_MIPS_ARCH_64R2.
[ gas/Changelog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa64r2, mipsisa64r2el, mipsisa64r2*): New CPUs.
* configure: Regenerate.
* config/tc-mips.c (imm2_expr): New variable.
(md_assemble, mips16_ip): Initialize imm2_expr.
(ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Add ISA_MIPS64R2.
(macro_build): Handle +A, +B, +C, +E, +F, +G, and +H format operands.
(macro): Handle M_DEXT and M_DINS.
(validate_mips_insn): Handle +E, +F, +G, +H, and +I format operands.
(mips_ip): Likewise.
(OPTION_MIPS64R2): New define.
(md_longopts): New entry for -mips64r2 (OPTION_MIPS64R2).
OPTION_ASE_BASE): Increase to compensate for OPTION_MIPS64R2.
(md_parse_option): Handle OPTION_MIPS64R2.
(s_mipsset): Handle setting "mips64r2" ISA.
(mips_cpu_info_table): Add mips64r2.
(md_show_usage): Document -mips64r2 option.
* doc/as.texinfo: Docuemnt -mips64r2 option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips64r2.d: New file.
* gas/mips/cp0sel-names-mips64r2.d: New file.
* gas/mips/elf_arch_mips64r2.d: New file.
* gas/mips/hwr-names-mips64r2.d: New file.
* gas/mips/mips32r2-ill-fp64.l: New file.
* gas/mips/mips32r2-ill-fp64.s: New file.
* gas/mips/mips64r2-ill.l: New file.
* gas/mips/mips64r2-ill.s: New file.
* gas/mips/mips64r2.d: New file.
* gas/mips/mips64r2.s: New file.
* gas/mips/mips.exp: Define "mips64r2" arch, and run new tests.
[ include/elf/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_64R2): New define.
[ include/opcode/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document +E, +F, +G, +H, and +I operand types.
Update documentation of I, +B and +C operand types.
(INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines.
(M_DEXT, M_DINS): New enum values.
[ ld/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ldmain.c (get_emulation): Ignore "-mips64r2".
[ ld/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ld-mips-elf/mips-elf-flags.exp: Add tests for combinations
with MIPS64r2.
[ opcodes/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_arch_choices): Add entry for "mips64r2"
(print_insn_args): Add handing for +E, +F, +G, and +H.
* mips-opc.c (I65): New define for MIPS64r2.
(mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins",
"dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh",
and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to
be supported on MIPS64r2.
2003-09-30 18:17:15 +02:00
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@sc{r10000} processors. @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2},
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@samp{-mips64}, and @samp{-mips64r2}
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correspond to generic
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@sc{MIPS V}, @sc{MIPS32}, @sc{MIPS32 Release 2}, @sc{MIPS64},
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and @sc{MIPS64 Release 2}
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ISA processors, respectively. You can also switch
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2000-12-12 20:36:32 +01:00
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instruction sets during the assembly; see @ref{MIPS ISA, Directives to
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2001-06-29 23:27:43 +02:00
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override the ISA level}.
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1999-05-03 09:29:11 +02:00
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2000-02-22 19:55:30 +01:00
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@item -mgp32
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2001-08-02 12:15:24 +02:00
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@itemx -mfp32
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Some macros have different expansions for 32-bit and 64-bit registers.
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The register sizes are normally inferred from the ISA and ABI, but these
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flags force a certain group of registers to be treated as 32 bits wide at
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all times. @samp{-mgp32} controls the size of general-purpose registers
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and @samp{-mfp32} controls the size of floating-point registers.
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On some MIPS variants there is a 32-bit mode flag; when this flag is
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set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
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save the 32-bit registers on a context switch, so it is essential never
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to use the 64-bit registers.
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2000-02-22 19:55:30 +01:00
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@item -mgp64
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Assume that 64-bit general purpose registers are available. This is
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provided in the interests of symmetry with -gp32.
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1999-05-03 09:29:11 +02:00
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@item -mips16
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@itemx -no-mips16
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Generate code for the MIPS 16 processor. This is equivalent to putting
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@samp{.set mips16} at the start of the assembly file. @samp{-no-mips16}
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turns off this option.
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2002-03-16 04:09:19 +01:00
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@item -mips3d
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@itemx -no-mips3d
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Generate code for the MIPS-3D Application Specific Extension.
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This tells the assembler to accept MIPS-3D instructions.
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@samp{-no-mips3d} turns off this option.
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[ gas/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* config/tc-mips.c (mips_set_options): New "ase_mdmx" member.
(mips_opts): Initialize "ase_mdmx" member.
(file_ase_mdmx): New variable.
(CPU_HAS_MDMX): New macro.
(md_begin): Initialize mips_opts.ase_mdmx and file_ase_mdmx
based on command line options and configuration defaults.
(macro_build): Note in comment that use of MDMX in macros is
not currently allowed.
(validate_mips_insn): Add support for the "O", "Q", "X", "Y", and
"Z" MDMX operand types.
(mips_ip): Accept MDMX instructions if mips_opts.ase_mdmx is set,
and add support for the "O", "Q", "X", "Y", and "Z" MDMX operand
types.
(OPTION_MDMX, OPTION_NO_MDMX, md_longopts, md_parse_option):
Add support for "-mdmx" and "-no-mdmx" options.
(OPTION_ELF_BASE): Move to accomodate new options.
(s_mipsset): Support ".set mdmx" and ".set nomdmx".
(mips_elf_final_processing): Set MDMX ASE ELF header flag if
file_ase_mdmx was set.
* doc/as.texinfo: Document -mdmx and -no-mdmx options.
* doc/c-mips.texi: Likewise, and document ".set mdmx" and ".set
nomdmx" directives.
[ gas/testsuite/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* gas/mips/mips64-mdmx.s: New file.
* gas/mips/mips64-mdmx.d: Likewise.
* gas/mips/mips.exp: Run new "mips64-mdmx" test.
[ include/opcode/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL)
(MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH)
(MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC)
(INSN_MDMX): New constants, for MDMX support.
(opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX.
[ opcodes/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* mips-dis.c (print_insn_arg): Add support for 'O', 'Q', 'X', 'Y',
and 'Z' formats, for MDMX.
(mips_isa_type): Add MDMX instructions to the ISA
bit mask for bfd_mach_mipsisa64.
* mips-opc.c: Add support for MDMX instructions.
(MX): New definition.
* mips-dis.c: Update copyright years to include 2002.
2002-05-31 03:17:18 +02:00
|
|
|
@item -mdmx
|
|
|
|
@itemx -no-mdmx
|
|
|
|
Generate code for the MDMX Application Specific Extension.
|
|
|
|
This tells the assembler to accept MDMX instructions.
|
|
|
|
@samp{-no-mdmx} turns off this option.
|
|
|
|
|
2000-02-21 21:00:33 +01:00
|
|
|
@item -mfix7000
|
2002-05-31 01:38:19 +02:00
|
|
|
@itemx -mno-fix7000
|
2000-02-21 21:00:33 +01:00
|
|
|
Cause nops to be inserted if the read of the destination register
|
|
|
|
of an mfhi or mflo instruction occurs in the following two instructions.
|
|
|
|
|
2004-04-14 09:48:49 +02:00
|
|
|
@item -mfix-vr4120
|
|
|
|
@itemx -no-mfix-vr4120
|
|
|
|
Insert nops to work around certain VR4120 errata. This option is
|
|
|
|
intended to be used on GCC-generated code: it is not designed to catch
|
|
|
|
all problems in hand-written assembler code.
|
[gas/]
* doc/c-mips.texi: Add entries for -march=vr4120,vr4130,vr4181,
vr5400 and vr5500. Add entry for -mfix-vr4122-bugs.
* config/tc-mips.c (CPU_HAS_DROR, CPU_HAS_ROR): New macros.
(hilo_interlocks): True for CPU_VR5500.
(gpr_interlocks, cop_interlocks): True for CPU_VR5400 and CPU_VR5500.
(mips_fix_vr4122_bugs): New.
(append_insn): Work around 4122 errors if mips_fix_vr4122_bugs.
(mips_emit_delays): Likewise.
(macro2) [M_DROLI]: Use dror or dror32 if CPU_HAS_DROR.
[M_ROLI]: Likewise ror if CPU_HAS_ROR.
(validate_mips_insn, mips_ip): Handle '[', ']', 'e' and '%'.
(OPTION_FIX_VR4122, OPTION_NO_FIX_VR4122): New options.
(md_longopts): Add -mfix-vr4122-bugs and -no-mfix-vr4122-bugs.
(OPTION_ELF_BASE): Bump.
(md_parse_option): Handle the new options.
(mips_cpu_info_table): Add entries for vr4120, vr4130, vr4181,
vr5400 and vr5500.
[gas/testsuite/]
* gas/mips/mips4100.[sd]: Move dmadd16 and madd16 checks to...
* gas/mips/vr4111.[sd]: ...this new test.
* gas/mips/vr4120.[sd],
* gas/mips/vr4122.[sd],
* gas/mips/vr5400.[sd],
* gas/mips/vr5500.[sd]: New tests.
* mips.exp: Run them.
2002-09-30 14:04:54 +02:00
|
|
|
|
2005-03-09 10:53:50 +01:00
|
|
|
@item -mfix-vr4130
|
|
|
|
@itemx -no-mfix-vr4130
|
|
|
|
Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata.
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
@item -m4010
|
|
|
|
@itemx -no-m4010
|
|
|
|
Generate code for the LSI @sc{r4010} chip. This tells the assembler to
|
|
|
|
accept the @sc{r4010} specific instructions (@samp{addciu}, @samp{ffc},
|
|
|
|
etc.), and to not schedule @samp{nop} instructions around accesses to
|
|
|
|
the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this
|
|
|
|
option.
|
|
|
|
|
|
|
|
@item -m4650
|
|
|
|
@itemx -no-m4650
|
|
|
|
Generate code for the MIPS @sc{r4650} chip. This tells the assembler to accept
|
|
|
|
the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
|
|
|
|
instructions around accesses to the @samp{HI} and @samp{LO} registers.
|
|
|
|
@samp{-no-m4650} turns off this option.
|
|
|
|
|
|
|
|
@itemx -m3900
|
|
|
|
@itemx -no-m3900
|
|
|
|
@itemx -m4100
|
|
|
|
@itemx -no-m4100
|
|
|
|
For each option @samp{-m@var{nnnn}}, generate code for the MIPS
|
|
|
|
@sc{r@var{nnnn}} chip. This tells the assembler to accept instructions
|
|
|
|
specific to that chip, and to schedule for that chip's hazards.
|
|
|
|
|
2001-06-29 23:27:43 +02:00
|
|
|
@item -march=@var{cpu}
|
1999-05-03 09:29:11 +02:00
|
|
|
Generate code for a particular MIPS cpu. It is exactly equivalent to
|
|
|
|
@samp{-m@var{cpu}}, except that there are more value of @var{cpu}
|
|
|
|
understood. Valid @var{cpu} value are:
|
|
|
|
|
|
|
|
@quotation
|
|
|
|
2000,
|
|
|
|
3000,
|
|
|
|
3900,
|
|
|
|
4000,
|
|
|
|
4010,
|
|
|
|
4100,
|
|
|
|
4111,
|
[gas/]
* doc/c-mips.texi: Add entries for -march=vr4120,vr4130,vr4181,
vr5400 and vr5500. Add entry for -mfix-vr4122-bugs.
* config/tc-mips.c (CPU_HAS_DROR, CPU_HAS_ROR): New macros.
(hilo_interlocks): True for CPU_VR5500.
(gpr_interlocks, cop_interlocks): True for CPU_VR5400 and CPU_VR5500.
(mips_fix_vr4122_bugs): New.
(append_insn): Work around 4122 errors if mips_fix_vr4122_bugs.
(mips_emit_delays): Likewise.
(macro2) [M_DROLI]: Use dror or dror32 if CPU_HAS_DROR.
[M_ROLI]: Likewise ror if CPU_HAS_ROR.
(validate_mips_insn, mips_ip): Handle '[', ']', 'e' and '%'.
(OPTION_FIX_VR4122, OPTION_NO_FIX_VR4122): New options.
(md_longopts): Add -mfix-vr4122-bugs and -no-mfix-vr4122-bugs.
(OPTION_ELF_BASE): Bump.
(md_parse_option): Handle the new options.
(mips_cpu_info_table): Add entries for vr4120, vr4130, vr4181,
vr5400 and vr5500.
[gas/testsuite/]
* gas/mips/mips4100.[sd]: Move dmadd16 and madd16 checks to...
* gas/mips/vr4111.[sd]: ...this new test.
* gas/mips/vr4120.[sd],
* gas/mips/vr4122.[sd],
* gas/mips/vr5400.[sd],
* gas/mips/vr5500.[sd]: New tests.
* mips.exp: Run them.
2002-09-30 14:04:54 +02:00
|
|
|
vr4120,
|
|
|
|
vr4130,
|
|
|
|
vr4181,
|
1999-05-03 09:29:11 +02:00
|
|
|
4300,
|
|
|
|
4400,
|
|
|
|
4600,
|
|
|
|
4650,
|
|
|
|
5000,
|
2000-06-16 21:11:27 +02:00
|
|
|
rm5200,
|
|
|
|
rm5230,
|
|
|
|
rm5231,
|
|
|
|
rm5261,
|
|
|
|
rm5721,
|
[gas/]
* doc/c-mips.texi: Add entries for -march=vr4120,vr4130,vr4181,
vr5400 and vr5500. Add entry for -mfix-vr4122-bugs.
* config/tc-mips.c (CPU_HAS_DROR, CPU_HAS_ROR): New macros.
(hilo_interlocks): True for CPU_VR5500.
(gpr_interlocks, cop_interlocks): True for CPU_VR5400 and CPU_VR5500.
(mips_fix_vr4122_bugs): New.
(append_insn): Work around 4122 errors if mips_fix_vr4122_bugs.
(mips_emit_delays): Likewise.
(macro2) [M_DROLI]: Use dror or dror32 if CPU_HAS_DROR.
[M_ROLI]: Likewise ror if CPU_HAS_ROR.
(validate_mips_insn, mips_ip): Handle '[', ']', 'e' and '%'.
(OPTION_FIX_VR4122, OPTION_NO_FIX_VR4122): New options.
(md_longopts): Add -mfix-vr4122-bugs and -no-mfix-vr4122-bugs.
(OPTION_ELF_BASE): Bump.
(md_parse_option): Handle the new options.
(mips_cpu_info_table): Add entries for vr4120, vr4130, vr4181,
vr5400 and vr5500.
[gas/testsuite/]
* gas/mips/mips4100.[sd]: Move dmadd16 and madd16 checks to...
* gas/mips/vr4111.[sd]: ...this new test.
* gas/mips/vr4120.[sd],
* gas/mips/vr4122.[sd],
* gas/mips/vr5400.[sd],
* gas/mips/vr5500.[sd]: New tests.
* mips.exp: Run them.
2002-09-30 14:04:54 +02:00
|
|
|
vr5400,
|
|
|
|
vr5500,
|
1999-05-03 09:29:11 +02:00
|
|
|
6000,
|
2000-06-16 21:11:27 +02:00
|
|
|
rm7000,
|
1999-05-03 09:29:11 +02:00
|
|
|
8000,
|
2003-07-15 11:02:59 +02:00
|
|
|
rm9000,
|
2000-12-01 22:35:38 +01:00
|
|
|
10000,
|
2001-07-04 14:32:07 +02:00
|
|
|
12000,
|
2000-12-02 02:10:33 +01:00
|
|
|
mips32-4k,
|
|
|
|
sb1
|
1999-05-03 09:29:11 +02:00
|
|
|
@end quotation
|
|
|
|
|
2001-06-29 23:27:43 +02:00
|
|
|
@item -mtune=@var{cpu}
|
|
|
|
Schedule and tune for a particular MIPS cpu. Valid @var{cpu} values are
|
|
|
|
identical to @samp{-march=@var{cpu}}.
|
|
|
|
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
@item -mabi=@var{abi}
|
|
|
|
Record which ABI the source code uses. The recognized arguments
|
|
|
|
are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}.
|
1999-05-03 09:29:11 +02:00
|
|
|
|
2005-03-04 10:51:11 +01:00
|
|
|
@item -msym32
|
|
|
|
@itemx -mno-sym32
|
|
|
|
@cindex -msym32
|
|
|
|
@cindex -mno-sym32
|
|
|
|
Equivalent to adding @code{.set sym32} or @code{.set nosym32} to
|
|
|
|
the beginning of the assembler input. @xref{MIPS symbol sizes}.
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
@cindex @code{-nocpp} ignored (MIPS)
|
|
|
|
@item -nocpp
|
|
|
|
This option is ignored. It is accepted for command-line compatibility with
|
|
|
|
other assemblers, which use it to turn off C style preprocessing. With
|
|
|
|
@sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
|
|
|
|
@sc{gnu} assembler itself never runs the C preprocessor.
|
|
|
|
|
2000-07-15 00:23:33 +02:00
|
|
|
@item --construct-floats
|
|
|
|
@itemx --no-construct-floats
|
|
|
|
@cindex --construct-floats
|
|
|
|
@cindex --no-construct-floats
|
|
|
|
The @code{--no-construct-floats} option disables the construction of
|
|
|
|
double width floating point constants by loading the two halves of the
|
|
|
|
value into the two single width floating point registers that make up
|
|
|
|
the double width register. This feature is useful if the processor
|
|
|
|
support the FR bit in its status register, and this bit is known (by
|
|
|
|
the programmer) to be set. This bit prevents the aliasing of the double
|
|
|
|
width register by the single width registers.
|
|
|
|
|
2000-07-15 17:09:13 +02:00
|
|
|
By default @code{--construct-floats} is selected, allowing construction
|
2000-07-15 00:23:33 +02:00
|
|
|
of these floating point constants.
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
@item --trap
|
|
|
|
@itemx --no-break
|
|
|
|
@c FIXME! (1) reflect these options (next item too) in option summaries;
|
|
|
|
@c (2) stop teasing, say _which_ instructions expanded _how_.
|
|
|
|
@code{@value{AS}} automatically macro expands certain division and
|
|
|
|
multiplication instructions to check for overflow and division by zero. This
|
|
|
|
option causes @code{@value{AS}} to generate code to take a trap exception
|
|
|
|
rather than a break exception when an error is detected. The trap instructions
|
|
|
|
are only supported at Instruction Set Architecture level 2 and higher.
|
|
|
|
|
|
|
|
@item --break
|
|
|
|
@itemx --no-trap
|
|
|
|
Generate code to take a break exception rather than a trap exception when an
|
|
|
|
error is detected. This is the default.
|
2001-06-11 22:40:36 +02:00
|
|
|
|
2003-07-28 22:06:27 +02:00
|
|
|
@item -mpdr
|
|
|
|
@itemx -mno-pdr
|
|
|
|
Control generation of @code{.pdr} sections. Off by default on IRIX, on
|
|
|
|
elsewhere.
|
2004-12-10 20:48:21 +01:00
|
|
|
|
|
|
|
@item -mshared
|
|
|
|
@itemx -mno-shared
|
|
|
|
When generating code using the Unix calling conventions (selected by
|
|
|
|
@samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code
|
|
|
|
which can go into a shared library. The @samp{-mno-shared} option
|
|
|
|
tells gas to generate code which uses the calling convention, but can
|
|
|
|
not go into a shared library. The resulting code is slightly more
|
|
|
|
efficient. This option only affects the handling of the
|
|
|
|
@samp{.cpload} and @samp{.cpsetup} pseudo-ops.
|
1999-05-03 09:29:11 +02:00
|
|
|
@end table
|
|
|
|
|
|
|
|
@node MIPS Object
|
|
|
|
@section MIPS ECOFF object code
|
|
|
|
|
|
|
|
@cindex ECOFF sections
|
|
|
|
@cindex MIPS ECOFF sections
|
|
|
|
Assembling for a @sc{mips} @sc{ecoff} target supports some additional sections
|
|
|
|
besides the usual @code{.text}, @code{.data} and @code{.bss}. The
|
|
|
|
additional sections are @code{.rdata}, used for read-only data,
|
|
|
|
@code{.sdata}, used for small data, and @code{.sbss}, used for small
|
|
|
|
common objects.
|
|
|
|
|
|
|
|
@cindex small objects, MIPS ECOFF
|
|
|
|
@cindex @code{gp} register, MIPS
|
|
|
|
When assembling for @sc{ecoff}, the assembler uses the @code{$gp} (@code{$28})
|
|
|
|
register to form the address of a ``small object''. Any object in the
|
|
|
|
@code{.sdata} or @code{.sbss} sections is considered ``small'' in this sense.
|
|
|
|
For external objects, or for objects in the @code{.bss} section, you can use
|
|
|
|
the @code{@value{GCC}} @samp{-G} option to control the size of objects addressed via
|
|
|
|
@code{$gp}; the default value is 8, meaning that a reference to any object
|
|
|
|
eight bytes or smaller uses @code{$gp}. Passing @samp{-G 0} to
|
|
|
|
@code{@value{AS}} prevents it from using the @code{$gp} register on the basis
|
|
|
|
of object size (but the assembler uses @code{$gp} for objects in @code{.sdata}
|
|
|
|
or @code{sbss} in any case). The size of an object in the @code{.bss} section
|
|
|
|
is set by the @code{.comm} or @code{.lcomm} directive that defines it. The
|
|
|
|
size of an external object may be set with the @code{.extern} directive. For
|
|
|
|
example, @samp{.extern sym,4} declares that the object at @code{sym} is 4 bytes
|
|
|
|
in length, whie leaving @code{sym} otherwise undefined.
|
|
|
|
|
|
|
|
Using small @sc{ecoff} objects requires linker support, and assumes that the
|
|
|
|
@code{$gp} register is correctly initialized (normally done automatically by
|
|
|
|
the startup code). @sc{mips} @sc{ecoff} assembly code must not modify the
|
|
|
|
@code{$gp} register.
|
|
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@node MIPS Stabs
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@section Directives for debugging information
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@cindex MIPS debugging directives
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@sc{mips} @sc{ecoff} @code{@value{AS}} supports several directives used for
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generating debugging information which are not support by traditional @sc{mips}
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assemblers. These are @code{.def}, @code{.endef}, @code{.dim}, @code{.file},
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@code{.scl}, @code{.size}, @code{.tag}, @code{.type}, @code{.val},
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@code{.stabd}, @code{.stabn}, and @code{.stabs}. The debugging information
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generated by the three @code{.stab} directives can only be read by @sc{gdb},
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not by traditional @sc{mips} debuggers (this enhancement is required to fully
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support C++ debugging). These directives are primarily used by compilers, not
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assembly language programmers!
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2005-03-04 10:51:11 +01:00
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@node MIPS symbol sizes
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@section Directives to override the size of symbols
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@cindex @code{.set sym32}
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@cindex @code{.set nosym32}
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The n64 ABI allows symbols to have any 64-bit value. Although this
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provides a great deal of flexibility, it means that some macros have
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much longer expansions than their 32-bit counterparts. For example,
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the non-PIC expansion of @samp{dla $4,sym} is usually:
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@smallexample
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lui $4,%highest(sym)
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lui $1,%hi(sym)
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daddiu $4,$4,%higher(sym)
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daddiu $1,$1,%lo(sym)
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dsll32 $4,$4,0
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daddu $4,$4,$1
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@end smallexample
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whereas the 32-bit expansion is simply:
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@smallexample
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lui $4,%hi(sym)
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daddiu $4,$4,%lo(sym)
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@end smallexample
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n64 code is sometimes constructed in such a way that all symbolic
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constants are known to have 32-bit values, and in such cases, it's
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preferable to use the 32-bit expansion instead of the 64-bit
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expansion.
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You can use the @code{.set sym32} directive to tell the assembler
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that, from this point on, all expressions of the form
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@samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}}
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have 32-bit values. For example:
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@smallexample
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.set sym32
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dla $4,sym
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lw $4,sym+16
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sw $4,sym+0x8000($4)
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@end smallexample
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will cause the assembler to treat @samp{sym}, @code{sym+16} and
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@code{sym+0x8000} as 32-bit values. The handling of non-symbolic
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addresses is not affected.
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The directive @code{.set nosym32} ends a @code{.set sym32} block and
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reverts to the normal behavior. It is also possible to change the
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symbol size using the command-line options @option{-msym32} and
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@option{-mno-sym32}.
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These options and directives are always accepted, but at present,
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they have no effect for anything other than n64.
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1999-05-03 09:29:11 +02:00
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@node MIPS ISA
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@section Directives to override the ISA level
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@cindex MIPS ISA override
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@kindex @code{.set mips@var{n}}
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@sc{gnu} @code{@value{AS}} supports an additional directive to change
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the @sc{mips} Instruction Set Architecture level on the fly: @code{.set
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[ bfd/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* archures.c (bfd_mach_mipsisa64r2): New define.
* bfd-in2.h: Regenerate.
* aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2.
* cpu-mips.c (I_mipsisa64r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa64r2.
* elfxx-mips.c (_bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2.
(mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case.
(mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2.
[ binutils/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* readelf.c (get_machine_flags): Handle E_MIPS_ARCH_64R2.
[ gas/Changelog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa64r2, mipsisa64r2el, mipsisa64r2*): New CPUs.
* configure: Regenerate.
* config/tc-mips.c (imm2_expr): New variable.
(md_assemble, mips16_ip): Initialize imm2_expr.
(ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Add ISA_MIPS64R2.
(macro_build): Handle +A, +B, +C, +E, +F, +G, and +H format operands.
(macro): Handle M_DEXT and M_DINS.
(validate_mips_insn): Handle +E, +F, +G, +H, and +I format operands.
(mips_ip): Likewise.
(OPTION_MIPS64R2): New define.
(md_longopts): New entry for -mips64r2 (OPTION_MIPS64R2).
OPTION_ASE_BASE): Increase to compensate for OPTION_MIPS64R2.
(md_parse_option): Handle OPTION_MIPS64R2.
(s_mipsset): Handle setting "mips64r2" ISA.
(mips_cpu_info_table): Add mips64r2.
(md_show_usage): Document -mips64r2 option.
* doc/as.texinfo: Docuemnt -mips64r2 option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips64r2.d: New file.
* gas/mips/cp0sel-names-mips64r2.d: New file.
* gas/mips/elf_arch_mips64r2.d: New file.
* gas/mips/hwr-names-mips64r2.d: New file.
* gas/mips/mips32r2-ill-fp64.l: New file.
* gas/mips/mips32r2-ill-fp64.s: New file.
* gas/mips/mips64r2-ill.l: New file.
* gas/mips/mips64r2-ill.s: New file.
* gas/mips/mips64r2.d: New file.
* gas/mips/mips64r2.s: New file.
* gas/mips/mips.exp: Define "mips64r2" arch, and run new tests.
[ include/elf/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_64R2): New define.
[ include/opcode/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document +E, +F, +G, +H, and +I operand types.
Update documentation of I, +B and +C operand types.
(INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines.
(M_DEXT, M_DINS): New enum values.
[ ld/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ldmain.c (get_emulation): Ignore "-mips64r2".
[ ld/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ld-mips-elf/mips-elf-flags.exp: Add tests for combinations
with MIPS64r2.
[ opcodes/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_arch_choices): Add entry for "mips64r2"
(print_insn_args): Add handing for +E, +F, +G, and +H.
* mips-opc.c (I65): New define for MIPS64r2.
(mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins",
"dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh",
and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to
be supported on MIPS64r2.
2003-09-30 18:17:15 +02:00
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mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 64
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or 64r2.
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2003-01-02 21:03:09 +01:00
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The values other than 0 make the assembler accept instructions
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2000-12-12 20:36:32 +01:00
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for the corresponding @sc{isa} level, from that point on in the
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assembly. @code{.set mips@var{n}} affects not only which instructions
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are permitted, but also how certain macros are expanded. @code{.set
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mips0} restores the @sc{isa} level to its original level: either the
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level you selected with command line options, or the default for your
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configuration. You can use this feature to permit specific @sc{r4000}
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instructions while assembling in 32 bit mode. Use this directive with
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2001-06-29 23:27:43 +02:00
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care!
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1999-05-03 09:29:11 +02:00
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The directive @samp{.set mips16} puts the assembler into MIPS 16 mode,
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in which it will assemble instructions for the MIPS 16 processor. Use
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@samp{.set nomips16} to return to normal 32 bit mode.
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2001-06-29 23:27:43 +02:00
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Traditional @sc{mips} assemblers do not support this directive.
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1999-05-03 09:29:11 +02:00
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@node MIPS autoextend
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@section Directives for extending MIPS 16 bit instructions
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@kindex @code{.set autoextend}
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@kindex @code{.set noautoextend}
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By default, MIPS 16 instructions are automatically extended to 32 bits
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when necessary. The directive @samp{.set noautoextend} will turn this
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off. When @samp{.set noautoextend} is in effect, any 32 bit instruction
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must be explicitly extended with the @samp{.e} modifier (e.g.,
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@samp{li.e $4,1000}). The directive @samp{.set autoextend} may be used
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to once again automatically extend instructions when necessary.
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This directive is only meaningful when in MIPS 16 mode. Traditional
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@sc{mips} assemblers do not support this directive.
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@node MIPS insn
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@section Directive to mark data as an instruction
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@kindex @code{.insn}
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The @code{.insn} directive tells @code{@value{AS}} that the following
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data is actually instructions. This makes a difference in MIPS 16 mode:
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when loading the address of a label which precedes instructions,
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@code{@value{AS}} automatically adds 1 to the value, so that jumping to
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the loaded address will do the right thing.
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@node MIPS option stack
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@section Directives to save and restore options
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@cindex MIPS option stack
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@kindex @code{.set push}
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@kindex @code{.set pop}
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The directives @code{.set push} and @code{.set pop} may be used to save
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and restore the current settings for all the options which are
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controlled by @code{.set}. The @code{.set push} directive saves the
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current settings on a stack. The @code{.set pop} directive pops the
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stack and restores the settings.
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These directives can be useful inside an macro which must change an
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option such as the ISA level or instruction reordering but does not want
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to change the state of the code which invoked the macro.
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Traditional @sc{mips} assemblers do not support these directives.
|
2002-03-16 04:09:19 +01:00
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@node MIPS ASE instruction generation overrides
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@section Directives to control generation of MIPS ASE instructions
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@cindex MIPS MIPS-3D instruction generation override
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@kindex @code{.set mips3d}
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@kindex @code{.set nomips3d}
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The directive @code{.set mips3d} makes the assembler accept instructions
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from the MIPS-3D Application Specific Extension from that point on
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in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D
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instructions from being accepted.
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[ gas/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* config/tc-mips.c (mips_set_options): New "ase_mdmx" member.
(mips_opts): Initialize "ase_mdmx" member.
(file_ase_mdmx): New variable.
(CPU_HAS_MDMX): New macro.
(md_begin): Initialize mips_opts.ase_mdmx and file_ase_mdmx
based on command line options and configuration defaults.
(macro_build): Note in comment that use of MDMX in macros is
not currently allowed.
(validate_mips_insn): Add support for the "O", "Q", "X", "Y", and
"Z" MDMX operand types.
(mips_ip): Accept MDMX instructions if mips_opts.ase_mdmx is set,
and add support for the "O", "Q", "X", "Y", and "Z" MDMX operand
types.
(OPTION_MDMX, OPTION_NO_MDMX, md_longopts, md_parse_option):
Add support for "-mdmx" and "-no-mdmx" options.
(OPTION_ELF_BASE): Move to accomodate new options.
(s_mipsset): Support ".set mdmx" and ".set nomdmx".
(mips_elf_final_processing): Set MDMX ASE ELF header flag if
file_ase_mdmx was set.
* doc/as.texinfo: Document -mdmx and -no-mdmx options.
* doc/c-mips.texi: Likewise, and document ".set mdmx" and ".set
nomdmx" directives.
[ gas/testsuite/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* gas/mips/mips64-mdmx.s: New file.
* gas/mips/mips64-mdmx.d: Likewise.
* gas/mips/mips.exp: Run new "mips64-mdmx" test.
[ include/opcode/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL)
(MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH)
(MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC)
(INSN_MDMX): New constants, for MDMX support.
(opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX.
[ opcodes/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* mips-dis.c (print_insn_arg): Add support for 'O', 'Q', 'X', 'Y',
and 'Z' formats, for MDMX.
(mips_isa_type): Add MDMX instructions to the ISA
bit mask for bfd_mach_mipsisa64.
* mips-opc.c: Add support for MDMX instructions.
(MX): New definition.
* mips-dis.c: Update copyright years to include 2002.
2002-05-31 03:17:18 +02:00
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@cindex MIPS MDMX instruction generation override
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@kindex @code{.set mdmx}
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@kindex @code{.set nomdmx}
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The directive @code{.set mdmx} makes the assembler accept instructions
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from the MDMX Application Specific Extension from that point on
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in the assembly. The @code{.set nomdmx} directive prevents MDMX
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instructions from being accepted.
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2002-03-16 04:09:19 +01:00
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Traditional @sc{mips} assemblers do not support these directives.
|