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MIPS/LD: Fix memory fault linking non-PIC object in to shared library bfd/ * elfxx-mips.c (_bfd_mips_elf_check_relocs): Add NULL pointer checks. Search the RELA table for n64 relocations. ld/ * testsuite/ld-mips-elf/pic-reloc-5.d: New test. * testsuite/ld-mips-elf/pic-reloc-6.d: New test. * testsuite/ld-mips-elf/pic-reloc-7.d: New test. * testsuite/ld-mips-elf/pic-reloc-5.s: New test source. * testsuite/ld-mips-elf/pic-reloc-6.s: New test source. * testsuite/ld-mips-elf/pic-reloc-7.s: New test source. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2019-05-18 10:19:03 +02:00
2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
* elfxx-mips.c (_bfd_mips_elf_check_relocs): Add NULL pointer
checks. Search the RELA table for n64 relocations.
[MIPS] Add generation of PLT entries with compact jumps for MIPS R6 Add a new option to get the linker to emit PLTs that use compact branches instead of delay slot branches. bfd/ * elfxx-mips.c (LA25_BC): New macro. (mips_elf_link_hash_table)<compact_branches>: New field. (STUB_JALRC): New macro. (mipsr6_o32_exec_plt0_entry_compact): New array. (mipsr6_n32_exec_plt0_entry_compact): Likewise. (mipsr6_n64_exec_plt0_entry_compact): Likewise. (mipsr6_exec_plt_entry_compact): Likewise. (mips_elf_create_la25_stub): Use BC instead of J for stubs when compact_branches is true. (_bfd_mips_elf_finish_dynamic_symbol): Choose the compact PLT for MIPSR6 with compact_branches. Do not reorder the compact branches PLT. Switch the lazy stub for MIPSR6 with compact_branches to use JALRC. (mips_finish_exec_plt): Choose the compact PLT0 for MIPSR6 when compact_branches is true. (_bfd_mips_elf_compact_branches): New function. * elfxx-mips.h (_bfd_mips_elf_compact_branches): New prototype. ld/ * emultempl/mipself.em (compact_branches): New static variable. (mips_create_output_section_statements): Call _bfd_mips_elf_compact_branches. (PARSE_AND_LIST_PROLOGUE): Add OPTION_COMPACT_BRANCHES and OPTION_NO_COMPACT_BRANCHES. (PARSE_AND_LIST_LONGOPTS): Add compact-branches, no-compact-branches. (PARSE_AND_LIST_OPTIONS): Add --compact-branches, --no-compact-branches. (PARSE_AND_LIST_ARGS_CASES): Handle the above. * ld.texinfo: Document --compact-branches, --no-compact-branches. * testsuite/ld-mips-elf/pic-and-nonpic-1-r6.dd: New test. * testsuite/ld-mips-elf/pic-and-nonpic-1-r6.nd: New test. * testsuite/ld-mips-elf/pic-and-nonpic-3a-r6.dd: New test. * testsuite/ld-mips-elf/pic-and-nonpic-3a-r6.gd: New test. * testsuite/ld-mips-elf/pic-and-nonpic-1a-r6.s: New test source. * testsuite/ld-mips-elf/pic-and-nonpic-3a-r6.s: New test source. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2019-05-14 02:03:19 +02:00
2019-05-21 Matthew Fortune <matthew.fortune@mips.com>
Faraz Shahbazker <fshahbazker@wavecomp.com>
* elfxx-mips.c (LA25_BC): New macro.
(mips_elf_link_hash_table)<compact_branches>: New field.
(STUB_JALRC): New macro.
(mipsr6_o32_exec_plt0_entry_compact): New array.
(mipsr6_n32_exec_plt0_entry_compact): Likewise.
(mipsr6_n64_exec_plt0_entry_compact): Likewise.
(mipsr6_exec_plt_entry_compact): Likewise.
(mips_elf_create_la25_stub): Use BC instead of J for stubs
when compact_branches is true.
(_bfd_mips_elf_finish_dynamic_symbol): Choose the compact
PLT for MIPSR6 with compact_branches. Do not reorder the
compact branches PLT. Switch the lazy stub for MIPSR6
with compact_branches to use JALRC.
(mips_finish_exec_plt): Choose the compact PLT0 for MIPSR6
when compact_branches is true.
(_bfd_mips_elf_compact_branches): New function.
* elfxx-mips.h (_bfd_mips_elf_compact_branches): New prototype.
AArch64: Fix -Werror on build This patch fixes a hardcoded `l` specifier on a `bfd_signed_vma`. Instead this now uses BFD_VMA_FMT which fixes the build on 32 bit hosts. Committed under the obvious rule. bfd/ChangeLog: PR ld/24373 * elfnn-aarch64.c (_bfd_aarch64_erratum_843419_branch_to_stub): Fix print formatter.
2019-05-21 18:15:36 +02:00
2019-05-21 Tamar Christina <tamar.christina@arm.com>
PR ld/24373
* elfnn-aarch64.c (_bfd_aarch64_erratum_843419_branch_to_stub):
Fix print formatter.
[binutils][Arm] Fix Branch Future relocation handling and testisms bfd/ChangeLog: 2019-05-21 Andre Vieira <andre.simoesdiasvieira@arm.com> PR/target 24460 * elf32-arm.c (get_value_helper): Remove. (elf32_arm_final_link_relocate): Fix branch future relocations. gas/ChangeLog: 2019-05-21 Andre Vieira <andre.simoesdiasvieira@arm.com> * testsuite/gas/arm/armv8_1-m-bf.d: Allow different branch target naming conventions. * testsuite/gas/arm/armv8_1-m-bfl.d: Likewise. * testsuite/gas/arm/armv8_1-m-bfcsel.d: Likewise. * testsuite/gas/arm/armv8_1-m-loloop.d: Likewise. * testsuite/gas/arm/armv8_1-m-bf-rel.d: Skip for vxworks. * testsuite/gas/arm/armv8_1-m-bf-rela.d: New test. * testsuite/gas/arm/armv8_1-m-bfl-rel.d: Skip for vxworks. * testsuite/gas/arm/armv8_1-m-bfl-rela.d: New test. ld/ChangeLog: 2019-05-21 Andre Vieira <andre.simoesdiasvieira@arm.com> * testsuite/ld-arm/arm-elf.exp: Add tests * testsuite/ld-arm/bfs-0.s: New test. * testsuite/ld-arm/bfs-1.s: New test. * testsuite/ld-arm/branch-futures.d: New test.
2019-05-21 15:49:03 +02:00
2019-05-21 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR 24460
* elf32-arm.c (get_value_helper): Remove.
(elf32_arm_final_link_relocate): Fix branch future relocations.
AArch64: Implement choice between Cortex-A53 erratum workarounds. (PR ld/24373) The Cortex-A53 erratum currently has two ways it can resolve the erratum when using the flag --fix-cortex-a53-843419: 1) If the address is within the range of an ADR instruction it rewrites the ADRP into an ADR, and those doesn't need the use of a veneer. 2) If the address is not within range, it adds a branch to a veneer which will execute the final bit of the erratum workaround and branch back to the call site. When we do this we always generate the veneers and we always align the size of the text section to 4KB. This is because we only know which workaround we can use after all linking has finished and all addresses are known. This means even though the veneers are not used, we still generate the section and we still change the size of the input section. This is problematic for small memory devices as this would require the user to take about a ~4KB hit in memory even though it's not even used. Since there's no real way to restart the linking process from the final write phase this patch solves the issue by allowing the user more control over which erratum workaround gets used. Concretely this changes the option --fix-cortex-a53-843419 to take optional arguments --fix-cortex-a53-843419[=full|adr|adrp] - full (default): Use both ADRP and ADR workaround. This is equivalent to not specifying any options and is the default behavior before this patch. - adr: Only use the ADR workaround, this will not cause any increase in binary size but linking will fail if the referenced address is out of range of an ADR instruction. - adrp: Use only the ADRP workaround, this will never rewrite your ADRP. In the cases where the user knows how big their binaries are the `adr` option would prevent the unneeded overhead. bfd/ChangeLog: PR ld/24373 * bfd-in.h (enum erratum_84319_opts): New (bfd_elf64_aarch64_set_options, bfd_elf32_aarch64_set_options): Change int to enum erratum_84319_opts. * bfd-in2.h: Regenerate. * elfnn-aarch64.c (struct elf_aarch64_link_hash_table): Change fix_erratum_843419 to use new enum, remove fix_erratum_843419_adr. (_bfd_aarch64_add_stub_entry_after): Conditionally create erratum stub. (aarch64_size_one_stub): Conditionally size erratum 843419 stubs. (_bfd_aarch64_resize_stubs): Amend comment. (elfNN_aarch64_size_stubs): Don't generate stubs when no workaround requested. (bfd_elfNN_aarch64_set_options): Use new fix_erratum_843419 enum. (_bfd_aarch64_erratum_843419_branch_to_stub): Implement selection of erratum workaround. (clear_erratum_843419_entry): Update erratum conditional. ld/ChangeLog: PR ld/24373 * emultempl/aarch64elf.em (PARSE_AND_LIST_LONGOPTS): Add optional args to flags. * NEWS: Add changes to flag. (PARSE_AND_LIST_OPTIONS): Update help descriptions. (PARSE_AND_LIST_ARGS_CASES): Add new options to parser. * testsuite/ld-aarch64/aarch64-elf.exp: Add new run_dump_tests. * testsuite/ld-aarch64/erratum843419-adr.d: New test. * testsuite/ld-aarch64/erratum843419-adrp.d: New test. * testsuite/ld-aarch64/erratum843419-far-adr.d: New test. * testsuite/ld-aarch64/erratum843419-far-full.d: New test. * testsuite/ld-aarch64/erratum843419-far.s: New test. * testsuite/ld-aarch64/erratum843419-full.d: New test. * testsuite/ld-aarch64/erratum843419-near.s: New test. * testsuite/ld-aarch64/erratum843419-no-args.d: New test.
2019-05-21 14:04:08 +02:00
2019-05-21 Tamar Christina <tamar.christina@arm.com>
PR ld/24373
* bfd-in.h (enum erratum_84319_opts): New
(bfd_elf64_aarch64_set_options, bfd_elf32_aarch64_set_options): Change
int to enum erratum_84319_opts.
* bfd-in2.h: Regenerate.
* elfnn-aarch64.c (struct elf_aarch64_link_hash_table): Change
fix_erratum_843419 to use new enum, remove fix_erratum_843419_adr.
(_bfd_aarch64_add_stub_entry_after): Conditionally create erratum stub.
(aarch64_size_one_stub): Conditionally size erratum 843419 stubs.
(_bfd_aarch64_resize_stubs): Amend comment.
(elfNN_aarch64_size_stubs): Don't generate stubs when no workaround
requested.
(bfd_elfNN_aarch64_set_options): Use new fix_erratum_843419 enum.
(_bfd_aarch64_erratum_843419_branch_to_stub): Implement selection of
erratum workaround.
(clear_erratum_843419_entry): Update erratum conditional.
Fix PR 24571 - Relaxation does not shorten jmp or call to target at pc-relative range boundary The range check done to transform an absolute call/jump to a pc-relative one is off-by-one, and that causes this shortening optimization to be missed if the branch target is right at the range boundary. In the non-shrinkable case, the range is what is mentioned in the ISA - -4094 bytes in the backward direction, and 4096 bytes in the positive direction. In the shrinkable case, the forward jump range increases by two bytes (deleted because of the shortening from call/jmp to rcall/rjmp), and therefore, the range is -4094 in the reverse, and 4098 in the positive direction. Fix the ranges for !shrinkable and shrinkable cases, and add a test caes to ensure jumps to max forward and backward ranges get relaxed to rjmp.
2019-05-16 08:42:33 +02:00
2019-05-21 Senthil Kumar Selvaraj <senthilkumar.selvaraj@microchip.com>
PR ld/24571
* bfd/elf32-avr.c (elf32_avr_relax_section): Adjust range check
when computing distance_short_enough.
Fix PR 24564 - link fails for some rcalls/rjmps with wraparound The current code to compute relative distance in the wrap around case does not handle the edge case of the target (after adjusting for implicit PC increment) being exactly half of the wrap around distance. This patch fixes that and adds a testcase. The range for a forward relative jump call is 4096 bytes ((2 * 2047) + (2 bytes for the implicit PC increment)). If the target of the jump is at a distance of 4098 bytes, it is out of range for a forward jump - however, a backward jump can still reach that address if pmem-wrap-around is 8192. Assume address 0 has rjmp to address 4098. With a wrap around of 8192 and *without* adjusting for the implicit PC increment of 2 bytes, rjmp .-4096 will jump to address 4096 (wrap around at 8192 and decreasing addresses from then on). Adjusting 2 bytes for the implicit PC increment, the actual target is 4098. avr_relative_distance_considering_wrap_around though, does the wrap around only if the passed in distance is less than half of the wrap around distance. In this case, it is exactly equal to half (original distance 4098, adjusted distance of 4096 and wraparound of 8192), and the bypassed wrap around causes the reloc overflow error. Fix by wrapping around even if adjusted distance is equal to half of wrap around distance.
2019-05-16 13:46:36 +02:00
2019-05-21 Senthil Kumar Selvaraj <senthilkumar.selvaraj@microchip.com>
PR ld/24564
* bfd/elf32-avr.c (avr_relative_distance_considering_wrap_around):
Wrap around even if distance equals avr_pc_wrap_around.
Updated translations for various binutils subdirectories. bfd * po/fr.po: Updated French translation. binutils* po/ca.po: Updated Catalan translation. gprof * po/de.po: Updated German translation. opcodes * po/fr.po: Updated French translation.
2019-05-20 17:18:19 +02:00
2019-05-20 Nick Clifton <nickc@redhat.com>
* po/fr.po: Updated French translation.
[PATCH 1/57][Arm][GAS]: Add support for +mve and +mve.fp bfd/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * elf32-arm.c (elf32_arm_merge_eabi_attributes): Add case for Tag_MVE_arch. binutils/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * readelf.c (arm_attr_tag_MVE_arch): New array for Tag_MVE_arch values. (arm_attr_public_tag arm_attr_public_tags): Add case for Tag_MVE_arch. elfcpp/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * arm.h (Tag_MVE_arch): Define new enum value. gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (mve_ext, mve_fp_ext): New features. (armv8_1m_main_ext_table): Add new extensions. (aeabi_set_public_attributes): Translate new features to new build attributes. (arm_convert_symbolic_attribute): Add Tag_MVE_arch. * doc/c-arm.texi: Document new extensions and new build attribute. include/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * elf/arm.h (Tag_MVE_arch): Define new enum value. * opcode/arm.h (FPU_MVE, FPU_MVE_FP): New MACROs for new features.
2019-05-15 17:44:57 +02:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* elf32-arm.c (elf32_arm_merge_eabi_attributes): Add case for Tag_MVE_arch.
Revert "ARM STM32L4XX erratum test failure" This reverts commit 3a1bb98c3c4f983b950fbaf2797ddcd21fcb5211.
2019-05-16 15:05:25 +02:00
2019-05-16 Alan Modra <amodra@gmail.com>
* elf32-arm.c (elf32_arm_write_section): Revert last change.
ARM STM32L4XX erratum test failure Fixes a failure seen with MALLOC_PERTURB_=1. * elf32-arm.c (elf32_arm_write_section): Don't leave error case of STM32L4XX_ERRATUM_BRANCH_TO_VENEER with unitialised section contents.
2019-05-15 09:01:28 +02:00
2019-05-15 Alan Modra <amodra@gmail.com>
* elf32-arm.c (elf32_arm_write_section): Don't leave
error case of STM32L4XX_ERRATUM_BRANCH_TO_VENEER with
unitialised section contents.
Add new option to objcopy: --verilog-data-width. Use this option to set the size of byte bundles generated in verilog format files. PR 19921 binutils* objcopy.c: Add new option --verilog-data-width. Use it to set the value of VerilogDataWidth. * doc/binutils.texi: Document the new option. * testsuite/binutils-all/objcopy.exp: Run tests of new option. * testsuite/binutils-all/verilog-1.hex: New file. * testsuite/binutils-all/verilog-2.hex: New file. * testsuite/binutils-all/verilog-4.hex: New file. * testsuite/binutils-all/verilog-8.hex: New file. * NEWS: Mention the new feature. bfd * verilog.c: (VerilogDataWidth): New variable. (verilog_write_record): Emit bytes in VerilogDataWidth bundles.
2019-05-14 11:40:04 +02:00
2019-05-14 Jamey Hicks <jamey.hicks@gmail.com>
PR 19921
* verilog.c: (VerilogDataWidth): New variable.
(verilog_write_record): Emit bytes in VerilogDataWidth bundles.
Do not force the m68k-elf linker to fail if it encoutners a non-ELF format file. PR 24523 * elf32-m68k.c (elf32_m68k_merge_private_bfd_data): Return TRUE rather than FALSE if encountering a non-ELF file.
2019-05-08 15:51:32 +02:00
2019-05-08 Nick Clifton <nickc@redhat.com>
PR 24523
* elf32-m68k.c (elf32_m68k_merge_private_bfd_data): Return TRUE
rather than FALSE if encountering a non-ELF file.
PicoJava weak undefined symbols This fixes the recently added ld-elf/pr24511 test failure on pj-elf. Incidentally, pj-elf has failed its gas "pj" test since 2005-12-22 (git commit 54758c3e39). I think that makes the target ripe for obsolescence. bfd/ * elf32-pj.c (pj_elf_reloc): Don't report undefined weak as an error. ld/ * testsuite/ld-undefined/weak-undef.exp: Don't xfail pj.
2019-05-06 01:43:53 +02:00
2019-05-06 Alan Modra <amodra@gmail.com>
* elf32-pj.c (pj_elf_reloc): Don't report undefined weak as an error.
PowerPC reloc symbols that shouldn't be adjusted GOT and PLT relocs shouldn't have their symbols replaced with a section symbol plus added. Nor should the HIGHA TLS relocations, which failed to be caught by the range test in ppc_fix_adjustable. bfd/ * reloc.c (BFD_RELOC_PPC64_TPREL16_HIGH, BFD_RELOC_PPC64_TPREL16_HIGHA), (BFD_RELOC_PPC64_DTPREL16_HIGH, BFD_RELOC_PPC64_DTPREL16_HIGHA): Sort before BFD_RELOC_PPC64_DTPREL16_HIGHESTA entry. gas/ * config/tc-ppc.c (ppc_fix_adjustable): Exclude all GOT and PLT relocs, and VLE sdarel relocs. * testsuite/gas/ppc/power4.d: Adjust.
2019-05-06 01:13:32 +02:00
2019-05-06 Alan Modra <amodra@gmail.com>
* reloc.c (BFD_RELOC_PPC64_TPREL16_HIGH, BFD_RELOC_PPC64_TPREL16_HIGHA),
(BFD_RELOC_PPC64_DTPREL16_HIGH, BFD_RELOC_PPC64_DTPREL16_HIGHA):
Sort before BFD_RELOC_PPC64_DTPREL16_HIGHESTA entry.
* libbfd.h: Regenerate.
* bfd-in2.h: Regenerate.
PR24511, nm should not mark symbols in .init_array as "t" This patch restricts the section names matched in coff_section_type, a function that translates section names to symbol type, and arranges to translate section flags to symbol type before looking at names. The latter change resulted in various test failures due to improper section flags being used in tests, and by the plugin support, so fix that too. The new test fails on many ELF targets that lack .init/fini_array in their scripts. I've just xfailed those. pru-elf oddly defines __init_array_begin rather than __init_array_start. I've left that target as a FAIL, and pj-elf too which reports an error for undefined weak symbols. bfd/ PR 24511 * syms.c (coff_section_type): Only allow '.', '$' and numeric following the standard section names. (bfd_decode_symclass): Prioritize section flag tests in decode_section_type before name tests in coff_section_type. * plugin.c (bfd_plugin_canonicalize_symtab): Init fake_section and fake_common_section using BFD_FAKE_SECTION. Use "fake" as their names and choose standard .text section flags for fake_section. ld/ PR 24511 * testsuite/ld-elf/pr14156a.d: Allow for .init/.fini being a data section on hppa64. * testsuite/ld-elf/pr14156b.d: Likewise. * testsuite/ld-scripts/pr18963.t: Map standard sections to set output section flags. * testsuite/ld-scripts/sane1.t: Likewise. * testsuite/ld-elf/init-fini-arrays.s: Reference __init_array_start and __fini_array_start. Define __start et al. * testsuite/ld-elf/pr24511.d: New test.
2019-05-03 14:06:46 +02:00
2019-05-04 Alan Modra <amodra@gmail.com>
PR 24511
* syms.c (coff_section_type): Only allow '.', '$' and numeric
following the standard section names.
(bfd_decode_symclass): Prioritize section flag tests in
decode_section_type before name tests in coff_section_type.
* plugin.c (bfd_plugin_canonicalize_symtab): Init fake_section
and fake_common_section using BFD_FAKE_SECTION. Use "fake" as
their names and choose standard .text section flags for
fake_section.
Treat the .gnu.debuglink and .gnu.debugaltlink sections as debug sections when reading them in from COFF/PE format files. PR 24493 * coffcode.h (styp_to_sec_flags): Treat .gnu.debuglink and .gnu.debugaltlink sections as debugging sections.
2019-05-02 16:11:39 +02:00
2019-05-02 Nick Clifton <nickc@redhat.com>
PR 24493
* coffcode.h (styp_to_sec_flags): Treat .gnu.debuglink and
.gnu.debugaltlink sections as debugging sections.
PowerPC64 GOT indirect to GOT relative optimisation This implements an optimisation that converts sequences like addis r9,r2,sym@got@ha ld r3,sym@got@l(r9) to addis r9,r2,sym@toc@ha addi r3,r9,sym@toc@l when "sym" is locally defined and can't be overridden. bfd/ * elf64-ppc.c (struct ppc64_elf_obj_tdata): Add has_gotrel. (struct _ppc64_elf_section_data): Likewise. (ppc64_elf_check_relocs): Set above fields. (ppc64_elf_edit_toc): Add a pass over GOT relocs. (ppc64_elf_relocate_section): Edit GOT indirect to GOT relative when possible. ld/ * testsuite/ld-powerpc/elfv2exe.d: Update. * testsuite/ld-powerpc/elfv2so.d: Update. * testsuite/ld-powerpc/tocopt.d: Update. * testsuite/ld-powerpc/tocopt.s: Update. * testsuite/ld-powerpc/tocopt5.d: Update. * testsuite/ld-powerpc/tocopt5.s: Update. * testsuite/ld-powerpc/tocopt7.d: Update. * testsuite/ld-powerpc/tocopt7.s: Update. * testsuite/ld-powerpc/tocopt8.d: Update. * testsuite/ld-powerpc/tocopt8.s: Update.
2019-04-30 09:01:01 +02:00
2019-04-30 Alan Modra <amodra@gmail.com>
* elf64-ppc.c (struct ppc64_elf_obj_tdata): Add has_gotrel.
(struct _ppc64_elf_section_data): Likewise.
(ppc64_elf_check_relocs): Set above fields.
(ppc64_elf_edit_toc): Add a pass over GOT relocs.
(ppc64_elf_relocate_section): Edit GOT indirect to GOT relative
when possible.
Don't complain undefined weak dynamic reference When undefined non-weak references in IR objects are optimized out by LTO, we can have weak dynamic referencs to symbols marked with bfd_link_hash_undefined. We shouldn't complain such undefined weak dynamic references. bfd/ PR ld/24486 * elflink.c (elf_link_output_extsym): Don't complain undefined weak dynamic reference. ld/ PR ld/24486 * testsuite/ld-plugin/lto.exp: Run PR ld/24486 tests. * testsuite/ld-plugin/pr24486a.c: New file. * testsuite/ld-plugin/pr24486b.c: Likewise. * testsuite/ld-plugin/pr24486c.c: Likewise.
2019-04-26 16:52:00 +02:00
2019-04-26 H.J. Lu <hongjiu.lu@intel.com>
PR ld/24486
* elflink.c (elf_link_output_extsym): Don't complain undefined
weak dynamic reference.
[BFD, AArch64] Improve bti/pac plts. This patch aims to improve the definitions of BTI and PAC based PLTs. The following changes are made: * PLT0 does not need PAC instructions since the PLTGOT[2] (and PLTGOT[1]) are readonly so they cannot be corrupted at runtime. Thus both PAC plt0 and BTI+PAC plt0 are removed and we can use basic plt0 and BTI plt0 instead, respectively. * We can remove the extra padding nops when we add the new bti instructions. BTI plt0 and BTI TLSDESC plt are updated. * For better performance PLTn could be padded to 24bytes. Both BTI pltn and PAC pltn are updated. *** bfd/ChangeLog *** 2019-04-25 Sudakshina Das <sudi.das@arm.com> * elfnn-aarch64.c (PLT_BTI_ENTRY_SIZE): Remove. (PLT_BTI_TLSDESC_ENTRY_SIZE): Remove. (PLT_PAC_ENTRY_SIZE, PLT_BTI_PAC_ENTRY_SIZE): Remove. (PLT_BTI_SMALL_ENTRY_SIZE, PLT_PAC_SMALL_ENTRY_SIZE): Update. (elfNN_aarch64_small_plt0_pac_entry): Remove. (elfNN_aarch64_small_plt0_bti_pac_entry): Remove. (elfNN_aarch64_small_plt0_bti_entry): Update. (elfNN_aarch64_small_plt_bti_entry): Update. (elfNN_aarch64_small_plt_pac_entry): Update. (elfNN_aarch64_tlsdesc_small_plt_bti_entry): Update. (setup_plt_values): Setup new entries. (elfNN_aarch64_finish_dynamic_sections): Remove size change. (elfNN_aarch64_plt_sym_val): Likewise. *** ld/ChangeLog *** 2019-04-25 Sudakshina Das <sudi.das@arm.com> * testsuite/ld-aarch64/bti-pac-plt-1.d: Update. * testsuite/ld-aarch64/bti-pac-plt-2.d: Update. * testsuite/ld-aarch64/bti-plt-1.d: Update. * testsuite/ld-aarch64/bti-plt-3.d: Update. * testsuite/ld-aarch64/bti-plt-5.d: Update. * testsuite/ld-aarch64/pac-plt-1.d: Update. * testsuite/ld-aarch64/pac-plt-2.d: Update.
2019-04-25 12:37:25 +02:00
2019-04-25 Sudakshina Das <sudi.das@arm.com>
* elfnn-aarch64.c (PLT_BTI_ENTRY_SIZE): Remove.
(PLT_BTI_TLSDESC_ENTRY_SIZE): Remove.
(PLT_PAC_ENTRY_SIZE, PLT_BTI_PAC_ENTRY_SIZE): Remove.
(PLT_BTI_SMALL_ENTRY_SIZE, PLT_PAC_SMALL_ENTRY_SIZE): Update.
(elfNN_aarch64_small_plt0_pac_entry): Remove.
(elfNN_aarch64_small_plt0_bti_pac_entry): Remove.
(elfNN_aarch64_small_plt0_bti_entry): Update.
(elfNN_aarch64_small_plt_bti_entry): Update.
(elfNN_aarch64_small_plt_pac_entry): Update.
(elfNN_aarch64_tlsdesc_small_plt_bti_entry): Update.
(setup_plt_values): Setup new entries.
(elfNN_aarch64_finish_dynamic_sections): Remove size change.
(elfNN_aarch64_plt_sym_val): Likewise.
RISC-V: Enable 32-bit linux gdb core file support. bfd/ * elfnn-riscv.c (PRSTATUS_SIZE) [ARCH_SIZE==32]: Change from 0 to 204.
2019-04-22 23:17:55 +02:00
2019-04-22 Jim Wilson <jimw@sifive.com>
* elfnn-riscv.c (PRSTATUS_SIZE) [ARCH_SIZE==32]: Change from 0 to 204.
s12z and h8300 no-print-map-discarded fails This tidies the remaining --no-print-map-discarded fails. h8300-elf warns on a section without flags, and s12z doesn't support --gc-sections. bfd/ * elf32-s12z.c (elf_backend_can_gc_sections): Don't define ld/ * testsuite/ld-gc/skip-map-discarded.s: Add section attributes. * testsuite/lib/ld-lib.exp (check_gc_sections_available): Add s12z to list of targets not supporting --gc-sections.
2019-04-19 05:03:46 +02:00
2019-04-19 Alan Modra <amodra@gmail.com>
* elf32-s12z.c (elf_backend_can_gc_sections): Don't define
x86: Suggest -fPIE when not building shared object When PIC is needed, linker should suggest -fPIE, instead of -fPIC, when not building shared object. bfd/ * elf64-x86-64.c (elf_x86_64_need_pic): Suggest -fPIE when not building shared object. * elfxx-x86.c (_bfd_x86_elf_size_dynamic_sections): Likewise. ld/ * testsuite/ld-i386/i386.exp: Run pr18801a and pr18801b instead of pr18801. * testsuite/ld-x86-64/x86-64.exp: Likewise. * testsuite/ld-i386/pr18801.d: Removed. * testsuite/ld-x86-64/pr18801.d: Likewise. * testsuite/ld-i386/pr18801a.d: New file. * testsuite/ld-i386/pr18801b.d: Likewise. * testsuite/ld-x86-64/pr18801a.d: Likewise. * testsuite/ld-x86-64/pr18801b.d: Likewise. * testsuite/ld-x86-64/pie2.d: Suggest -fPIE instead of -fPIC. * testsuite/ld-x86-64/pie2.d: Likewise. * testsuite/ld-x86-64/pr19719.d: Likewise. * testsuite/ld-x86-64/pr19807-2a.d: Likewise. * testsuite/ld-x86-64/pr19969.d: Likewise. * testsuite/ld-x86-64/pr21997-1a.err: Likewise. * testsuite/ld-x86-64/pr21997-1b.err: Likewise. * testsuite/ld-x86-64/pr22001-1a.err: Likewise. * testsuite/ld-x86-64/pr22001-1b.err: Likewise. * testsuite/ld-x86-64/pr22791-1.err: Likewise.
2019-04-17 19:22:19 +02:00
2019-04-17 H.J. Lu <hongjiu.lu@intel.com>
* elf64-x86-64.c (elf_x86_64_need_pic): Suggest -fPIE when not
building shared object.
* elfxx-x86.c (_bfd_x86_elf_size_dynamic_sections): Likewise.
x86: Also check x86 linker_def for non-shared definition Since elf_x86_linker_defined sets linker_def in elf_x86_link_hash_entry for linker defined symbols, SYMBOL_DEFINED_NON_SHARED_P should also check linker_def in elf_x86_link_hash_entry. bfd/ PR ld/24458 * elfxx-x86.h (SYMBOL_DEFINED_NON_SHARED_P): Also check x86 linker_def. ld/ PR ld/24458 * testsuite/ld-x86-64/x86-64.exp: Run PR ld/24458 tests. * testsuite/ld-x86-64/pr24458.s: New file. * testsuite/ld-x86-64/pr24458a-x32.d: Likewise. * testsuite/ld-x86-64/pr24458a.d: Likewise. * testsuite/ld-x86-64/pr24458b-x32.d: Likewise. * testsuite/ld-x86-64/pr24458b.d: Likewise. * testsuite/ld-x86-64/pr24458c-x32.d: Likewise. * testsuite/ld-x86-64/pr24458c.d: Likewise.
2019-04-17 18:08:46 +02:00
2019-04-17 H.J. Lu <hongjiu.lu@intel.com>
PR ld/24458
* elfxx-x86.h (SYMBOL_DEFINED_NON_SHARED_P): Also check x86
linker_def.
[binutils, ARM, 16/16] Add support to VLDR and VSTR of system registers GNU as' Arm backend assumes each mnemonic has a single entry in the instruction table but VLDR (system register) and VSTR (system register) are different instructions than VLDR and VSTR. It is thus necessary to add some form of demultiplexing in the parser. It starts by creating a new operand type OP_VLDR which indicate that the operand is either the existing OP_RVSD operand or a system register. The function parse_operands () then tries these two cases in order, calling the new parse_sys_vldr_vstr for the second case. Since the encoding function is specified in the instruction table entry, it also need to have some sort of demultiplexing. This is done in do_vldr_vstr which either calls the existing do_neon_ldr_str () or calls the new do_t_vldr_vstr_sysreg (). A new internal relocation is needed as well since the offset has a shorter range than in other Thumb coprocessor instructions. Disassembly also requires special care since VSTR (system register) reuse the STC encoding with the coprocessor number 15. Armv8.1-M Mainline ARM manual states that coprocessor 8, 14 and 15 are reserved for floating-point and MVE instructions a feature bit check is added if the coprocessor number is one of this value and we are trying to match a coprocessor instruction (eg. STC) to forbid the match. ChangeLog entries are as follows: *** bfd/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * reloc.c (BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM): New internal relocation. * bfd-in2.h: Regenerate. * libbfd.h: Likewise. *** gas/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/tc-arm.c (parse_sys_vldr_vstr): New function. (OP_VLDR): New enum operand_parse_code enumerator. (parse_operands): Add logic for OP_VLDR. (do_t_vldr_vstr_sysreg): New function. (do_vldr_vstr): Likewise. (insns): Guard VLDR and VSTR by arm_ext_v4t for Thumb mode. (md_apply_fix): Add bound check for VLDR and VSTR co-processor offset. Add masking logic for BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM relocation. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add examples of bad uses of VLDR and VSTR. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error messages for above bad uses. * testsuite/gas/arm/archv8m_1m-cmse-main.s: Add examples of VLDR and VSTR valid uses. * testsuite/gas/arm/archv8m_1m-cmse-main.d: Add disassembly for the above examples. *** opcodes/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * arm-dis.c (coprocessor_opcodes): Document new %J and %K format specifier. Add entries for VLDR and VSTR of system registers. (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in coprocessor instructions on Armv8.1-M Mainline targets. Add handling of %J and %K format specifier.
2019-04-15 13:23:24 +02:00
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* reloc.c (BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM): New internal
relocation.
* bfd-in2.h: Regenerate.
* libbfd.h: Likewise.
[binutils, ARM, 12/16] Scalar Low Overhead loop instructions for Armv8.1-M Mainline s patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This patch adds support to the Scalar low overhead loop instructions: LE WLS DLS We also add a new assembler resolvable relocation bfd_reloc_code_real enum for the 12-bit branch offset used in these instructions. ChangeLog entries are as follows: *** bfd/ChnageLog *** 2019-04-12 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_ARM_THUMB_LOOP12): New. * bfd-in2.h: Regenerated. * libbfd.h: Regenerated. *** gas/ChangeLog *** 2019-04-12 Sudakshina Das <sudi.das@arm.com> Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (operand_parse_code): Add OP_LR and OP_oLR for the LR operand and optional LR operand. (parse_operands): Add switch cases for OP_LR and OP_oLR for both type checking and value checking. (encode_thumb32_addr_mode): New entries for DLS, WLS and LE. (v8_1_loop_reloc): New helper function for handling labels for the low overhead loop instructions. (do_t_loloop): New function to encode DLS, WLS and LE. (insns): New entries for WLS, DLS and LE. (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_LOOP12. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. * testsuite/gas/arm/armv8_1-m-tloop.s: New. * testsuite/gas/arm/armv8_1-m-tloop.d: New. * testsuite/gas/arm/armv8_1-m-tloop-bad.s: New. * testsuite/gas/arm/armv8_1-m-tloop-bad.d: New. * testsuite/gas/arm/armv8_1-m-tloop-bad.l: New. *** opcodes/ChangeLog *** 2019-04-12 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %P and %Q patterns.
2019-04-15 12:58:47 +02:00
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_LOOP12): New.
* bfd-in2.h: Regenerated.
* libbfd.h: Regenerated.
[binutils, ARM, 11/16] New BFCSEL instruction for Armv8.1-M Mainline s patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This patch adds the BFCSEL instruction. It also adds a local relocation with a new bfd_reloc_code_real enum. ChangeLog entries are as follows: 2019-04-15 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_THUMB_PCREL_BFCSEL): New relocation. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (T16_32_TAB): New entriy for bfcsel. (do_t_v8_1_branch): New switch case for bfcsel. (toU): Define. (insns): New instruction for bfcsel. (md_pcrel_from_section): New switch case for BFD_RELOC_THUMB_PCREL_BFCSEL. (md_appdy_fix): Likewise (tc_gen_reloc): Likewise. * testsuite/gas/arm/armv8_1-m-bfcsel.d: New. * testsuite/gas/arm/armv8_1-m-bfcsel.s: New. *** ld/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * testsuite/ld-arm/bfcsel.s: New. * testsuite/ld-arm/bfcsel.d: New. * testsuite/ld-arm/arm-elf.exp: Add above test. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (thumb32_opcodes): New instruction bfcsel. (print_insn_thumb32): Edit the switch case for %Z.
2019-04-15 12:53:25 +02:00
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_THUMB_PCREL_BFCSEL): New relocation.
* bfd-in2.h: Regenerated.
* libbfd.h: Likewise.
[binutils, ARM, 10/16] BFCSEL infrastructure with new global reloc R_ARM_THM_BF12 This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This adds infrastructure for the BFCSEL instructions which is one of the first instructions in Arm that have more than one relocations in them. This adds a new relocation R_ARM_THM_BF12. The inconsistency between external R_ARM_THM_BF12 and internal BFD_RELOC_ARM_THUMB_BF13 is because internally we count the static bit-0 of the immediate and we don't externally. ChangeLog entries are as follows : ChangeLog entries are as follows : *** bfd/ChnageLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_ARM_THUMB_BF13): New. * bfd-in2.h: Regenerated. * libbfd.h: Regenerated. * elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF13. (elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF13 and R_ARM_THM_BF12 together. (elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF13. *** elfcpp/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * arm.h (R_ARM_THM_BF12): New relocation code. *** gas/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_BF13. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. *** include/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF12. *** opcodes/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
2019-04-15 12:46:54 +02:00
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_BF13): New.
* bfd-in2.h: Regenerated.
* libbfd.h: Regenerated.
* elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF13.
(elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF13
and R_ARM_THM_BF12 together.
(elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF13.
[binutils, ARM, 8/16] BFL infrastructure with new global reloc R_ARM_THM_BF18 This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This adds infrastructure for the BFL instructions which is one of the first instructions in Arm that have more than one relocations in them. This adds a new relocation R_ARM_THM_BF18. The inconsistency between external R_ARM_THM_BF18 and internal BFD_RELOC_ARM_THUMB_BF19 is because internally we count the static bit-0 of the immediate and we don't externally. ChangeLog entries are as follows : *** bfd/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_ARM_THUMB_BF19): New * libbfd.h: Regenerated. * bfd-in2.h: Regenerated. * bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF18. (elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF19 and R_ARM_THM_BF18 together. (elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF19. *** elfcpp/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm.h (R_ARM_THM_BF18): New relocation code. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_BF19. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. *** include/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF18. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
2019-04-15 12:37:51 +02:00
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_BF19): New
* libbfd.h: Regenerated.
* bfd-in2.h: Regenerated.
* bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF18.
(elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF19
and R_ARM_THM_BF18 together.
(elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF19.
[binutils, ARM, 5/16] BF insns infrastructure with new global reloc R_ARM_THM_BF16 This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This adds infrastructure for the BF instructions which is one of the first instructions in Arm that have more than one relocations in them. This is the third infrastructure patch that adds a new relocation R_ARM_THM_BF16. The inconsistency between external R_ARM_THM_BF16 and internal BFD_RELOC_ARM_THUMB_BF17 is because internally we count the static bit-0 of the immediate and we don't externally. ChangeLog entries are as follows : *** bfd/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_ARM_THUMB_BF17): New enum. * bfd-in2.h: Regenerated. * libbfd.h: Regenerated. * bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF16. (elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF17 and R_ARM_THM_BF16 together. (get_value_helper): New reloc helper. (elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF16. *** elfcpp/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm.h (R_ARM_THM_BF16): New relocation code. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_BF17. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. *** include/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF16. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
2019-04-15 12:18:57 +02:00
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_BF17): New enum.
* bfd-in2.h: Regenerated.
* libbfd.h: Regenerated.
* bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF16.
(elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF17
and R_ARM_THM_BF16 together.
(get_value_helper): New reloc helper.
(elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF16.
[binutils, ARM, 3/16] BF insns infrastructure with new bfd_reloc_code_real for fallback branch This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This adds infrastructure for the Branch Future instructions (BF, BFX, BFL, BFLX, BFCSEL). These are the first instructions in ARM that have more than one relocations in them. This is the first infrastructure patch that adds a new bfd_reloc_code_real enum for the fallback branch offset. This is common for all such instructions and needs to be resolvable by the assembler. ChangeLog entries are as follows : *** bfd/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_THUMB_PCREL_BRANCH5): New enum. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (md_pcrel_from_section): New switch case for BFD_RELOC_THUMB_PCREL_BRANCH5. (v8_1_branch_value_check): New function to check branch offsets. (md_appdy_fix): New switch case for BFD_RELOC_THUMB_PCREL_BRANCH5. (tc_gen_reloc): Likewise. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
2019-04-15 12:06:30 +02:00
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_THUMB_PCREL_BRANCH5): New enum.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
[binutils, ARM, 1/16] Add support for Armv8.1-M Mainline CLI The patch is straightforward, it does the following: - support the new Tag_CPU_arch build attribute value, ie.: + declare the new value + update all the asserts forcing logic to be reviewed for new architectures + create a corresponding bfd_mach_arm_8_1M_MAIN enumerator in bfd and add mapping from Tag_CPU_arch to it + teach readelf about new Tag_CPU_arch value - declare armv8.1-m.main as a supported architecture value - define Armv8.1-M Mainline in terms of feature bits available - tell objdump mapping from bfd_mach_arm_8_1M_MAIN enumerator to feature bits available - update architecture-specific logic in gas and bfd guarded by the asserts mentioned above. - tests for all the above ChangeLog entries are as follows: *** bfd/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * archures.c (bfd_mach_arm_8_1M_MAIN): Define. * bfd-in2.h: Regenerate. * cpu-arm.c (arch_info_struct): Add entry for Armv8.1-M Mainline. * elf32-arm.c (using_thumb_only): Return true for Armv8.1-M Mainline and update assert. (using_thumb2): Likewise. (using_thumb2_bl): Update assert. (arch_has_arm_nop): Likewise. (bfd_arm_get_mach_from_attributes): Add case for Armv8.1-M Mainline. (tag_cpu_arch_combine): Add logic for Armv8.1-M Mainline merging. *** binutils/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * readelf.c (arm_attr_tag_CPU_arch): Add entry for Armv8.1-M Mainline. *** gas/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/tc-arm.c (cpu_arch_ver): Add entry for Armv8.1-M Mainline Tag_CPU_arch build attribute value. Reindent. (get_aeabi_cpu_arch_from_fset): Update assert. (aeabi_set_public_attributes): Update assert for Tag_DIV_use logic. * testsuite/gas/arm/attr-march-armv8_1-m.main.d: New test. *** include/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * elf/arm.h (TAG_CPU_ARCH_V8_1M_MAIN): new macro. (MAX_TAG_CPU_ARCH): Set value to above macro. * opcode/arm.h (ARM_EXT2_V8_1M_MAIN): New macro. (ARM_AEXT_V8_1M_MAIN): Likewise. (ARM_AEXT2_V8_1M_MAIN): Likewise. (ARM_ARCH_V8_1M_MAIN): Likewise. *** ld/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * testsuite/ld-arm/attr-merge-13.attr: New test. * testsuite/ld-arm/attr-merge-13a.s: New test. * testsuite/ld-arm/attr-merge-13b.s: New test. *** opcodes/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
2019-04-15 11:54:42 +02:00
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* archures.c (bfd_mach_arm_8_1M_MAIN): Define.
* bfd-in2.h: Regenerate.
* cpu-arm.c (arch_info_struct): Add entry for Armv8.1-M Mainline.
* elf32-arm.c (using_thumb_only): Return true for Armv8.1-M Mainline
and update assert.
(using_thumb2): Likewise.
(using_thumb2_bl): Update assert.
(arch_has_arm_nop): Likewise.
(bfd_arm_get_mach_from_attributes): Add case for Armv8.1-M Mainline.
(tag_cpu_arch_combine): Add logic for Armv8.1-M Mainline merging.
x86: Add -z cet-report=[none|warning|error] Add -z cet-report=[none|warning|error] to report the missing Intel Indirect Branch Tracking (IBT) and Shadow Stack (SHSTK) properties in input .note.gnu.property section. -z cet-report=none, which is the default, will make the linker not report missing properties in input files. -z cet-report=warning will make the linker issue a warning for missing properties in input files. -z cet-report=error will make the linker issue an error for missing properties in input files. Note that -z ibt will turn off the missing IBT property report and -z shstk will turn off the missing SHSTK property report. Supported for Linux/i386 and Linux/x86_64. bfd/ * elf-linker-x86.h (elf_x86_cet_report): New. (elf_linker_x86_params): Add cet_report. * elfxx-x86.c (_bfd_x86_elf_link_setup_gnu_properties): Report missing IBT and SHSTK properties if needed. ld/ * ld.texi: Document -z cet-report=[none|warning|error]. * emulparams/cet.sh: Add -z cet-report=[none|warning|error]. * testsuite/ld-i386/i386.exp: Run -z cet-report=[warning|error] tests. * testsuite/ld-x86-64/x86-64.exp: Likewise. * testsuite/ld-i386/property-x86-cet1.d: New file. * testsuite/ld-i386/property-x86-cet2a.d: Likewise. * testsuite/ld-i386/property-x86-cet2b.d: Likewise. * testsuite/ld-i386/property-x86-cet3a.d: Likewise. * testsuite/ld-i386/property-x86-cet3b.d: Likewise. * testsuite/ld-i386/property-x86-cet4a.d: Likewise. * testsuite/ld-i386/property-x86-cet4b.d: Likewise. * testsuite/ld-i386/property-x86-cet5a.d: Likewise. * testsuite/ld-i386/property-x86-cet5b.d: Likewise. * testsuite/ld-i386/property-x86-cet6.d: Likewise. * testsuite/ld-x86-64/property-x86-cet.s: Likewise. * testsuite/ld-x86-64/property-x86-cet1-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet1.d: Likewise. * testsuite/ld-x86-64/property-x86-cet2a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet2a.d: Likewise. * testsuite/ld-x86-64/property-x86-cet2b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet2b.d: Likewise. * testsuite/ld-x86-64/property-x86-cet3a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet3a.d: Likewise. * testsuite/ld-x86-64/property-x86-cet3b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet3b.d: Likewise. * testsuite/ld-x86-64/property-x86-cet4a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet4a.d: Likewise. * testsuite/ld-x86-64/property-x86-cet4b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet4b.d: Likewise. * testsuite/ld-x86-64/property-x86-cet5a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet5a.d: Likewise. * testsuite/ld-x86-64/property-x86-cet5b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet5b.d: Likewise. * testsuite/ld-x86-64/property-x86-cet6-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet6.d: Likewise.
2019-04-11 17:18:51 +02:00
2019-04-11 H.J. Lu <hongjiu.lu@intel.com>
* elf-linker-x86.h (elf_x86_cet_report): New.
(elf_linker_x86_params): Add cet_report.
* elfxx-x86.c (_bfd_x86_elf_link_setup_gnu_properties): Report
missing IBT and SHSTK properties if needed.
Check corrupt VTENTRY entry in bfd_elf_gc_record_vtentry Instead of BFD_ASSERT (h != NULL) with ld: BFD ... assertion fail .../bfd/elf64-x86-64.c:2562 ld: bad.o: invalid string offset 50331648 >= 371 for section `nterp' check corrupt VTENTRY entry in bfd_elf_gc_record_vtentry with ld: bad.o: section 'g': corrupt VTENTRY entry * elf-m10300.c (mn10300_elf_check_relocs): Remove BFD_ASSERT of "h != NULL". Don't check "h != NULL" before calling. bfd_elf_gc_record_vtentry. * elf32-arm.c (elf32_arm_check_relocs): Likewise. * elf32-bfin.c (bfin_check_relocs): Likewise. * elf32-cris.c (cris_elf_check_relocs): Likewise. * elf32-csky.c (csky_elf_check_relocs): Likewise. * elf32-d10v.c (elf32_d10v_check_relocs): Likewise. * elf32-dlx.c (elf32_dlx_check_relocs): Likewise. * elf32-fr30.c (fr30_elf_check_relocs): Likewise. * elf32-frv.c (elf32_frv_check_relocs): Likewise. * elf32-hppa.c (elf32_hppa_check_relocs): Likewise. * elf32-i386.c (elf_i386_check_relocs): Likewise. * elf32-iq2000.c (iq2000_elf_check_relocs): Likewise. * elf32-m32r.c (m32r_elf_check_relocs): Likewise. * elf32-m68hc1x.c (elf32_m68hc11_check_relocs): Likewise. * elf32-m68k.c (elf_m68k_check_relocs): Likewise. * elf32-mcore.c (mcore_elf_check_relocs): Likewise. * elf32-metag.c (elf_metag_check_relocs): Likewise. * elf32-or1k.c (or1k_elf_check_relocs): Likewise. * elf32-ppc.c (ppc_elf_check_relocs): Likewise. * elf32-s390.c (elf_s390_check_relocs): Likewise. * elf32-sh.c (sh_elf_check_relocs): Likewise. * elf32-v850.c (v850_elf_check_relocs): Likewise. * elf32-vax.c (elf_vax_check_relocs): Likewise. * elf32-xstormy16.c (xstormy16_elf_check_relocs): Likewise. * elf32-xtensa.c (elf_xtensa_check_relocs): Likewise. * elf64-mmix.c (mmix_elf_check_relocs): Likewise. * elf64-ppc.c (ppc64_elf_check_relocs): Likewise. * elf64-s390.c (elf_s390_check_relocs): Likewise. * elf64-x86-64.c (elf_s390_check_relocs): Likewise. * elfxx-mips.c (_bfd_mips_elf_check_relocs): Likewise. * elfxx-sparc.c (_bfd_sparc_elf_check_relocs): Likewise. * elflink.c (bfd_elf_gc_record_vtinherit): Check for corrupt VTENTRY entry.
2019-04-11 15:44:53 +02:00
2019-04-11 H.J. Lu <hongjiu.lu@intel.com>
Add PR ld/24436 to ChangeLog entry
2019-04-11 16:53:55 +02:00
PR ld/24436
Check corrupt VTENTRY entry in bfd_elf_gc_record_vtentry Instead of BFD_ASSERT (h != NULL) with ld: BFD ... assertion fail .../bfd/elf64-x86-64.c:2562 ld: bad.o: invalid string offset 50331648 >= 371 for section `nterp' check corrupt VTENTRY entry in bfd_elf_gc_record_vtentry with ld: bad.o: section 'g': corrupt VTENTRY entry * elf-m10300.c (mn10300_elf_check_relocs): Remove BFD_ASSERT of "h != NULL". Don't check "h != NULL" before calling. bfd_elf_gc_record_vtentry. * elf32-arm.c (elf32_arm_check_relocs): Likewise. * elf32-bfin.c (bfin_check_relocs): Likewise. * elf32-cris.c (cris_elf_check_relocs): Likewise. * elf32-csky.c (csky_elf_check_relocs): Likewise. * elf32-d10v.c (elf32_d10v_check_relocs): Likewise. * elf32-dlx.c (elf32_dlx_check_relocs): Likewise. * elf32-fr30.c (fr30_elf_check_relocs): Likewise. * elf32-frv.c (elf32_frv_check_relocs): Likewise. * elf32-hppa.c (elf32_hppa_check_relocs): Likewise. * elf32-i386.c (elf_i386_check_relocs): Likewise. * elf32-iq2000.c (iq2000_elf_check_relocs): Likewise. * elf32-m32r.c (m32r_elf_check_relocs): Likewise. * elf32-m68hc1x.c (elf32_m68hc11_check_relocs): Likewise. * elf32-m68k.c (elf_m68k_check_relocs): Likewise. * elf32-mcore.c (mcore_elf_check_relocs): Likewise. * elf32-metag.c (elf_metag_check_relocs): Likewise. * elf32-or1k.c (or1k_elf_check_relocs): Likewise. * elf32-ppc.c (ppc_elf_check_relocs): Likewise. * elf32-s390.c (elf_s390_check_relocs): Likewise. * elf32-sh.c (sh_elf_check_relocs): Likewise. * elf32-v850.c (v850_elf_check_relocs): Likewise. * elf32-vax.c (elf_vax_check_relocs): Likewise. * elf32-xstormy16.c (xstormy16_elf_check_relocs): Likewise. * elf32-xtensa.c (elf_xtensa_check_relocs): Likewise. * elf64-mmix.c (mmix_elf_check_relocs): Likewise. * elf64-ppc.c (ppc64_elf_check_relocs): Likewise. * elf64-s390.c (elf_s390_check_relocs): Likewise. * elf64-x86-64.c (elf_s390_check_relocs): Likewise. * elfxx-mips.c (_bfd_mips_elf_check_relocs): Likewise. * elfxx-sparc.c (_bfd_sparc_elf_check_relocs): Likewise. * elflink.c (bfd_elf_gc_record_vtinherit): Check for corrupt VTENTRY entry.
2019-04-11 15:44:53 +02:00
* elf-m10300.c (mn10300_elf_check_relocs): Remove BFD_ASSERT of
"h != NULL". Don't check "h != NULL" before calling.
bfd_elf_gc_record_vtentry.
* elf32-arm.c (elf32_arm_check_relocs): Likewise.
* elf32-bfin.c (bfin_check_relocs): Likewise.
* elf32-cris.c (cris_elf_check_relocs): Likewise.
* elf32-csky.c (csky_elf_check_relocs): Likewise.
* elf32-d10v.c (elf32_d10v_check_relocs): Likewise.
* elf32-dlx.c (elf32_dlx_check_relocs): Likewise.
* elf32-fr30.c (fr30_elf_check_relocs): Likewise.
* elf32-frv.c (elf32_frv_check_relocs): Likewise.
* elf32-hppa.c (elf32_hppa_check_relocs): Likewise.
* elf32-i386.c (elf_i386_check_relocs): Likewise.
* elf32-iq2000.c (iq2000_elf_check_relocs): Likewise.
* elf32-m32r.c (m32r_elf_check_relocs): Likewise.
* elf32-m68hc1x.c (elf32_m68hc11_check_relocs): Likewise.
* elf32-m68k.c (elf_m68k_check_relocs): Likewise.
* elf32-mcore.c (mcore_elf_check_relocs): Likewise.
* elf32-metag.c (elf_metag_check_relocs): Likewise.
* elf32-or1k.c (or1k_elf_check_relocs): Likewise.
* elf32-ppc.c (ppc_elf_check_relocs): Likewise.
* elf32-s390.c (elf_s390_check_relocs): Likewise.
* elf32-sh.c (sh_elf_check_relocs): Likewise.
* elf32-v850.c (v850_elf_check_relocs): Likewise.
* elf32-vax.c (elf_vax_check_relocs): Likewise.
* elf32-xstormy16.c (xstormy16_elf_check_relocs): Likewise.
* elf32-xtensa.c (elf_xtensa_check_relocs): Likewise.
* elf64-mmix.c (mmix_elf_check_relocs): Likewise.
* elf64-ppc.c (ppc64_elf_check_relocs): Likewise.
* elf64-s390.c (elf_s390_check_relocs): Likewise.
* elf64-x86-64.c (elf_s390_check_relocs): Likewise.
* elfxx-mips.c (_bfd_mips_elf_check_relocs): Likewise.
* elfxx-sparc.c (_bfd_sparc_elf_check_relocs): Likewise.
* elflink.c (bfd_elf_gc_record_vtinherit): Check for corrupt
VTENTRY entry.
PR24435, buffer overflow reading dynamic entries PR 24435 * elflink.c (elf_link_add_object_symbols): Don't read partial dynamic entries from fuzzed objects.
2019-04-11 12:12:31 +02:00
2019-04-11 Alan Modra <amodra@gmail.com>
PR 24435
* elflink.c (elf_link_add_object_symbols): Don't read partial
dynamic entries from fuzzed objects.
AArch64: When DF_BIND_NOW don't use TLSDESC GOT value. When using DF_BIND_NOW on AArch64 we don't reserve the GOT slot for a TLSDESC, but we still emitted DT_TLSDESC_GOT and DT_TLSDESC_PLT. This caused random memory corruption as the "special" value of (bfd_vma)-1 would be set for dt_tlsdesc_got. Since we don't have a value of dt_tlsdesc_got I also don't emit DT_TLSDESC_PLT now becuase it would point to an incomplete PLT. To be able to write the PLT entry DT_TLSDESC_GOT is needed and since we don't have one we can't write the PLT entry either. It is my understanding that GLIBC doesn't need these two entries when not lazy loading. Conversely AArch32 does not reserve neither the GOT not the PLT slot when doing DF_BIND_NOW. AArch32 does not need these checks because these values are initialized to 0 and so the if (...) checks don't pass, but on AArch64 these are initialized to (bfd_vma)-1 and thus we need some extra checks. bfd/ChangeLog: PR ld/24302 * elfnn-aarch64.c (elfNN_aarch64_size_dynamic_sections): Don't emit DT_TLSDESC_GOT and DT_TLSDESC_PLT when DF_BIND_NOW. (elfNN_aarch64_finish_dynamic_sections): Don't write PLT if DF_BIND_NOW. ld/ChangeLog: PR ld/24302 * testsuite/ld-aarch64/aarch64-elf.exp: Add new test. * testsuite/ld-aarch64/tls-relax-gdesc-le-now.d: New test.
2019-04-11 12:27:28 +02:00
2019-04-11 Tamar Christina <tamar.christina@arm.com>
PR ld/24302
* elfnn-aarch64.c (elfNN_aarch64_size_dynamic_sections): Don't emit
DT_TLSDESC_GOT and DT_TLSDESC_PLT when DF_BIND_NOW.
(elfNN_aarch64_finish_dynamic_sections): Don't write PLT if DF_BIND_NOW.
PR24427, bfd/doc/chew.c reads uninitialized memory and subtracts from function pointer PR 24427 * doc/chew.c (free_words): Correctly free "push_text" strings.
2019-04-10 10:47:37 +02:00
2019-04-10 Michael Forney <mforney@mforney.org>
PR 24427
* doc/chew.c (free_words): Correctly free "push_text" strings.
x86: Remove i386-*-kaos* and i386-*-chaos targets Remove i386-*-kaos* and i386-*-chaos targets since they are no longer supported by config.sub: $ .../config.sub i386-kaos Invalid configuration `i386-kaos': system `kaos' not recognized $ .../config.sub i386-chaos Invalid configuration `i386-chaos': system `chaos' not recognized $ bfd/ * config.bfd: Remove i[3-7]86-*-kaos* and i[3-7]86-*-chaos targets. gas/ * configure.tgt: Remove i386-*-kaos* and i386-*-chaos targets. * testsuite/gas/i386/i386.exp: Remove *-*-caos* and "*-*-kaos* check. ld/ * Makefile.am (ALL_EMULATION_SOURCES): Remove eelf_i386_chaos.c. (eelf_i386_chaos.c): Removed. * Makefile.in: Regenerated. * configure.tgt: Remove i[3-7]86-*-kaos*. * emulparams/elf_i386_chaos.sh: Removed.
2019-04-08 20:58:51 +02:00
2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
* config.bfd: Remove i[3-7]86-*-kaos* and i[3-7]86-*-chaos targets.
Fix x86_64-rdos build fail x86_64-rdos is one of the few x86_64 targets that is 64-bit only and the x86_64 configure entries don't depend on elf-vxworks.lo. This results in undefined references from elfxx-x86.o. * configure.ac (elfxx_x86): Define and use. * configure: Regenerate.
2019-04-08 06:31:17 +02:00
2019-04-08 Alan Modra <amodra@gmail.com>
* configure.ac (elfxx_x86): Define and use.
* configure: Regenerate.
x86: Move x86-specific linker options to elf_linker_x86_params Remove x86-specific linker options from bfd_link_info and put them in elf_linker_x86_params. Add _bfd_elf_linker_x86_set_options to pass x86-specific linker options from ld to bfd. bfd/ * elf-linker-x86.h: New file. * elf32-i386.c (elf_i386_convert_load_reloc): Use htab->params to get x86-specific linker options. * elf64-x86-64.c (elf_x86_64_convert_load_reloc): Likewise. (elf_x86_64_check_relocs): Likewise. (elf_x86_64_relocate_section): Likewise. (elf_x86_64_link_setup_gnu_properties): Likewise. * elfxx-x86.c (_bfd_x86_elf_merge_gnu_properties): Likewise. (_bfd_x86_elf_link_setup_gnu_properties): Likewise. (_bfd_elf_linker_x86_set_options): New function. * elfxx-x86.h: Include "elf-linker-x86.h". (elf_x86_link_hash_table): Add params. include/ * bfdlink.h (bfd_link_info): Remove x86-specific linker options. ld/ * Makefile.am (ELF_X86_DEPS): Add $(srcdir)/emultempl/elf-x86.em. (eelf_i386_sol2.c): Also depend on $(srcdir)/emultempl/solaris2-x86.em. (eelf_x86_64_sol2.c): Likewise. * Makefile.in: Regenerated. * emulparams/call_nop.sh: Set x86-specific linker options via params. * emulparams/cet.sh: Likewise. * emulparams/reloc_overflow.sh: Likewise. * emulparams/elf32_x86_64.sh (EXTRA_EM_FILE): New. Set to "elf-x86". * emulparams/elf_i386.sh: Likewise. * emulparams/elf_i386_be.sh: Likewise. * emulparams/elf_i386_chaos.sh: Likewise. * emulparams/elf_i386_ldso.sh: Likewise. * emulparams/elf_i386_vxworks.sh: Likewise. * emulparams/elf_iamcu.sh: Likewise. * emulparams/elf_k1om.sh: Likewise. * emulparams/elf_l1om.sh: Likewise. * emulparams/elf_x86_64.sh: Likewise. * emulparams/elf_i386_sol2.sh (EXTRA_EM_FILE): Changed to "solaris2-x86". * emulparams/elf_x86_64_sol2.sh: Likewise. * emultempl/elf-x86.em: New file. * emultempl/solaris2-x86.em: Likewise. * emultempl/elf32.em (gld${EMULATION_NAME}_before_parse): Don't set link_info.call_nop_byte.
2019-04-06 16:25:10 +02:00
2019-04-06 H.J. Lu <hongjiu.lu@intel.com>
* elf-linker-x86.h: New file.
* elf32-i386.c (elf_i386_convert_load_reloc): Use htab->params
to get x86-specific linker options.
* elf64-x86-64.c (elf_x86_64_convert_load_reloc): Likewise.
(elf_x86_64_check_relocs): Likewise.
(elf_x86_64_relocate_section): Likewise.
(elf_x86_64_link_setup_gnu_properties): Likewise.
* elfxx-x86.c (_bfd_x86_elf_merge_gnu_properties): Likewise.
(_bfd_x86_elf_link_setup_gnu_properties): Likewise.
(_bfd_elf_linker_x86_set_options): New function.
* elfxx-x86.h: Include "elf-linker-x86.h".
(elf_x86_link_hash_table): Add params.
BFD whitespace fixes * coff-i386.c, * coff-x86_64.c, * coffgen.c, * dwarf2.c, * elf-m10200.c, * elf.c, * elf32-arm.c, * elf32-bfin.c, * elf32-csky.c, * elf32-m32r.c, * elf32-microblaze.c, * elf32-pru.c, * elf32-rx.c, * elf32-xgate.c, * elf64-sparc.c, * elfnn-ia64.c, * elfxx-riscv.c, * elfxx-sparc.c, * linker.c, * mach-o.c, * pe-x86_64.c, * pei-x86_64.c, * plugin.c: Whitespace fixes.
2019-04-02 08:08:20 +02:00
2019-04-03 Alan Modra <amodra@gmail.com>
* coff-i386.c, * coff-x86_64.c, * coffgen.c, * dwarf2.c,
* elf-m10200.c, * elf.c, * elf32-arm.c, * elf32-bfin.c,
* elf32-csky.c, * elf32-m32r.c, * elf32-microblaze.c, * elf32-pru.c,
* elf32-rx.c, * elf32-xgate.c, * elf64-sparc.c, * elfnn-ia64.c,
* elfxx-riscv.c, * elfxx-sparc.c, * linker.c, * mach-o.c,
* pe-x86_64.c, * pei-x86_64.c, * plugin.c: Whitespace fixes.
RISC-V: Don't check ABI flags if no code section. This fixes a glib build failure reported in PR 24389. Using ld -b binary creates an object file with no elf header flags set which has the wrong ABI info for riscv64-linux. But the file also has no code sections, so I added code borrowed from the arm port that only checks the ELF header ABI flags if there is a code section. bfd/ PR 24389 * elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Move read of ELF header flags to after check for ELF object file. Loop through sections looking for code sections, if none, then skip ABI checks.
2019-04-02 22:30:07 +02:00
2019-04-02 Jim Wilson <jimw@sifive.com>
PR 24389
* elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Move read of
ELF header flags to after check for ELF object file. Loop through
sections looking for code sections, if none, then skip ABI checks.
RISC-V: Relax tail/j to c.j for RV64. 2019-03-30 Andrew Waterman <andrew@sifive.com> bfd/ * elfnn-riscv.c (_bfd_riscv_relax_call): Only check ARCH_SIZE for rd == X_RA case.
2019-03-30 18:12:12 +01:00
2019-03-30 Andrew Waterman <andrew@sifive.com>
* elfnn-riscv.c (_bfd_riscv_relax_call): Only check ARCH_SIZE for
rd == X_RA case.
bfd: xtensa: fix shrink_dynamic_reloc_sections for export-dynamic shrink_dynamic_reloc_sections must remove PLT entry that was created for an undefined weak symbol in the presence of --export-dynamic option when relaxation coalesces literals pointing to that symbol. This fixes the following assertion: ld: BFD (GNU Binutils) 2.31.1 internal error, aborting at elf32-xtensa.c:3292 in elf_xtensa_finish_dynamic_sections 2019-03-29 Max Filippov <jcmvbkbc@gmail.com> bfd/ * elf32-xtensa.c (shrink_dynamic_reloc_sections): Add info->export_dynamic to the conditional. ld/ * testsuite/ld-xtensa/relax-undef-weak-pie-export-dynamic.d: New test definition. * testsuite/ld-xtensa/xtensa.exp (relax-undef-weak-pie-export-dynamic): Add new test.
2019-03-29 01:03:57 +01:00
2019-03-29 Max Filippov <jcmvbkbc@gmail.com>
* elf32-xtensa.c (shrink_dynamic_reloc_sections): Add
info->export_dynamic to the conditional.
PR24392, Clang warning Wtautological-constant-out-of-range-compare PR 24392 * configure.ac: Invoke AC_CHECK_SIZEOF(int). * configure: Regenerate. * coffgen.c (coff_get_reloc_upper_bound): Replace gcc diagnostic workaround with SIZEOF_LONG vs. SIZEOF_INT check. * elf.c (_bfd_elf_get_reloc_upper_bound): Likewise. * elf64-sparc.c (elf64_sparc_get_reloc_upper_bound): Likewise. * mach-o.c (bfd_mach_o_get_reloc_upper_bound): Likewise.
2019-03-28 07:23:32 +01:00
2019-03-28 Alan Modra <amodra@gmail.com>
PR 24392
* configure.ac: Invoke AC_CHECK_SIZEOF(int).
* configure: Regenerate.
* coffgen.c (coff_get_reloc_upper_bound): Replace gcc diagnostic
workaround with SIZEOF_LONG vs. SIZEOF_INT check.
* elf.c (_bfd_elf_get_reloc_upper_bound): Likewise.
* elf64-sparc.c (elf64_sparc_get_reloc_upper_bound): Likewise.
* mach-o.c (bfd_mach_o_get_reloc_upper_bound): Likewise.
RISC-V: Fix linker crash in section symbol check. sym is only set for local symbols. h is only set for global symbols. Gas won't let me create a global section symbol, but bfd appears to have some support for that, and I can't rule out that other assemblers might do this. So we need to support both, and verify sym and h are non-NULL before using. bfd/ PR 24365 * elfnn-riscv.c (riscv_elf_relocate_section): For STT_SECTION check, verify sym non-NULL before using. Add identical check using h.
2019-03-21 23:08:48 +01:00
2019-03-21 Jim Wilson <jimw@sifive.com>
PR 24365
* elfnn-riscv.c (riscv_elf_relocate_section): For STT_SECTION check,
verify sym non-NULL before using. Add identical check using h.
[BFD, AArch64, x86] Improve warning for --force-bti The AArch64 linker option to turn on BTI (--force-bti) warns in case there are input objects which have a missing GNU NOTE section for BTI. This patch is trying to improve the warnings that come out. In order to do so, I propose adding a new argument to elf_merge_gnu_properties and the backend function merge_gnu_properties. This new argument makes sure that we now pass both the objects along with the properties to which they belong to. The x86 backend function has also been updated to match this change. *** bfd/ChangeLog *** 2019-03-21 Sudakshina Das <sudi.das@arm.com> * elf-bfd.h (struct elf_backend_data): Add argument to merge_gnu_properties. * elf-properties.c (elf_merge_gnu_properties): Add argument to itself and while calling bed->merge_gnu_properties. (elf_merge_gnu_property_list): Update the calls for elf_merge_gnu_properties. * elfnn-aarch64.c (elfNN_aarch64_merge_gnu_properties): Update handling of --force-bti warning and add argument. * elfxx-aarch64.c (_bfd_aarch64_elf_link_setup_gnu_properties): Add warning. * elfxx-x86.c (_bfd_x86_elf_merge_gnu_properties): Add argument. * elfxx-x86.h (_bfd_x86_elf_merge_gnu_properties): Likewise in declaration. *** ld/ChangeLog *** 2019-03-21 Sudakshina Das <sudi.das@arm.com> * testsuite/ld-aarch64/aarch64-elf.exp: Add new test. * testsuite/ld-aarch64/bti-plt-1.s: Add .ifdef for PAC note section. * testsuite/ld-aarch64/bti-plt-6.d: Update warning. * testsuite/ld-aarch64/bti-plt-7.d: Likewise. * testsuite/ld-aarch64/bti-warn.d: New test.
2019-03-21 17:20:21 +01:00
2019-03-21 Sudakshina Das <sudi.das@arm.com>
* elf-bfd.h (struct elf_backend_data): Add argument to
merge_gnu_properties.
* elf-properties.c (elf_merge_gnu_properties): Add argument to
itself and while calling bed->merge_gnu_properties.
(elf_merge_gnu_property_list): Update the calls for
elf_merge_gnu_properties.
* elfnn-aarch64.c (elfNN_aarch64_merge_gnu_properties): Update handling
of --force-bti warning and add argument.
* elfxx-aarch64.c (_bfd_aarch64_elf_link_setup_gnu_properties): Add
warning.
* elfxx-x86.c (_bfd_x86_elf_merge_gnu_properties): Add argument.
* elfxx-x86.h (_bfd_x86_elf_merge_gnu_properties): Likewise in
declaration.
[BFD, AArch64] Define elf_backend_fixup_gnu_properties in AArch64 This patch add support for elf_backend_fixup_gnu_properties for GNU property support for AArch64. The new AArch64 specific definition _bfd_aarch64_elf_link_fixup_gnu_properties goes through the property list to find AArch64 type properties and removes the properties that are marked as "property_remove". *** bfd/ChangeLog *** 2019-03-20 Sudakshina Das <sudi.das@arm.com> * elfxx-aarch64.c (_bfd_aarch64_elf_link_fixup_gnu_properties): Define. * elfxx-aarch64.h (_bfd_aarch64_elf_link_fixup_gnu_properties): Declare. (elf_backend_fixup_gnu_properties): Define for AArch64.
2019-03-20 19:00:07 +01:00
2019-03-20 Sudakshina Das <sudi.das@arm.com>
* elfxx-aarch64.c (_bfd_aarch64_elf_link_fixup_gnu_properties): Define.
* elfxx-aarch64.h (_bfd_aarch64_elf_link_fixup_gnu_properties): Declare.
(elf_backend_fixup_gnu_properties): Define for AArch64.
PR24355, segmentation fault in function called from ppc_finish_symbols This one looks to be a bug going back to 2009, git commit e054468f6c "STT_GNU_IFUNC support for PowerPC". That bug was carried over with git commit 49c09209d0 "Rearrange PLT reloc output on powerpc". If the refcount for an ifunc local sym plt entry was zero, ppc_elf_size_dynamic_sections would correctly set plt.offset to -1 but leave glink_offset uninitialized. That leads to occasional segfaults (which can be made solid with MALLOC_PERTURB_=1 when using glibc). So, guard the write_glink_stub call with plt.offset != -1. Also, remove the totally ineffective attempt at writing multiple-use glink stubs only once. PR 24355 * elf32-ppc.c (ppc_finish_symbols): Don't call write_glink_stub for local iplt syms with ent->plt.offset == -1. Remove ineffective attempt at writing glink stubs only once.
2019-03-18 12:08:36 +01:00
2019-03-18 Alan Modra <amodra@gmail.com>
PR 24355
* elf32-ppc.c (ppc_finish_symbols): Don't call write_glink_stub
for local iplt syms with ent->plt.offset == -1. Remove ineffective
attempt at writing glink stubs only once.
PR24337, segfault in _bfd_elf_rela_local_sym, again Reverts commit 1ff31e135f, fixing the problem more generally. There are likely other place that will segfault on a NULL section. PR 24337 * elf.c (_bfd_elf_rela_local_sym): Revert last change. (_bfd_elf_rel_local_sym): Likewise. * elflink.c (elf_link_input_bfd): Use bfd_und_section for section of symbols with unrecognized shndx.
2019-03-16 00:04:47 +01:00
2019-03-16 Alan Modra <amodra@gmail.com>
PR 24337
* elf.c (_bfd_elf_rela_local_sym): Revert last change.
(_bfd_elf_rel_local_sym): Likewise.
* elflink.c (elf_link_input_bfd): Use bfd_und_section for
section of symbols with unrecognized shndx.
COFF: Check for symbols defined in discarded section For LTO, a symbol may defined in discarded section. We should mark it as undefined so that LTO plugin will make IR definition available. PR ld/24267 * coffgen.c (_bfd_coff_section_already_linked): Skip discarded section. * cofflink.c (coff_link_add_symbols): Check for symbols defined in discarded section.
2019-03-15 15:19:01 +01:00
2019-03-15 H.J. Lu <hongjiu.lu@intel.com>
PR ld/24267
* coffgen.c (_bfd_coff_section_already_linked): Skip discarded
section.
* cofflink.c (coff_link_add_symbols): Check for symbols defined
in discarded section.
PR24339, segfault on NULL symbol section PR 24339 * elflink.c (elf_link_add_object_symbols): Bail out on a local symbol after globals if elf_bad_symtab is not set.
2019-03-15 07:19:59 +01:00
2019-03-15 Alan Modra <amodra@gmail.com>
PR 24339
* elflink.c (elf_link_add_object_symbols): Bail out on a local
symbol after globals if elf_bad_symtab is not set.
PR24337, segfault in _bfd_elf_rela_local_sym PR 24337 * elf.c (_bfd_elf_rela_local_sym): Don't segfault on NULL sec. (_bfd_elf_rel_local_sym): Likewise.
2019-03-15 07:19:42 +01:00
2019-03-15 Alan Modra <amodra@gmail.com>
PR 24337
* elf.c (_bfd_elf_rela_local_sym): Don't segfault on NULL sec.
(_bfd_elf_rel_local_sym): Likewise.
PR24336, buffer overflow in swap_reloca_in PR 24336 * elflink.c (elf_link_read_relocs_from_section): Handle fuzzed object files with sh_size not a multiple of sh_entsize.
2019-03-15 06:19:27 +01:00
2019-03-15 Alan Modra <amodra@gmail.com>
PR 24336
* elflink.c (elf_link_read_relocs_from_section): Handle fuzzed
object files with sh_size not a multiple of sh_entsize.
Re-indent elf_x86_64_relocate_section * elf64-x86-64.c (elf_x86_64_relocate_section): Re-indent.
2019-03-15 07:43:36 +01:00
2019-03-15 H.J. Lu <hongjiu.lu@intel.com>
x86-64: Check for corrupt input with bad relocation PR ld/24338 * elf64-x86-64.c (elf_x86_64_relocate_section): Check for corrupt input with bad relocation.
2019-03-15 08:46:12 +01:00
PR ld/24338
* elf64-x86-64.c (elf_x86_64_relocate_section): Check for corrupt
input with bad relocation.
22019-03-15 H.J. Lu <hongjiu.lu@intel.com>
Re-indent elf_x86_64_relocate_section * elf64-x86-64.c (elf_x86_64_relocate_section): Re-indent.
2019-03-15 07:43:36 +01:00
* elf64-x86-64.c (elf_x86_64_relocate_section): Re-indent.
Fix a buffer overrun error when attempting to parse corrupt DWARF information. PR 24334 * dwarf2.c (struct dwarf2_debug): Add sec_vma_count field. (save_section_vma): Initialise field to the number of entries in the sec_vma table. (section_vma_same): Check that the number of entries in the sec_vma table matches the number of sections in the bfd.
2019-03-14 18:21:41 +01:00
2019-03-14 Nick Clifton <nickc@redhat.com>
PR 24334
* dwarf2.c (struct dwarf2_debug): Add sec_vma_count field.
(save_section_vma): Initialise field to the number of entries in
the sec_vma table.
(section_vma_same): Check that the number of entries in the
sec_vma table matches the number of sections in the bfd.
Fix an illegal memory access when parsing a corrupt ELF file. PR 24333 * elflink.c (_bfd_elf_add_default_symbol): Add a check for a NULL section owner pointer when adding the default symbol.
2019-03-14 17:03:07 +01:00
2019-03-14 Nick Clifton <nickc@redhat.com>
PR 24333
* elflink.c (_bfd_elf_add_default_symbol): Add a check for a NULL
section owner pointer when adding the default symbol.
Fix illegal memory access parsing a corrupt ELF file. PR 24332 * elflink.c (elf_link_add_object_symbols): Add new local variable extversym_end. Initialise it to point to the end of the version symbol table, if present. Check it when initialising and updating the ever pointer.
2019-03-14 15:45:32 +01:00
2019-03-14 Nick Clifton <nickc@redhat.com>
PR 24332
* elflink.c (elf_link_add_object_symbols): Add new local variable
extversym_end. Initialise it to point to the end of the version
symbol table, if present. Check it when initialising and updating
the ever pointer.
[BFD, LD, AArch64, 3/3] Add --pac-plt to enable PLTs protected with PAC. This is part of the patch series to add support for BTI and PAC in AArch64 linker. 1) This patch adds new definitions of PAC enabled PLTs and both BTI and PAC enabled PLTs. 2) It also defines the new dynamic tag DT_AARCH64_PAC_PLT for the PAC enabled PLTs. 3) This patch adds a new ld command line option: --pac-plt. In the presence of this option, the linker uses the PAC enabled PLTs and marks with DT_AARCH64_PAC_PLT. 4) In case both BTI and PAC are enabled the linker should pick PLTs enabled with both and also use dynamic tags for both. All these are made according to the new AArch64 ELF ABI https://developer.arm.com/docs/ihi0056/latest/elf-for-the-arm-64-bit-architecture-aarch64-abi-2018q4 *** bfd/ChangeLog *** 2019-03-13 Sudakshina Das <sudi.das@arm.com> * elfnn-aarch64.c (PLT_PAC_ENTRY_SIZE, PLT_PAC_SMALL_ENTRY_SIZE): New. (PLT_BTI_PAC_ENTRY_SIZE, PLT_BTI_PAC_SMALL_ENTRY_SIZE): New. (setup_plt_values): Account for PAC or PAC and BTI enabled PLTs. (elfNN_aarch64_size_dynamic_sections): Add checks for PLT_BTI_PAC and PLT_PAC_PLT. (elfNN_aarch64_finish_dynamic_sections): Account for PLT_BTI_PAC. (get_plt_type): Add case for DT_AARCH64_PAC_PLT. (elfNN_aarch64_plt_sym_val): Add cases for PLT_BTI_PAC and PLT_PAC. *** binutils/ChangeLog *** 2019-03-13 Sudakshina Das <sudi.das@arm.com> * readelf.c (get_aarch64_dynamic_type): Add case for DT_AARCH64_PAC_PLT. (dynamic_section_aarch64_val): Likewise. *** include/ChangeLog *** 2019-03-13 Sudakshina Das <sudi.das@arm.com> * elf/aarch64.h (DT_AARCH64_PAC_PLT): New. *** ld/ChangeLog *** 2019-03-13 Sudakshina Das <sudi.das@arm.com> * NEWS: Document --pac-plt. * emultempl/aarch64elf.em (OPTION_PAC_PLT): New. (PARSE_AND_LIST_LONGOPTS, PARSE_AND_LIST_OPTIONS): Add pac-plt. (PARSE_AND_LIST_ARGS_CASES): Handle OPTION_PAC_PLT. * testsuite/ld-aarch64/aarch64-elf.exp: Add the following tests. * testsuite/ld-aarch64/bti-pac-plt-1.d: New test. * testsuite/ld-aarch64/bti-pac-plt-2.d: New test. * testsuite/ld-aarch64/pac-plt-1.d: New test. * testsuite/ld-aarch64/pac-plt-2.d: New test. * testsuite/ld-aarch64/bti-plt-1.s: Add .ifndef directive.
2019-03-13 12:09:10 +01:00
2019-03-13 Sudakshina Das <sudi.das@arm.com>
* elfnn-aarch64.c (PLT_PAC_ENTRY_SIZE, PLT_PAC_SMALL_ENTRY_SIZE): New.
(PLT_BTI_PAC_ENTRY_SIZE, PLT_BTI_PAC_SMALL_ENTRY_SIZE): New.
(setup_plt_values): Account for PAC or PAC and BTI enabled PLTs.
(elfNN_aarch64_size_dynamic_sections): Add checks for PLT_BTI_PAC
and PLT_PAC_PLT.
(elfNN_aarch64_finish_dynamic_sections): Account for PLT_BTI_PAC.
(get_plt_type): Add case for DT_AARCH64_PAC_PLT.
(elfNN_aarch64_plt_sym_val): Add cases for PLT_BTI_PAC and PLT_PAC.
[BFD, LD, AArch64, 2/3] Add --force-bti to enable BTI and to select BTI enabled PLTs This is part of the patch series to add support for BTI and PAC in AArch64 linker. 1) This patch adds a new ld command line option: --force-bti. In the presence of this option, the linker enables BTI with the GNU_PROPERTY_AARCH64_FEATURE_1_BTI feature. This gives out warning in case of missing gnu notes for BTI in inputs. 2) It also defines a new set of BTI enabled PLTs. These are used either when all the inputs are marked with GNU_PROPERTY_AARCH64_FEATURE_1_BTI or when the new --force-bti option is used. This required adding new fields in elf_aarch64_link_hash_table so that we could make the PLT related information more generic. 3) It also defines a dynamic tag DT_AARCH64_BTI_PLT. The linker uses this whenever it picks BTI enabled PLTs. All these are made according to the new AArch64 ELF ABI https://developer.arm.com/docs/ihi0056/latest/elf-for-the-arm-64-bit-architecture-aarch64-abi-2018q4 *** bfd/ChangeLog *** 2019-03-13 Sudakshina Das <sudi.das@arm.com> Szabolcs Nagy <szabolcs.nagy@arm.com> * bfd-in.h (aarch64_plt_type, aarch64_enable_bti_type): New. (aarch64_bti_pac_info): New. (bfd_elf64_aarch64_set_options): Add aarch64_bti_pac_info argument. (bfd_elf32_aarch64_set_options): Likewise. * bfd-in2.h: Regenerate * elfnn-aarch64.c (PLT_BTI_ENTRY_SIZE): New. (PLT_BTI_SMALL_ENTRY_SIZE, PLT_BTI_TLSDESC_ENTRY_SIZE): New. (elfNN_aarch64_small_plt0_bti_entry): New. (elfNN_aarch64_small_plt_bti_entry): New. (elfNN_aarch64_tlsdesc_small_plt_bti_entry): New. (elf_aarch64_obj_tdata): Add no_bti_warn and plt_type fields. (elf_aarch64_link_hash_table): Add plt0_entry, plt_entry and tlsdesc_plt_entry_size fields. (elfNN_aarch64_link_hash_table_create): Initialise the new fields. (setup_plt_values): New helper function. (bfd_elfNN_aarch64_set_options): Use new bp_info to set plt sizes and bti enable type. (elfNN_aarch64_allocate_dynrelocs): Use new size members instead of fixed macros. (elfNN_aarch64_size_dynamic_sections): Likewise and add checks. (elfNN_aarch64_create_small_pltn_entry): Use new generic pointers to plt stubs instead of fixed ones and update filling them according to the need for bti. (elfNN_aarch64_init_small_plt0_entry): Likewise. (elfNN_aarch64_finish_dynamic_sections): Likewise. (get_plt_type, elfNN_aarch64_get_synthetic_symtab): New. (elfNN_aarch64_plt_sym_val): Update size accordingly. (elfNN_aarch64_link_setup_gnu_properties): Set up plts if BTI GNU NOTE is set. (bfd_elfNN_get_synthetic_symtab): Define. (elfNN_aarch64_merge_gnu_properties): Give out warning with --force-bti and mising BTI NOTE SECTION. *** binutils/ChangeLog *** 2019-03-13 Sudakshina Das <sudi.das@arm.com> Szabolcs Nagy <szabolcs.nagy@arm.com> * readelf.c (get_aarch64_dynamic_type): New. (get_dynamic_type): Use above for EM_AARCH64. (dynamic_section_aarch64_val): New. (process_dynamic_section): Use above for EM_AARCH64. *** include/ChangeLog *** 2019-03-13 Sudakshina Das <sudi.das@arm.com> Szabolcs Nagy <szabolcs.nagy@arm.com> * elf/aarch64.h (DT_AARCH64_BTI_PLT): New. *** ld/ChangeLog *** 2019-03-13 Sudakshina Das <sudi.das@arm.com> Szabolcs Nagy <szabolcs.nagy@arm.com> * NEWS: Document --force-bti. * emultempl/aarch64elf.em (plt_type, bti_type, OPTION_FORCE_BTI): New. (PARSE_AND_LIST_SHORTOPTS, PARSE_AND_LIST_OPTIONS): Add force-bti. (PARSE_AND_LIST_ARGS_CASES): Handle OPTION_FORCE_BTI. * testsuite/ld-aarch64/aarch64-elf.exp: Add all the tests below. * testsuite/ld-aarch64/bti-plt-1.d: New test. * testsuite/ld-aarch64/bti-plt-1.s: New test. * testsuite/ld-aarch64/bti-plt-2.s: New test. * testsuite/ld-aarch64/bti-plt-2.d: New test. * testsuite/ld-aarch64/bti-plt-3.d: New test. * testsuite/ld-aarch64/bti-plt-4.d: New test. * testsuite/ld-aarch64/bti-plt-5.d: New test. * testsuite/ld-aarch64/bti-plt-6.d: New test. * testsuite/ld-aarch64/bti-plt-7.d: New test. * testsuite/ld-aarch64/bti-plt-so.s: New test. * testsuite/ld-aarch64/bti-plt.ld: New test.
2019-03-13 11:54:30 +01:00
2019-03-13 Sudakshina Das <sudi.das@arm.com>
Szabolcs Nagy <szabolcs.nagy@arm.com>
* bfd-in.h (aarch64_plt_type, aarch64_enable_bti_type): New.
(aarch64_bti_pac_info): New.
(bfd_elf64_aarch64_set_options): Add aarch64_bti_pac_info argument.
(bfd_elf32_aarch64_set_options): Likewise.
* bfd-in2.h: Regenerate
* elfnn-aarch64.c (PLT_BTI_ENTRY_SIZE): New.
(PLT_BTI_SMALL_ENTRY_SIZE, PLT_BTI_TLSDESC_ENTRY_SIZE): New.
(elfNN_aarch64_small_plt0_bti_entry): New.
(elfNN_aarch64_small_plt_bti_entry): New.
(elfNN_aarch64_tlsdesc_small_plt_bti_entry): New.
(elf_aarch64_obj_tdata): Add no_bti_warn and plt_type fields.
(elf_aarch64_link_hash_table): Add plt0_entry, plt_entry and
tlsdesc_plt_entry_size fields.
(elfNN_aarch64_link_hash_table_create): Initialise the new fields.
(setup_plt_values): New helper function.
(bfd_elfNN_aarch64_set_options): Use new bp_info to set plt sizes and
bti enable type.
(elfNN_aarch64_allocate_dynrelocs): Use new size members instead of
fixed macros.
(elfNN_aarch64_size_dynamic_sections): Likewise and add checks.
(elfNN_aarch64_create_small_pltn_entry): Use new generic pointers
to plt stubs instead of fixed ones and update filling them according
to the need for bti.
(elfNN_aarch64_init_small_plt0_entry): Likewise.
(elfNN_aarch64_finish_dynamic_sections): Likewise.
(get_plt_type, elfNN_aarch64_get_synthetic_symtab): New.
(elfNN_aarch64_plt_sym_val): Update size accordingly.
(elfNN_aarch64_link_setup_gnu_properties): Set up plts if BTI GNU NOTE
is set.
(bfd_elfNN_get_synthetic_symtab): Define.
(elfNN_aarch64_merge_gnu_properties): Give out warning with --force-bti
and mising BTI NOTE SECTION.
[BFD, LD, AArch64, 1/3] Add support for GNU PROPERTIES in AArch64 for BTI and PAC This is part of the patch series to add support for BTI and PAC in AArch64 linker. This patch implements the following: 1) This extends in the gnu property support in the linker for AArch64 by defining backend hooks for elf_backend_setup_gnu_properties, elf_backend_merge_gnu_properties and elf_backend_parse_gnu_properties. 2) It defines AArch64 specific GNU property GNU_PROPERTY_AARCH64_FEATURE_1_AND and 2 bit for BTI and PAC in it. 3) It also adds support in readelf.c to read and print these new GNU properties in AArch64. All these are made according to the new AArch64 ELF ABI https://developer.arm.com/docs/ihi0056/latest/elf-for-the-arm-64-bit-architecture-aarch64-abi-2018q4 *** bfd/ChangeLog *** 2019-03-13 Sudakshina Das <sudi.das@arm.com> * elf-properties.c (_bfd_elf_link_setup_gnu_properties): Exclude linker created inputs from merge. * elfnn-aarch64.c (struct elf_aarch64_obj_tdata): Add field for GNU_PROPERTY_AARCH64_FEATURE_1_AND properties. (elfNN_aarch64_link_setup_gnu_properties): New. (elfNN_aarch64_merge_gnu_properties): New. (elf_backend_setup_gnu_properties): Define for AArch64. (elf_backend_merge_gnu_properties): Likewise. * elfxx-aarch64.c (_bfd_aarch64_elf_link_setup_gnu_properties): Define. (_bfd_aarch64_elf_parse_gnu_properties): Define. (_bfd_aarch64_elf_merge_gnu_properties): Define. * elfxx-aarch64.h (_bfd_aarch64_elf_link_setup_gnu_properties): Declare. (_bfd_aarch64_elf_parse_gnu_properties): Declare. (_bfd_aarch64_elf_merge_gnu_properties): Declare. (elf_backend_parse_gnu_properties): Define for AArch64. *** binutils/ChangeLog *** 2019-03-13 Sudakshina Das <sudi.das@arm.com> * readelf.c (decode_aarch64_feature_1_and): New. (print_gnu_property_note): Add case for AArch64 gnu notes. *** include/ChangeLog *** 2019-03-13 Sudakshina Das <sudi.das@arm.com> * elf/common.h (GNU_PROPERTY_AARCH64_FEATURE_1_AND): New. (GNU_PROPERTY_AARCH64_FEATURE_1_BTI): New. (GNU_PROPERTY_AARCH64_FEATURE_1_PAC): New. *** ld/ChangeLog *** 2019-03-13 Sudakshina Das <sudi.das@arm.com> * NEWS: Document GNU_PROPERTY_AARCH64_FEATURE_1_BTI and GNU_PROPERTY_AARCH64_FEATURE_1_PAC. * testsuite/ld-aarch64/aarch64-elf.exp: Add run commands for new tests. * testsuite/ld-aarch64/property-bti-pac1.d: New test. * testsuite/ld-aarch64/property-bti-pac1.s: New test. * testsuite/ld-aarch64/property-bti-pac2.d: New test. * testsuite/ld-aarch64/property-bti-pac2.s: New test. * testsuite/ld-aarch64/property-bti-pac3.d: New test.
2019-03-13 11:42:27 +01:00
2019-03-13 Sudakshina Das <sudi.das@arm.com>
* elf-properties.c (_bfd_elf_link_setup_gnu_properties): Exclude
linker created inputs from merge.
* elfnn-aarch64.c (struct elf_aarch64_obj_tdata): Add field for
GNU_PROPERTY_AARCH64_FEATURE_1_AND properties.
(elfNN_aarch64_link_setup_gnu_properties): New.
(elfNN_aarch64_merge_gnu_properties): New.
(elf_backend_setup_gnu_properties): Define for AArch64.
(elf_backend_merge_gnu_properties): Likewise.
* elfxx-aarch64.c (_bfd_aarch64_elf_link_setup_gnu_properties): Define.
(_bfd_aarch64_elf_parse_gnu_properties): Define.
(_bfd_aarch64_elf_merge_gnu_properties): Define.
* elfxx-aarch64.h (_bfd_aarch64_elf_link_setup_gnu_properties): Declare.
(_bfd_aarch64_elf_parse_gnu_properties): Declare.
(_bfd_aarch64_elf_merge_gnu_properties): Declare.
(elf_backend_parse_gnu_properties): Define for AArch64.
x86: Properly set IBT and SHSTK properties for -z ibt/shstk There should be no AND properties if some input doesn't have them. We should set IBT and SHSTK properties for -z ibt and -z shstk if needed. bfd/ PR ld/24322 * elfxx-x86.c (_bfd_x86_elf_merge_gnu_properties): Properly merge GNU_PROPERTY_X86_FEATURE_1_[IBT|SHSTK]. ld/ PR ld/24322 * testsuite/ld-i386/i386.exp: Run PR ld/24322 tests. * testsuite/ld-x86-64/x86-64.exp: Likewise. * testsuite/ld-i386/pr24322a.d: New file. * testsuite/ld-i386/pr24322b.d: Likewise. * testsuite/ld-x86-64/pr24322a-x32.d: Likewise. * testsuite/ld-x86-64/pr24322a.d: Likewise. * testsuite/ld-x86-64/pr24322b-x32.d: Likewise. * testsuite/ld-x86-64/pr24322b.d: Likewise. * testsuite/ld-x86-64/pr24322a.s: Likewise. * testsuite/ld-x86-64/pr24322b.s: Likewise. * testsuite/ld-x86-64/pr24322c.s: Likewise.
2019-03-13 07:38:15 +01:00
2019-03-13 H.J. Lu <hongjiu.lu@intel.com>
PR ld/24322
* elfxx-x86.c (_bfd_x86_elf_merge_gnu_properties): Properly
merge GNU_PROPERTY_X86_FEATURE_1_[IBT|SHSTK].
Don't use bfd_get_file_size in objdump Compressed debug sections can have uncompressed sizes that exceed the original file size, so we can't use bfd_get_file_size. objdump also used bfd_get_file_size to limit reloc section size, but I believe the underlying bug causing the PR22508 out of bounds buffer access was that we had an integer overflow when calculating the reloc buffer size. I've fixed that instead in most of the backends, som and vms-alpha being the exceptions. SOM and vmd-alpha have rather more serious bugs in their slurp_relocs routines that would need fixing first if we want to fuss about making them safe against fuzzed object files. The patch also fixes a number of other potential overflows by using the bfd_alloc2/malloc2/zalloc2 memory allocation functions. bfd/ * coffcode.h (buy_and_read): Delete unnecessary forward decl. Add nmemb parameter. Use bfd_alloc2. (coff_slurp_line_table): Use bfd_alloc2. Update buy_and_read calls. Delete assertion. (coff_slurp_symbol_table): Use bfd_alloc2 and bfd_zalloc2. (coff_slurp_reloc_table): Use bfd_alloc2. Update buy_and_read calls. * coffgen.c (coff_get_reloc_upper_bound): Ensure size calculation doesn't overflow. * elf.c (bfd_section_from_shdr): Use bfd_zalloc2. Style fix. (assign_section_numbers): Style fix. (swap_out_syms): Use bfd_malloc2. (_bfd_elf_get_reloc_upper_bound): Ensure size calculation doesn't overflow. (_bfd_elf_make_empty_symbol): Style fix. (elfobj_grok_stapsdt_note_1): Formatting. * elfcode.h (elf_object_p): Use bfd_alloc2. (elf_write_relocs, elf_write_shdrs_and_ehdr): Likewise. (elf_slurp_symbol_table): Use bfd_zalloc2. (elf_slurp_reloc_table): Use bfd_alloc2. (_bfd_elf_bfd_from_remote_memory): Use bfd_malloc2. * elf64-sparc (elf64_sparc_get_reloc_upper_bound): Ensure size calculation doesn't overflow. (elf64_sparc_get_dynamic_reloc_upper_bound): Likewise. * mach-o.c (bfd_mach_o_get_reloc_upper_bound): Likewise. * pdp11.c (get_reloc_upper_bound): Copy aoutx.h version. binutils/ * objdump.c (load_specific_debug_section): Don't compare section size against file size. (dump_relocs_in_section): Don't compare reloc size against file size. Print "failed to read relocs" on bfd_get_reloc_upper_bound error.
2019-03-12 06:49:25 +01:00
2019-03-12 Alan Modra <amodra@gmail.com>
* coffcode.h (buy_and_read): Delete unnecessary forward decl. Add
nmemb parameter. Use bfd_alloc2.
(coff_slurp_line_table): Use bfd_alloc2. Update buy_and_read calls.
Delete assertion.
(coff_slurp_symbol_table): Use bfd_alloc2 and bfd_zalloc2.
(coff_slurp_reloc_table): Use bfd_alloc2. Update buy_and_read calls.
* coffgen.c (coff_get_reloc_upper_bound): Ensure size calculation
doesn't overflow.
* elf.c (bfd_section_from_shdr): Use bfd_zalloc2. Style fix.
(assign_section_numbers): Style fix.
(swap_out_syms): Use bfd_malloc2.
(_bfd_elf_get_reloc_upper_bound): Ensure size calculation doesn't
overflow.
(_bfd_elf_make_empty_symbol): Style fix.
(elfobj_grok_stapsdt_note_1): Formatting.
* elfcode.h (elf_object_p): Use bfd_alloc2.
(elf_write_relocs, elf_write_shdrs_and_ehdr): Likewise.
(elf_slurp_symbol_table): Use bfd_zalloc2.
(elf_slurp_reloc_table): Use bfd_alloc2.
(_bfd_elf_bfd_from_remote_memory): Use bfd_malloc2.
* elf64-sparc (elf64_sparc_get_reloc_upper_bound): Ensure
size calculation doesn't overflow.
(elf64_sparc_get_dynamic_reloc_upper_bound): Likewise.
* mach-o.c (bfd_mach_o_get_reloc_upper_bound): Likewise.
* pdp11.c (get_reloc_upper_bound): Copy aoutx.h version.
PR24311, FAIL: S-records with constructors Not padding string merge section output to its alignment can cause failures of the S-record tests when input string merge sections are padded, since the ELF linker output for the single string section would shrink compared to the SREC linker output. That might result in following sections having different addresses. On the other hand, padding string merge section output when input string merge sections are *not* padded can also cause failures, in this case due to the ELF linker output for the string section being larger (due to padding) than the SREC linker output. It would be better to write a more robust test, but it is also nice to leave input unchanged when no string merges occur. PR 24311 * merge.c (merge_strings): Return secinfo. Don't pad section to alignment here. (_bfd_merge_sections): Pad section to alignment here, if input sections contributing to merged output all pad to alignment. Formatting.
2019-03-08 13:11:55 +01:00
2019-03-08 Alan Modra <amodra@gmail.com>
PR 24311
* merge.c (merge_strings): Return secinfo. Don't pad section
to alignment here.
(_bfd_merge_sections): Pad section to alignment here, if input
sections contributing to merged output all pad to alignment.
Formatting.
Fix a segmentation fault triggered by disassembling an EFi file with source included. * dwarf2.c (_bfd_dwarf2_find_symbol_bias): Check for a NULL symbol table pointer. * coffgen.c (coff_find_nearest_line_with_names): Do not call _bfd_dwarf2_find_symbol_bias if there is no symbol table available. https://bugzilla.redhat.com/show_bug.cgi?id=1685727
2019-03-06 10:43:15 +01:00
2019-03-06 Nick Clifton <nickc@redhat.com>
* dwarf2.c (_bfd_dwarf2_find_symbol_bias): Check for a NULL symbol
table pointer.
* coffgen.c (coff_find_nearest_line_with_names): Do not call
_bfd_dwarf2_find_symbol_bias if there is no symbol table available.
Revert "Add support to GNU ld to separate got related plt entries" bfd/ChangeLog: 2019-03-01 Andreas Krebbel <krebbel@linux.ibm.com> This reverts commit 5a12586d44fa8d5dfc74cbca4f2f36a273a16335. 2019-01-14 Maamoun Tarsha <maamountk@hotmail.com> PR 20113 * elf32-s390.c (allocate_dynrelocs): Update comment. ld/ChangeLog: 2019-03-01 Andreas Krebbel <krebbel@linux.ibm.com> This reverts commit 5a12586d44fa8d5dfc74cbca4f2f36a273a16335. 2019-01-14 Maamoun Tarsha <maamountk@hotmail.com> PR 20113 * emulparams/elf64_s390.sh (SEPARATE_GOTPLT): Define. * emulparams/elf_s390.sh (SEPARATE_GOTPLT): Define. * testsuite/ld-s390/gotreloc_31-1.dd: Update expected output. * testsuite/ld-s390/tlsbin.dd: Likewise. * testsuite/ld-s390/tlsbin.rd: Likewise. * testsuite/ld-s390/tlsbin.sd: Likewise. * testsuite/ld-s390/tlsbin_64.dd: Likewise. * testsuite/ld-s390/tlsbin_64.rd: Likewise. * testsuite/ld-s390/tlsbin_64.sd: Likewise. * testsuite/ld-s390/tlspic.dd: Likewise. * testsuite/ld-s390/tlspic.rd: Likewise. * testsuite/ld-s390/tlspic.sd: Likewise. * testsuite/ld-s390/tlspic_64.dd: Likewise. * testsuite/ld-s390/tlspic_64.rd: Likewise. * testsuite/ld-s390/tlspic_64.sd: Likewise. * testsuite/ld-s390/s390.exp: Skip s390 tests for tpf targets.
2019-03-01 15:23:42 +01:00
2019-03-01 Andreas Krebbel <krebbel@linux.ibm.com>
This reverts commit 5a12586d44fa8d5dfc74cbca4f2f36a273a16335.
2019-01-14 Maamoun Tarsha <maamountk@hotmail.com>
PR 20113
* elf32-s390.c (allocate_dynrelocs): Update comment.
Binutils: Always skip only 1 byte for CIE version 1's return address register. According to the specification for the CIE entries, when the CIE version is 1 then the return address register field is always 1 byte. Readelf does this correctly in read_cie in dwarf.c but ld does this incorrectly and always tries to read a skip_leb128. If the value here has the top bit set then ld will incorrectly read at least another byte, causing either an assert failure or an incorrect address to be used in eh_frame. I'm not sure how to generate a generic test for this as I'd need to write assembly, and it's a bit hard to trigger. Essentially the relocated value needs to start with something that & 0x70 != 0x10 while trying to write a personality. bfd/ChangeLog: * elf-eh-frame.c (_bfd_elf_write_section_eh_frame): Correct CIE parse.
2019-03-01 12:37:51 +01:00
2019-02-28 Tamar Christina <tamar.christina@arm.com>
* elf-eh-frame.c (_bfd_elf_write_section_eh_frame): Correct CIE parse.
Prevent a buffer overrun error when attempting to parse a corrupt ELF file. PR 24273 * elf.c (bfd_elf_string_from_elf_section): Check for a string section that is not NUL terminated.
2019-02-28 15:30:20 +01:00
2019-02-28 Nick Clifton <nickc@redhat.com>
PR 24273
* elf.c (bfd_elf_string_from_elf_section): Check for a string
section that is not NUL terminated.
x86-64: Skip protected check on symbol defined by linker Skip symbol defined by linker when checking copy reloc on protected symbol. bfd/ PR ld/24276 * elf64-x86-64.c (elf_x86_64_check_relocs): Skip symbol defined by linker when checking copy reloc on protected symbol. ld/ PR ld/24276 * testsuite/ld-i386/i386.exp: Run PR ld/24276 test. * testsuite/ld-x86-64/x86-64.exp: Likewise. * testsuite/ld-i386/pr24276.dso: New file. * testsuite/ld-i386/pr24276.warn: Likewise. * testsuite/ld-x86-64/pr24276.dso: Likewise. * testsuite/ld-x86-64/pr24276.warn: Likewise.
2019-02-27 20:53:16 +01:00
2019-02-27 H.J. Lu <hongjiu.lu@intel.com>
PR ld/24276
* elf64-x86-64.c (elf_x86_64_check_relocs): Skip symbol defined
by linker when checking copy reloc on protected symbol.
PR24144, pdp11-ld overwriting section data with zeros bfd/ PR 24144 * pdp11.c (set_section_contents): Revert 2015-02-24 change. gas/ PR 24144 * config/obj-aout.c (obj_aout_frob_file_before_fix): Write to end of section to ensure file contents cover aligned section size.
2019-02-24 07:14:48 +01:00
2019-02-24 Alan Modra <amodra@gmail.com>
PR 24144
* pdp11.c (set_section_contents): Revert 2015-02-24 change.
bfd: xtensa: fix callx relaxation Big section alignment requirements between source and destination of a long call can result in making call range bigger than what's reachable by the call opcode. Add biggest section alignment of sections between the call site and call destination to the call distance when making long call relaxation decision. 2019-02-20 Eric Tsai <erictsai@cadence.com> bfd/ * elf32-xtensa.c (is_resolvable_asm_expansion): Scan output sections between the call site and call destination and adjust call distance by the largest alignment. ld/ * testsuite/ld-xtensa/call_overflow.d: New test definition. * testsuite/ld-xtensa/call_overflow1.s: New test source. * testsuite/ld-xtensa/call_overflow2.s: New test source. * testsuite/ld-xtensa/call_overflow3.s: New test source. * testsuite/ld-xtensa/xtensa.exp: Add call_overflow test.
2019-02-16 01:43:23 +01:00
2019-02-20 Eric Tsai <erictsai@cadence.com>
* elf32-xtensa.c (is_resolvable_asm_expansion): Scan output
sections between the call site and call destination and adjust
call distance by the largest alignment.
AArch64: Add pauth core file section Used for the AArch64 pointer authentication code mask registers in Arm v8.3-a. NT_ARM_PAC_MASK matches the value in Linux include/uapi/linux/elf.h include/ChangeLog: * elf/common.h (NT_ARM_PAC_MASK): Add define. bfd/ChangeLog: * elf-bfd.h (elfcore_write_aarch_pauth): Add declaration. * elf.c (elfcore_grok_aarch_pauth): New function. (elfcore_grok_note): Check for NT_ARM_PAC_MASK. (elfcore_write_aarch_pauth): New function. (elfcore_write_register_note): Check for AArch64 pauth section.
2019-02-20 11:39:28 +01:00
2019-02-20 Alan Hayward <alan.hayward@arm.com>
* elf-bfd.h (elfcore_write_aarch_pauth): Add declaration.
* elf.c (elfcore_grok_aarch_pauth): New function.
(elfcore_grok_note): Check for NT_ARM_PAC_MASK.
(elfcore_write_aarch_pauth): New function.
(elfcore_write_register_note): Check for AArch64 pauth section.
Check asprintf return value git a31b8bd9a05 introduced a warning (depending on your system headers). PR 24225 * elf32-nios2.c (nios2_elf32_relocate_section): Check asprintf return value.
2019-02-20 09:24:41 +01:00
2019-02-20 Alan Modra <amodra@gmail.com>
PR 24225
* elf32-nios2.c (nios2_elf32_relocate_section): Check asprintf
return value.
Use or1k-darwin host SHARED_LIBADD for *-darwin. * configure.ac (SHARED_LIBADD): Add -liberty -lintl for all Darwin hosts, not just or1k. * configure: Regenerate.
2019-02-20 05:17:40 +01:00
2019-02-20 Michael Roitzsch <reactorcontrol@icloud.com>
* configure.ac (SHARED_LIBADD): Add -liberty -lintl for all
Darwin hosts, not just or1k.
* configure: Regenerate.
PR24236, Heap buffer overflow in _bfd_archive_64_bit_slurp_armap PR 24236 * archive64.c (_bfd_archive_64_bit_slurp_armap): Move code adding sentinel NUL to string buffer nearer to loop where it is used. Don't go past sentinel when scanning strings, and don't write NUL again. * archive.c (do_slurp_coff_armap): Simplify string handling to archive64.c style.
2019-02-19 22:51:24 +01:00
2019-02-20 Alan Modra <amodra@gmail.com>
PR 24236
* archive64.c (_bfd_archive_64_bit_slurp_armap): Move code adding
sentinel NUL to string buffer nearer to loop where it is used.
Don't go past sentinel when scanning strings, and don't write
NUL again.
* archive.c (do_slurp_coff_armap): Simplify string handling to
archive64.c style.
PR24235, Read memory violation in pei-x86_64.c PR 24235 * pei-x86_64.c (pex64_bfd_print_pdata_section): Correct checks attempting to prevent read past end of section.
2019-02-19 13:18:44 +01:00
2019-02-19 Alan Modra <amodra@gmail.com>
PR 24235
* pei-x86_64.c (pex64_bfd_print_pdata_section): Correct checks
attempting to prevent read past end of section.
PR24225, nios2 buffer overflow PR 24225 * elf32-nios2.c (nios2_elf32_relocate_section): Use asprintf and PRIx64 to generate warning messages. Print local sym names too.
2019-02-18 02:27:22 +01:00
2019-02-18 Alan Modra <amodra@gmail.com>
PR 24225
* elf32-nios2.c (nios2_elf32_relocate_section): Use asprintf and
PRIx64 to generate warning messages. Print local sym names too.
[ARC] don't force _init/_fini as DT_INIT/DT_FINI. Recent gcc commit b4371b277f1e ("[ARC] Enable init_array support") inhibits DT_"INIT,FINI} in favor of DT_{INIT,FINI}ARRAY. Even prior to that, it seems ARC port is the only one with this special DT_INIT/FINI handling in linker emulation. Removing it doesn't seem to change any uClibc/glibc testsuite results, so this can RIP anyways. bfd/ 2019-02-01 Vineet Gupta <vgupta@synopsys.com> * elf32-arc.c: Delete init_str, fini_str ld/ 2019-02-01 Vineet Gupta <vgupta@synopsys.com> * emultempl/arclinux.em : Delete special INIT/FINI handling.
2019-02-09 11:07:42 +01:00
2019-02-09 Vineet Gupta <vgupta@synopsys.com>
* elf32-arc (INIT_SYM_STRING): Delete.
(FINI_SYM_STRING): Likewise.
(init_str): Likewise.
(fini_str): Likewise.
Make inline plt reloc "unsupported for bss-plt" an error This was always supposed to be an error. Code emitted by gcc for inline PLT calls assumes PLT is an array of addresses. * elf32-ppc.c (ppc_elf_relocate_section): Add %X to "unsupported for bss-plt" warning to make it an error.
2019-02-08 02:21:34 +01:00
2019-02-08 Alan Modra <amodra@gmail.com>
* elf32-ppc.c (ppc_elf_relocate_section): Add %X to "unsupported
for bss-plt" warning to make it an error.
SPARC: fix PR ld/18841 This fixes the last ld failures on SPARC64/Linux: FAIL: Run pr18841 with libpr18841b.so FAIL: Run pr18841 with libpr18841c.so FAIL: Run pr18841 with libpr18841bn.so (-z now) FAIL: Run pr18841 with libpr18841cn.so (-z now) by mimicing what has been done on x86-64 and Aarch64 to fix the PR. bfd/ PR ld/18841 * elf32-sparc.c (elf32_sparc_reloc_type_class): Return reloc_class_ifunc for ifunc symbols. * elf64-sparc.c (elf64_sparc_reloc_type_class): Likewise.
2019-02-07 17:04:31 +01:00
2019-02-07 Eric Botcazou <ebotcazou@adacore.com>
PR ld/18841
* elf32-sparc.c (elf32_sparc_reloc_type_class): Return
reloc_class_ifunc for ifunc symbols.
* elf64-sparc.c (elf64_sparc_reloc_type_class): Likewise.
Visium: fix bogus overflow check on 32-bit hosts bfd/ * elf32-visium.c (visium_elf_howto_parity_reloc): Minor tweak. <R_VISIUM_PC16>: Use explicit range test to detect an overflow.
2019-02-07 17:02:24 +01:00
2019-02-07 Eric Botcazou <ebotcazou@adacore.com>
* elf32-visium.c (visium_elf_howto_parity_reloc): Minor tweak.
<R_VISIUM_PC16>: Use explicit range test to detect an overflow.
Move potentially obsolete BFD targets into the definitely obsolete section. Add a note to the README-how-to-make-a-release document about doing this. bfd * config.bfd: Move the powerpc-lynxos and powerpc-windiss targets into the definitely obsolete list. binutils * README-how-to-make-a-release: Add a note about updating the obsolete targets in the bfd/config.bfd file.
2019-02-07 15:30:02 +01:00
2019-02-07 Nick Clifton <nickc@redhat.com>
* config.bfd: Move the powerpc-lynxos and powerpc-windiss targets
into the definitely obsolete list.
x86-64: Restore PIC check for PCREL reloc against protected symbol commit bd7ab16b4537788ad53521c45469a1bdae84ad4a Author: H.J. Lu <hjl.tools@gmail.com> Date: Tue Feb 13 07:34:22 2018 -0800 x86-64: Generate branch with PLT32 relocation removed check R_X86_64_PC32 relocation against protected symbols in shared objects. Since elf_x86_64_check_relocs is called after we have seen all input files, we can check for PC-relative relocations in elf_x86_64_check_relocs. We should not allow PC-relative relocations against protected symbols since address of protected function and location of protected data may not be in the shared object. bfd/ PR ld/24151 * elf64-x86-64.c (elf_x86_64_need_pic): Check SYMBOL_DEFINED_NON_SHARED_P instead of def_regular. (elf_x86_64_relocate_section): Move PIC check for PC-relative relocations to ... (elf_x86_64_check_relocs): Here. (elf_x86_64_finish_dynamic_symbol): Use SYMBOL_DEFINED_NON_SHARED_P to check if a symbol is defined in a non-shared object. * elfxx-x86.h (SYMBOL_DEFINED_NON_SHARED_P): New. ld/ PR ld/24151 * testsuite/ld-x86-64/pr24151a-x32.d: New file. * testsuite/ld-x86-64/pr24151a.d: Likewise. * testsuite/ld-x86-64/pr24151a.s: Likewise. * testsuite/ld-x86-64/x86-64.exp: Run pr24151a and pr24151a-x32.
2019-02-06 03:45:23 +01:00
2019-02-05 H.J. Lu <hongjiu.lu@intel.com>
PR ld/24151
* elf64-x86-64.c (elf_x86_64_need_pic): Check
SYMBOL_DEFINED_NON_SHARED_P instead of def_regular.
(elf_x86_64_relocate_section): Move PIC check for PC-relative
relocations to ...
(elf_x86_64_check_relocs): Here.
(elf_x86_64_finish_dynamic_symbol): Use SYMBOL_DEFINED_NON_SHARED_P
to check if a symbol is defined in a non-shared object.
* elfxx-x86.h (SYMBOL_DEFINED_NON_SHARED_P): New.
Fix GCC9 warning on elf32-arm.c:elf32_arm_final_link_relocate Fedora Rawhide has just switched to GCC9, and now GDB doesn't compile because of a BFD warning: BUILDSTDERR: ../../bfd/elf32-arm.c: In function 'elf32_arm_final_link_relocate': BUILDSTDERR: ../../bfd/elf32-arm.c:10907:10: error: absolute value function 'labs' given an argument of type 'bfd_signed_vma' {aka 'long long int'} but has parameter of type 'long int' which may cause truncation of value [-Werror=absolute-value] BUILDSTDERR: 10907 | value = labs (relocation); BUILDSTDERR: | ^~~~ You can take a look at the full build log here: https://kojipkgs.fedoraproject.org//work/tasks/4828/32174828/build.log The fix is (apparently) simple: instead of using 'labs', we should use 'llabs', since we're passing a 'bfd_signed_vma' to it, which is at least a 'long long int', as far as I have checked. This is what this patch does. bfd/ChangeLog: 2019-01-25 Sergio Durigan Junior <sergiodj@redhat.com> * elf32-arm.c (elf32_arm_final_link_relocate): Use 'llabs' instead of 'labs' (and fix GCC warning).
2019-01-21 21:36:41 +01:00
2019-01-21 Sergio Durigan Junior <sergiodj@redhat.com>
* elf32-arm.c (elf32_arm_final_link_relocate): Use 'llabs' instead
of 'labs' (and fix GCC warning).
Updated Bulgarian and Russian translations for some of the binutils sub-directories
2019-01-25 12:48:55 +01:00
2019-01-25 Nick Clifton <nickc@redhat.com>
* po/ru.po: Updated Russian translation.
Updated translations for some of the binutils subdirectory.
2019-01-23 11:26:54 +01:00
2019-01-23 Nick Clifton <nickc@redhat.com>
* po/fr.po: Updated French translation.
Updated translations for various binutils subdirectories.
2019-01-21 13:59:20 +01:00
2019-01-21 Nick Clifton <nickc@redhat.com>
* po/pt.po: Updated Portuguese translation.
* po/uk.po: Updated Ukranian translation.
Fix spelling mistakes in BFD library. PR 24108 bfd * elf32-nds32.c (nds32_relocate_section): Add space between words in error message. * elfnn-riscv.c (riscv_version_mismatch): Fix spelling mistake in error message. (riscv_i_or_e_p): Likewise. (riscv_merge_arch_attr_info): Likewise. ld * testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d: Update expected error message.
2019-01-21 13:39:24 +01:00
2019-01-21 Yuri Chornoivan <yurchor@ukr.net>
PR 24108
* elf32-nds32.c (nds32_relocate_section): Add space between words
in error message.
* elfnn-riscv.c (riscv_version_mismatch): Fix spelling mistake in
error message.
(riscv_i_or_e_p): Likewise.
(riscv_merge_arch_attr_info): Likewise.
Change version to 2.32.51 and regenerate configure and pot files.
2019-01-19 17:51:42 +01:00
2019-01-19 Nick Clifton <nickc@redhat.com>
* version.m4: Reset to 2.32.51
* configure: Regenerate.
* po/bfd.pot: Regenerate.
Add markers for 2.32 branch to NEWS and ChangeLog files.
2019-01-19 16:55:50 +01:00
2018-06-24 Nick Clifton <nickc@redhat.com>
2.32 branch created.
Don't emit vendor attribute section if there is no attribute to emit. 2019-01-16 Kito Cheng <kito@andestech.com> bfd/ * elf-attrs.c (vendor_obj_attr_size): Return 0 if size is 0 even for OBJ_ATTR_PROC. gas/ * testsuite/gas/riscv/attribute-empty.d: New.
2019-01-16 22:37:35 +01:00
2019-01-16 Kito Cheng <kito@andestech.com>
* elf-attrs.c (vendor_obj_attr_size): Return 0 if size is 0 even
for OBJ_ATTR_PROC.
RISC-V: Support ELF attribute for gas and readelf. 2019-01-16 Kito Cheng <kito@andestech.com> Nelson Chu <nelson@andestech.com> bfd/ * elfnn-riscv.c (riscv_elf_obj_attrs_arg_type): New. (elf_backend_obj_attrs_vendor): Define. (elf_backend_obj_attrs_section_type): Likewise. (elf_backend_obj_attrs_section): Likewise. (elf_backend_obj_attrs_arg_type): Define as riscv_elf_obj_attrs_arg_type. * elfxx-riscv.c (riscv_estimate_digit): New. (riscv_estimate_arch_strlen1): Likewise. (riscv_estimate_arch_strlen): Likewise. (riscv_arch_str1): Likewise. (riscv_arch_str): Likewise. * elfxx-riscv.h (riscv_arch_str): Declare. binutils/ * readelf.c (get_riscv_section_type_name): New function. (get_section_type_name): Add handler for RISC-V. (riscv_attr_tag_t): Declare. (riscv_attr_tag): New. (display_riscv_attribute): New function. (process_attributes): Add handler for RISC-V. * testsuite/binutils-all/strip-3.d: Remove .riscv.attribute section. gas/ * config/tc-riscv.c (DEFAULT_RISCV_ATTR): Define to 0 if not defined. (riscv_set_options): Add `arch_attr` field. (riscv_opts): Set default value for arch_attr. (riscv_write_out_arch_attr): New. (riscv_set_public_attributes): Likewise. (riscv_md_end): Likewise. (riscv_convert_symbolic_attribute): Likewise. (s_riscv_attribute): Likewise. (explicit_arch_attr): Likewise. (riscv_pseudo_table): Add .attribute to the table. (options): Add OPTION_ARCH_ATTR and OPTION_NO_ARCH_ATTR enumeration constants. (md_longopts): Add `march-attr' and `mno-arch-attr' options. (md_parse_option): Handle the new options. (md_show_usage): Document the `march-attr' option. * config/tc-riscv.h (md_end): Define as riscv_md_end (riscv_md_end): Declare. (CONVERT_SYMBOLIC_ATTRIBUTE): Define as riscv_convert_symbolic_attribute. (riscv_convert_symbolic_attribute): Declare. (start_assemble): Declare. * testsuite/gas/elf/elf.exp: Adjust test case for section2.e. * testsuite/gas/elf/section2.e-riscv: New. * testsuite/gas/riscv/attribute-01.d: New test * testsuite/gas/riscv/attribute-02.d: Likewise. * testsuite/gas/riscv/attribute-03.d: Likewise. * testsuite/gas/riscv/attribute-04.d: Likewise. * testsuite/gas/riscv/attribute-04.s: Likewise. * testsuite/gas/riscv/attribute-05.d: Likewise. * testsuite/gas/riscv/attribute-05.s: Likewise. * testsuite/gas/riscv/attribute-06.d: Likewise. * testsuite/gas/riscv/attribute-06.s: Likewise. * testsuite/gas/riscv/attribute-07.d: Likewise. * testsuite/gas/riscv/attribute-07.s: Likewise. * testsuite/gas/riscv/attribute-08.d: Likewise. * testsuite/gas/riscv/attribute-08.s: Likewise. * testsuite/gas/riscv/attribute-unknown.d: Likewise. * testsuite/gas/riscv/attribute-unknown.s: Likewise. * testsuite/gas/riscv/empty.l: Likewise. * doc/c-riscv.texi (.attribute): Add documentation. * configure.ac (--enable-default-riscv-attribute): New options. * configure: Re-generate. * config.in: Re-generate. include/ * elf/riscv.h (SHT_RISCV_ATTRIBUTES): Define. (Tag_RISCV_arch): Likewise. (Tag_RISCV_priv_spec): Likewise. (Tag_RISCV_priv_spec_minor): Likewise. (Tag_RISCV_priv_spec_revision): Likewise. (Tag_RISCV_unaligned_access): Likewise. (Tag_RISCV_stack_align): Likewise.
2019-01-16 22:14:59 +01:00
2019-01-16 Kito Cheng <kito@andestech.com>
Nelson Chu <nelson@andestech.com>
RISC-V: Merge ELF attribute for ld. 2019-01-16 Kito Cheng <kito@andestech.com> Nelson Chu <nelson@andestech.com> bfd/ * elfnn-riscv.c (in_subsets): New. (out_subsets): Likewise. (merged_subsets): Likewise. (riscv_std_ext_p): Likewise. (riscv_non_std_ext_p): Likewise. (riscv_std_sv_ext_p): Likewise. (riscv_non_std_sv_ext_p): Likewise. (riscv_version_mismatch): Likewise. (riscv_i_or_e_p): Likewise. (riscv_merge_std_ext): Likewise. (riscv_merge_non_std_and_sv_ext): Likewise. (riscv_merge_arch_attr_info): Likewise. (riscv_merge_attributes): Likewise. (_bfd_riscv_elf_merge_private_bfd_data): Merge attribute. ld/ * testsuite/ld-elf/orphan-region.d: XFAIL for RISC-V, because add new section. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Add new tests. * testsuite/ld-riscv-elf/attr-merge-arch-01.d: New test. * testsuite/ld-riscv-elf/attr-merge-arch-01a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-01b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-02a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-02b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-failed-01a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-failed-01b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-stack-align-a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-stack-align-b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-stack-align-failed-a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-stack-align-failed-b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-stack-align-failed.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-01a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-01b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-02a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-02b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-03a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-03b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-04a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-04b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-05a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-05b.s: Likewise.
2019-01-16 22:28:35 +01:00
* elfnn-riscv.c (in_subsets): New.
(out_subsets): Likewise.
(merged_subsets): Likewise.
(riscv_std_ext_p): Likewise.
(riscv_non_std_ext_p): Likewise.
(riscv_std_sv_ext_p): Likewise.
(riscv_non_std_sv_ext_p): Likewise.
(riscv_version_mismatch): Likewise.
(riscv_i_or_e_p): Likewise.
(riscv_merge_std_ext): Likewise.
(riscv_merge_non_std_and_sv_ext): Likewise.
(riscv_merge_arch_attr_info): Likewise.
(riscv_merge_attributes): Likewise.
(_bfd_riscv_elf_merge_private_bfd_data): Merge attribute.
RISC-V: Support ELF attribute for gas and readelf. 2019-01-16 Kito Cheng <kito@andestech.com> Nelson Chu <nelson@andestech.com> bfd/ * elfnn-riscv.c (riscv_elf_obj_attrs_arg_type): New. (elf_backend_obj_attrs_vendor): Define. (elf_backend_obj_attrs_section_type): Likewise. (elf_backend_obj_attrs_section): Likewise. (elf_backend_obj_attrs_arg_type): Define as riscv_elf_obj_attrs_arg_type. * elfxx-riscv.c (riscv_estimate_digit): New. (riscv_estimate_arch_strlen1): Likewise. (riscv_estimate_arch_strlen): Likewise. (riscv_arch_str1): Likewise. (riscv_arch_str): Likewise. * elfxx-riscv.h (riscv_arch_str): Declare. binutils/ * readelf.c (get_riscv_section_type_name): New function. (get_section_type_name): Add handler for RISC-V. (riscv_attr_tag_t): Declare. (riscv_attr_tag): New. (display_riscv_attribute): New function. (process_attributes): Add handler for RISC-V. * testsuite/binutils-all/strip-3.d: Remove .riscv.attribute section. gas/ * config/tc-riscv.c (DEFAULT_RISCV_ATTR): Define to 0 if not defined. (riscv_set_options): Add `arch_attr` field. (riscv_opts): Set default value for arch_attr. (riscv_write_out_arch_attr): New. (riscv_set_public_attributes): Likewise. (riscv_md_end): Likewise. (riscv_convert_symbolic_attribute): Likewise. (s_riscv_attribute): Likewise. (explicit_arch_attr): Likewise. (riscv_pseudo_table): Add .attribute to the table. (options): Add OPTION_ARCH_ATTR and OPTION_NO_ARCH_ATTR enumeration constants. (md_longopts): Add `march-attr' and `mno-arch-attr' options. (md_parse_option): Handle the new options. (md_show_usage): Document the `march-attr' option. * config/tc-riscv.h (md_end): Define as riscv_md_end (riscv_md_end): Declare. (CONVERT_SYMBOLIC_ATTRIBUTE): Define as riscv_convert_symbolic_attribute. (riscv_convert_symbolic_attribute): Declare. (start_assemble): Declare. * testsuite/gas/elf/elf.exp: Adjust test case for section2.e. * testsuite/gas/elf/section2.e-riscv: New. * testsuite/gas/riscv/attribute-01.d: New test * testsuite/gas/riscv/attribute-02.d: Likewise. * testsuite/gas/riscv/attribute-03.d: Likewise. * testsuite/gas/riscv/attribute-04.d: Likewise. * testsuite/gas/riscv/attribute-04.s: Likewise. * testsuite/gas/riscv/attribute-05.d: Likewise. * testsuite/gas/riscv/attribute-05.s: Likewise. * testsuite/gas/riscv/attribute-06.d: Likewise. * testsuite/gas/riscv/attribute-06.s: Likewise. * testsuite/gas/riscv/attribute-07.d: Likewise. * testsuite/gas/riscv/attribute-07.s: Likewise. * testsuite/gas/riscv/attribute-08.d: Likewise. * testsuite/gas/riscv/attribute-08.s: Likewise. * testsuite/gas/riscv/attribute-unknown.d: Likewise. * testsuite/gas/riscv/attribute-unknown.s: Likewise. * testsuite/gas/riscv/empty.l: Likewise. * doc/c-riscv.texi (.attribute): Add documentation. * configure.ac (--enable-default-riscv-attribute): New options. * configure: Re-generate. * config.in: Re-generate. include/ * elf/riscv.h (SHT_RISCV_ATTRIBUTES): Define. (Tag_RISCV_arch): Likewise. (Tag_RISCV_priv_spec): Likewise. (Tag_RISCV_priv_spec_minor): Likewise. (Tag_RISCV_priv_spec_revision): Likewise. (Tag_RISCV_unaligned_access): Likewise. (Tag_RISCV_stack_align): Likewise.
2019-01-16 22:14:59 +01:00
* elfnn-riscv.c (riscv_elf_obj_attrs_arg_type): New.
(elf_backend_obj_attrs_vendor): Define.
(elf_backend_obj_attrs_section_type): Likewise.
(elf_backend_obj_attrs_section): Likewise.
(elf_backend_obj_attrs_arg_type): Define as
riscv_elf_obj_attrs_arg_type.
* elfxx-riscv.c (riscv_estimate_digit): New.
(riscv_estimate_arch_strlen1): Likewise.
(riscv_estimate_arch_strlen): Likewise.
(riscv_arch_str1): Likewise.
(riscv_arch_str): Likewise.
* elfxx-riscv.h (riscv_arch_str): Declare.
S12Z: Emit RELOC_S12Z_OPR instead of RELOC_EXT24 where appropriate. When assembling instructions which involve OPR references, emit RELOC_S12Z_OPR instead of RELOC_EXT24. bfd/ * bfd-in2.h [BFD_RELOC_S12Z_OPR]: New reloc. * libbfd.h: regen. * elf32-s12z.c (eld_s12z_howto_table): R_S12Z_OPR takes non zero source field. (md_apply_fix): Apply final fix to BFD_RELOC_S12Z_OPR. * reloc.c[BFD_RELOC_S12Z_OPR]: New reloc. gas/ * config/tc-s12z.c (emit_opr): Emit BFD_RELOC_S12Z_OPR instead of BFD_RELOC_24. * testsuite/gas/s12z/opr-indirect-expr.d: Expect R_S12Z_OPR instead of R_S12Z_EXT24.
2019-01-16 14:34:50 +01:00
2019-01-14 John Darrington <john@darrington.wattle.id.au>
* bfd-in2.h [BFD_RELOC_S12Z_OPR]: New reloc.
* libbfd.h: regen.
* elf32-s12z.c (eld_s12z_howto_table): R_S12Z_OPR takes non zero
source field. (md_apply_fix): Apply final fix
to BFD_RELOC_S12Z_OPR.
* reloc.c[BFD_RELOC_S12Z_OPR]: New reloc.
Add support to GNU ld to separate got related plt entries from normal ones in order to be able to switch the non-plt got entries to read-only after startup, conforming to revised Linux for zSeries ABI. PR 20133 * emulparams/elf64_s390.sh (SEPARATE_GOTPLT): Define. * emulparams/elf_s390.sh (SEPARATE_GOTPLT): Define. * testsuite/ld-s390/gotreloc_31-1.dd: Update expected output. * testsuite/ld-s390/tlsbin.dd: Likewise. * testsuite/ld-s390/tlsbin.rd: Likewise. * testsuite/ld-s390/tlsbin.sd: Likewise. * testsuite/ld-s390/tlsbin_64.dd: Likewise. * testsuite/ld-s390/tlsbin_64.rd: Likewise. * testsuite/ld-s390/tlsbin_64.sd: Likewise. * testsuite/ld-s390/tlspic.dd: Likewise. * testsuite/ld-s390/tlspic.rd: Likewise. * testsuite/ld-s390/tlspic.sd: Likewise. * testsuite/ld-s390/tlspic_64.dd: Likewise. * testsuite/ld-s390/tlspic_64.rd: Likewise. * testsuite/ld-s390/tlspic_64.sd: Likewise. * testsuite/ld-s390/s390.exp: Skip s390 tests for tpf targets.
2019-01-14 17:00:14 +01:00
2019-01-14 Maamoun Tarsha <maamountk@hotmail.com>
Correct PR number in prevvious delta
2019-01-14 17:04:18 +01:00
PR 20113
Add support to GNU ld to separate got related plt entries from normal ones in order to be able to switch the non-plt got entries to read-only after startup, conforming to revised Linux for zSeries ABI. PR 20133 * emulparams/elf64_s390.sh (SEPARATE_GOTPLT): Define. * emulparams/elf_s390.sh (SEPARATE_GOTPLT): Define. * testsuite/ld-s390/gotreloc_31-1.dd: Update expected output. * testsuite/ld-s390/tlsbin.dd: Likewise. * testsuite/ld-s390/tlsbin.rd: Likewise. * testsuite/ld-s390/tlsbin.sd: Likewise. * testsuite/ld-s390/tlsbin_64.dd: Likewise. * testsuite/ld-s390/tlsbin_64.rd: Likewise. * testsuite/ld-s390/tlsbin_64.sd: Likewise. * testsuite/ld-s390/tlspic.dd: Likewise. * testsuite/ld-s390/tlspic.rd: Likewise. * testsuite/ld-s390/tlspic.sd: Likewise. * testsuite/ld-s390/tlspic_64.dd: Likewise. * testsuite/ld-s390/tlspic_64.rd: Likewise. * testsuite/ld-s390/tlspic_64.sd: Likewise. * testsuite/ld-s390/s390.exp: Skip s390 tests for tpf targets.
2019-01-14 17:00:14 +01:00
* elf32-s390.c (allocate_dynrelocs): Update comment.
Adjust bfd/warning.m4 egrep patterns Adjust the `bfd/warning.m4` `egrep` patterns to handle preprocessors that do not define `__GNUC__`, leaving the string in the output. bfd/ * warning.m4: Adjust egrep pattern for non-GNU compilers. * configure: Regenerate. binutils/ * configure: Regenerate. gas/ * configure: Regenerate. gold/ * configure: Regenerate. gprof/ * configure: Regenerate. ld/ * configure: Regenerate. opcodes/ * configure: Regenerate.
2019-01-09 04:21:08 +01:00
2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
* warning.m4: Adjust egrep pattern for non-GNU compilers.
* configure: Regenerate.
PR24065, 32-bit objcopy fails with 64-bit address ... out of range PR 23699 PR 24065 * ihex.c (ihex_write_object_contents): Properly check 32-bit address range.
2019-01-08 12:51:57 +01:00
2019-01-08 Alan Modra <amodra@gmail.com>
PR 23699
PR 24065
* ihex.c (ihex_write_object_contents): Properly check 32-bit
address range.
RX: bfd - Add RXv3 support. * bfd/archures.c: Add bfd_mach_rx_v2 and bfd_mach_rx_v3. * bfd/bfd-in2.h: Regenerate. * bfd/cpu-rx.c (arch_info_struct): Add RXv2 and RXv3 entry. * bfd/elf32-rx.c (elf32_rx_machine): Add RXv2 and RXv3 support.
2018-12-25 11:58:54 +01:00
2019-01-05 Yoshinori Sato <ysato@users.sourceforge.jp>
* bfd/archures.c: Add bfd_mach_rx_v2 and bfd_mach_rx_v3.
* bfd/bfd-in2.h: Regenerate.
* bfd/cpu-rx.c (arch_info_struct): Add RXv2 and RXv3 entry.
* bfd/elf32-rx.c (elf32_rx_machine): Add RXv2 and RXv3 support.
Change the default for the CSKY target to be little endian. * config.bfd (csky-*-elf* | csky-*-linux*): Modify the csky default target, little endian target is more suitable.
2019-01-04 14:56:46 +01:00
2019-01-04 Lifang Xia <lifang_xia@c-sky.com>
* config.bfd (csky-*-elf* | csky-*-linux*): Modify the csky
default target, little endian target is more suitable.
PR24061, powerpc-ibm-aix-ar sets bogus file permissions when extracting Mode field should be read in octal, all the rest in decimal. Do so. PR 24061 PR 21786 * coff-rs6000.c (GET_VALUE_IN_FIELD): Add base parameter and adjust all callers. (EQ_VALUE_IN_FIELD): Likewise. * coff64-rs6000.c (GET_VALUE_IN_FIELD): Likewise.
2019-01-04 02:48:36 +01:00
2019-01-04 Alan Modra <amodra@gmail.com>
PR 24061
PR 21786
* coff-rs6000.c (GET_VALUE_IN_FIELD): Add base parameter and
adjust all callers.
(EQ_VALUE_IN_FIELD): Likewise.
* coff64-rs6000.c (GET_VALUE_IN_FIELD): Likewise.
Update year range in copyright notice of binutils files
2019-01-01 11:31:27 +01:00
2019-01-01 Alan Modra <amodra@gmail.com>
Update year range in copyright notice of all files.
ChangeLog rotation
2019-01-01 11:53:15 +01:00
For older changes see ChangeLog-2018
New 2016 binutils ChangeLog files Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01 11:44:31 +01:00
ChangeLog rotation
2019-01-01 11:53:15 +01:00
Copyright (C) 2019 Free Software Foundation, Inc.
New 2016 binutils ChangeLog files Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01 11:44:31 +01:00
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.
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