2017-02-15 17:54:21 +01:00
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2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
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* aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
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(aarch64_sys_reg_supported_p): Handle them.
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2017-02-15 11:57:51 +01:00
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2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
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* arc-opc.c (UIMM6_20R): Define.
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(SIMM12_20): Use above.
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(SIMM12_20R): Define.
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(SIMM3_5_S): Use above.
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(UIMM7_A32_11R_S): Define.
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(UIMM7_9_S): Use above.
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(UIMM3_13R_S): Define.
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(SIMM11_A32_7_S): Use above.
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(SIMM9_8R): Define.
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(UIMM10_A32_8_S): Use above.
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(UIMM8_8R_S): Define.
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(W6): Use above.
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(arc_relax_opcodes): Use all above defines.
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2017-02-15 09:52:53 +01:00
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2017-02-15 Vineet Gupta <vgupta@synopsys.com>
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* arc-regs.h: Distinguish some of the registers different on
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ARC700 and HS38 cpus.
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2017-02-14 11:08:21 +01:00
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2017-02-14 Alan Modra <amodra@gmail.com>
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PR 21118
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* ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
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with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
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2017-02-11 07:47:59 +01:00
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2017-02-11 Stafford Horne <shorne@gmail.com>
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Alan Modra <amodra@gmail.com>
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* cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
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Use insn_bytes_value and insn_int_value directly instead. Don't
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free allocated memory until function exit.
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2017-02-10 05:18:23 +01:00
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2017-02-10 Nicholas Piggin <npiggin@gmail.com>
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* ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
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2017-02-03 10:04:21 +01:00
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2017-02-03 Nick Clifton <nickc@redhat.com>
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PR 21096
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* aarch64-opc.c (print_register_list): Ensure that the register
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list index will fir into the tb buffer.
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(print_register_offset_address): Likewise.
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* tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
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2017-01-27 13:00:55 +01:00
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2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
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PR 21056
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* tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
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instructions when the previous fetch packet ends with a 32-bit
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instruction.
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2017-01-25 13:19:27 +01:00
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2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
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* pru-opc.c: Remove vague reference to a future GDB port.
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2017-01-20 13:25:07 +01:00
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2017-01-20 Nick Clifton <nickc@redhat.com>
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* po/ga.po: Updated Irish translation.
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2017-01-18 18:08:34 +01:00
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2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
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* arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
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2017-01-13 13:27:39 +01:00
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2017-01-13 Yao Qi <yao.qi@linaro.org>
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* m68k-dis.c (match_insn_m68k): Extend comments. Return -1
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if FETCH_DATA returns 0.
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(m68k_scan_mask): Likewise.
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(print_insn_m68k): Update code to handle -1 return value.
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2017-01-13 13:21:22 +01:00
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2017-01-13 Yao Qi <yao.qi@linaro.org>
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* m68k-dis.c (enum print_insn_arg_error): New.
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(NEXTBYTE): Replace -3 with
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PRINT_INSN_ARG_MEMORY_ERROR.
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(NEXTULONG): Likewise.
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(NEXTSINGLE): Likewise.
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(NEXTDOUBLE): Likewise.
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(NEXTDOUBLE): Likewise.
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(NEXTPACKED): Likewise.
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(FETCH_ARG): Likewise.
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(FETCH_DATA): Update comments.
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(print_insn_arg): Update comments. Replace magic numbers with
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enum.
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(match_insn_m68k): Likewise.
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2017-01-12 17:42:17 +01:00
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2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
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* i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
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* i386-dis-evex.h (evex_table): Updated.
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* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
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CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
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(cpu_flags): Add CpuAVX512_VPOPCNTDQ.
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* i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
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(i386_cpu_flags): Add cpuavx512_vpopcntdq.
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* i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
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* i386-init.h: Regenerate.
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* i386-tbl.h: Ditto.
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2017-01-12 10:40:41 +01:00
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2017-01-12 Yao Qi <yao.qi@linaro.org>
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* msp430-dis.c (msp430_singleoperand): Return -1 if
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msp430dis_opcode_signed returns false.
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(msp430_doubleoperand): Likewise.
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(msp430_branchinstr): Return -1 if
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msp430dis_opcode_unsigned returns false.
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(msp430x_calla_instr): Likewise.
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(print_insn_msp430): Likewise.
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2017-01-05 10:11:47 +01:00
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2017-01-05 Nick Clifton <nickc@redhat.com>
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PR 20946
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* frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
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could not be matched.
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(frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
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NULL.
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2017-01-04 13:27:10 +01:00
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2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
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* aarch64-tbl.h (RCPC, RCPC_INSN): Define.
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(aarch64_opcode_table): Use RCPC_INSN.
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2017-01-03 18:42:01 +01:00
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2017-01-03 Kito Cheng <kito.cheng@gmail.com>
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* riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
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extension.
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* riscv-opcodes/all-opcodes: Likewise.
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2017-01-03 17:02:36 +01:00
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2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
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* riscv-dis.c (print_insn_args): Add fall through comment.
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2017-01-03 16:51:11 +01:00
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2017-01-03 Nick Clifton <nickc@redhat.com>
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* po/sr.po: New Serbian translation.
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* configure.ac (ALL_LINGUAS): Add sr.
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* configure: Regenerate.
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2017-01-02 14:27:58 +01:00
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2017-01-02 Alan Modra <amodra@gmail.com>
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* epiphany-desc.h: Regenerate.
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* epiphany-opc.h: Regenerate.
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* fr30-desc.h: Regenerate.
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* fr30-opc.h: Regenerate.
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* frv-desc.h: Regenerate.
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* frv-opc.h: Regenerate.
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* ip2k-desc.h: Regenerate.
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* ip2k-opc.h: Regenerate.
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* iq2000-desc.h: Regenerate.
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* iq2000-opc.h: Regenerate.
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* lm32-desc.h: Regenerate.
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* lm32-opc.h: Regenerate.
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* m32c-desc.h: Regenerate.
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* m32c-opc.h: Regenerate.
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* m32r-desc.h: Regenerate.
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* m32r-opc.h: Regenerate.
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* mep-desc.h: Regenerate.
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* mep-opc.h: Regenerate.
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* mt-desc.h: Regenerate.
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* mt-opc.h: Regenerate.
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* or1k-desc.h: Regenerate.
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* or1k-opc.h: Regenerate.
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* xc16x-desc.h: Regenerate.
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* xc16x-opc.h: Regenerate.
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* xstormy16-desc.h: Regenerate.
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* xstormy16-opc.h: Regenerate.
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2017-01-02 04:36:43 +01:00
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2017-01-02 Alan Modra <amodra@gmail.com>
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Update year range in copyright notice of all files.
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2017-01-02 04:25:05 +01:00
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For older changes see ChangeLog-2016
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2016-01-01 11:44:31 +01:00
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2017-01-02 04:25:05 +01:00
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Copyright (C) 2017 Free Software Foundation, Inc.
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2016-01-01 11:44:31 +01:00
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved.
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Local Variables:
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mode: change-log
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left-margin: 8
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fill-column: 74
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version-control: never
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End:
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