2012-08-13 16:52:54 +02:00
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/* This file is automatically generated by aarch64-gen. Do not edit! */
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2015-01-01 15:15:26 +01:00
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/* Copyright (C) 2012-2015 Free Software Foundation, Inc.
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2012-08-13 16:52:54 +02:00
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Contributed by ARM Ltd.
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; see the file COPYING3. If not,
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see <http://www.gnu.org/licenses/>. */
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#include "sysdep.h"
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#include "aarch64-dis.h"
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/* Called by aarch64_opcode_lookup. */
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static int
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aarch64_opcode_lookup_1 (uint32_t word)
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{
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if (((word >> 26) & 0x1) == 0)
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{
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if (((word >> 25) & 0x1) == 0)
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{
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if (((word >> 27) & 0x1) == 0)
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{
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if (((word >> 24) & 0x1) == 0)
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{
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if (((word >> 31) & 0x1) == 0)
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{
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/* 33222222222211111111110000000000
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10987654321098765432109876543210
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xxxxxxxxxxxxxxxxxxxxxxxx0000xxx0
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adr. */
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2015-12-14 18:40:03 +01:00
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return 1111;
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2012-08-13 16:52:54 +02:00
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}
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else
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{
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/* 33222222222211111111110000000000
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10987654321098765432109876543210
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xxxxxxxxxxxxxxxxxxxxxxxx0000xxx1
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adrp. */
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2015-12-14 18:40:03 +01:00
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return 1112;
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2012-08-13 16:52:54 +02:00
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}
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}
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else
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{
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if (((word >> 29) & 0x1) == 0)
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{
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if (((word >> 30) & 0x1) == 0)
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{
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/* 33222222222211111111110000000000
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10987654321098765432109876543210
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xxxxxxxxxxxxxxxxxxxxxxxx1000x00x
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add. */
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return 12;
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}
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else
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{
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/* 33222222222211111111110000000000
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10987654321098765432109876543210
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xxxxxxxxxxxxxxxxxxxxxxxx1000x01x
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sub. */
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return 16;
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}
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}
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else
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{
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if (((word >> 30) & 0x1) == 0)
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{
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/* 33222222222211111111110000000000
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10987654321098765432109876543210
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xxxxxxxxxxxxxxxxxxxxxxxx1000x10x
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adds. */
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return 14;
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}
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else
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{
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/* 33222222222211111111110000000000
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10987654321098765432109876543210
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xxxxxxxxxxxxxxxxxxxxxxxx1000x11x
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subs. */
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return 17;
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}
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}
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}
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}
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else
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{
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if (((word >> 28) & 0x1) == 0)
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{
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if (((word >> 22) & 0x1) == 0)
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{
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if (((word >> 23) & 0x1) == 0)
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{
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if (((word >> 29) & 0x1) == 0)
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{
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if (((word >> 15) & 0x1) == 0)
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{
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if (((word >> 21) & 0x1) == 0)
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{
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if (((word >> 31) & 0x1) == 0)
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{
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if (((word >> 30) & 0x1) == 0)
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{
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/* 33222222222211111111110000000000
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10987654321098765432109876543210
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xxxxxxxxxxxxxxx0xxxxx000x0010000
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stxrb. */
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2015-12-14 18:40:03 +01:00
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return 869;
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2012-08-13 16:52:54 +02:00
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}
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else
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{
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/* 33222222222211111111110000000000
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10987654321098765432109876543210
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xxxxxxxxxxxxxxx0xxxxx000x0010010
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stxrh. */
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2015-12-14 18:40:03 +01:00
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return 875;
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2012-08-13 16:52:54 +02:00
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}
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}
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else
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{
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/* 33222222222211111111110000000000
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10987654321098765432109876543210
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xxxxxxxxxxxxxxx0xxxxx000x00100x1
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stxr. */
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2015-12-14 18:40:03 +01:00
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return 881;
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2012-08-13 16:52:54 +02:00
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}
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}
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else
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{
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2014-09-03 15:40:41 +02:00
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if (((word >> 31) & 0x1) == 0)
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{
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/* 33222222222211111111110000000000
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10987654321098765432109876543210
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xxxxxxxxxxxxxxx0xxxxx100x00100x0
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casp. */
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2015-12-14 18:40:03 +01:00
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return 946;
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2014-09-03 15:40:41 +02:00
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}
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else
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{
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/* 33222222222211111111110000000000
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10987654321098765432109876543210
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xxxxxxxxxxxxxxx0xxxxx100x00100x1
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stxp. */
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2015-12-14 18:40:03 +01:00
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return 883;
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2014-09-03 15:40:41 +02:00
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}
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2012-08-13 16:52:54 +02:00
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}
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}
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else
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{
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if (((word >> 21) & 0x1) == 0)
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{
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if (((word >> 31) & 0x1) == 0)
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{
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if (((word >> 30) & 0x1) == 0)
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{
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/* 33222222222211111111110000000000
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10987654321098765432109876543210
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xxxxxxxxxxxxxxx1xxxxx000x0010000
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stlxrb. */
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2015-12-14 18:40:03 +01:00
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return 870;
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2012-08-13 16:52:54 +02:00
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}
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else
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{
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/* 33222222222211111111110000000000
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10987654321098765432109876543210
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xxxxxxxxxxxxxxx1xxxxx000x0010010
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stlxrh. */
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2015-12-14 18:40:03 +01:00
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return 876;
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2012-08-13 16:52:54 +02:00
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}
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}
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else
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{
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/* 33222222222211111111110000000000
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10987654321098765432109876543210
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xxxxxxxxxxxxxxx1xxxxx000x00100x1
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stlxr. */
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2015-12-14 18:40:03 +01:00
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return 882;
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2012-08-13 16:52:54 +02:00
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}
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}
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else
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{
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2014-09-03 15:40:41 +02:00
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if (((word >> 31) & 0x1) == 0)
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{
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/* 33222222222211111111110000000000
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10987654321098765432109876543210
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xxxxxxxxxxxxxxx1xxxxx100x00100x0
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caspl. */
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2015-12-14 18:40:03 +01:00
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return 948;
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2014-09-03 15:40:41 +02:00
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}
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else
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{
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/* 33222222222211111111110000000000
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10987654321098765432109876543210
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xxxxxxxxxxxxxxx1xxxxx100x00100x1
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stlxp. */
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2015-12-14 18:40:03 +01:00
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return 884;
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2014-09-03 15:40:41 +02:00
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}
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2012-08-13 16:52:54 +02:00
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}
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}
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}
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else
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{
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/* 33222222222211111111110000000000
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10987654321098765432109876543210
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xxxxxxxxxxxxxxxxxxxxxx00x00101xx
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stnp. */
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2015-12-14 18:40:03 +01:00
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return 897;
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2012-08-13 16:52:54 +02:00
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}
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}
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else
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{
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if (((word >> 29) & 0x1) == 0)
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{
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2014-09-03 15:40:41 +02:00
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if (((word >> 15) & 0x1) == 0)
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2012-08-13 16:52:54 +02:00
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{
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2015-06-02 12:29:15 +02:00
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if (((word >> 21) & 0x1) == 0)
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2012-08-13 16:52:54 +02:00
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{
|
2015-06-02 12:29:15 +02:00
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if (((word >> 31) & 0x1) == 0)
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2014-09-03 15:40:41 +02:00
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{
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/* 33222222222211111111110000000000
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10987654321098765432109876543210
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2015-06-02 12:29:15 +02:00
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xxxxxxxxxxxxxxx0xxxxx001x00100x0
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stllrb. */
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2015-12-14 18:40:03 +01:00
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return 895;
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2014-09-03 15:40:41 +02:00
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}
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else
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{
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/* 33222222222211111111110000000000
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10987654321098765432109876543210
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2015-06-02 12:29:15 +02:00
|
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xxxxxxxxxxxxxxx0xxxxx001x00100x1
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stllr. */
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2015-12-14 18:40:03 +01:00
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return 894;
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2014-09-03 15:40:41 +02:00
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}
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2012-08-13 16:52:54 +02:00
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}
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else
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{
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2015-06-02 12:29:15 +02:00
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if (((word >> 31) & 0x1) == 0)
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{
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if (((word >> 30) & 0x1) == 0)
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{
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/* 33222222222211111111110000000000
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10987654321098765432109876543210
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xxxxxxxxxxxxxxx0xxxxx101x0010000
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casb. */
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2015-12-14 18:40:03 +01:00
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return 934;
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2015-06-02 12:29:15 +02:00
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}
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else
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{
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/* 33222222222211111111110000000000
|
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10987654321098765432109876543210
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xxxxxxxxxxxxxxx0xxxxx101x0010010
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cash. */
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2015-12-14 18:40:03 +01:00
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return 935;
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2015-06-02 12:29:15 +02:00
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}
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}
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else
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{
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/* 33222222222211111111110000000000
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10987654321098765432109876543210
|
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xxxxxxxxxxxxxxx0xxxxx101x00100x1
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cas. */
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2015-12-14 18:40:03 +01:00
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return 936;
|
2015-06-02 12:29:15 +02:00
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}
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2012-08-13 16:52:54 +02:00
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}
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}
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else
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{
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2014-09-03 15:40:41 +02:00
|
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if (((word >> 21) & 0x1) == 0)
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{
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if (((word >> 31) & 0x1) == 0)
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{
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if (((word >> 30) & 0x1) == 0)
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{
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/* 33222222222211111111110000000000
|
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10987654321098765432109876543210
|
|
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|
xxxxxxxxxxxxxxx1xxxxx001x0010000
|
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|
stlrb. */
|
2015-12-14 18:40:03 +01:00
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return 873;
|
2014-09-03 15:40:41 +02:00
|
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}
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|
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|
else
|
|
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|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxx1xxxxx001x0010010
|
|
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|
stlrh. */
|
2015-12-14 18:40:03 +01:00
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return 879;
|
2014-09-03 15:40:41 +02:00
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}
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}
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else
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{
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|
/* 33222222222211111111110000000000
|
|
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|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxx1xxxxx001x00100x1
|
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|
stlr. */
|
2015-12-14 18:40:03 +01:00
|
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return 889;
|
2014-09-03 15:40:41 +02:00
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|
}
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|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxx1xxxxx101x0010000
|
|
|
|
caslb. */
|
2015-12-14 18:40:03 +01:00
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return 938;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxx1xxxxx101x0010010
|
|
|
|
caslh. */
|
2015-12-14 18:40:03 +01:00
|
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|
return 941;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxx1xxxxx101x00100x1
|
|
|
|
casl. */
|
2015-12-14 18:40:03 +01:00
|
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return 944;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxx01x00101xx
|
|
|
|
stp. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 906;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 21) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxx0xxxxx010x0010000
|
|
|
|
ldxrb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 871;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxx0xxxxx010x0010010
|
|
|
|
ldxrh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 877;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxx0xxxxx010x00100x1
|
|
|
|
ldxr. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 885;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2014-09-03 15:40:41 +02:00
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxx0xxxxx110x00100x0
|
|
|
|
caspa. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 947;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxx0xxxxx110x00100x1
|
|
|
|
ldxp. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 887;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 21) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxx1xxxxx010x0010000
|
|
|
|
ldaxrb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 872;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxx1xxxxx010x0010010
|
|
|
|
ldaxrh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 878;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxx1xxxxx010x00100x1
|
|
|
|
ldaxr. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 886;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2014-09-03 15:40:41 +02:00
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxx1xxxxx110x00100x0
|
|
|
|
caspal. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 949;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxx1xxxxx110x00100x1
|
|
|
|
ldaxp. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 888;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxx10x001010x
|
|
|
|
ldnp. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 898;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxx10x001011x
|
|
|
|
ldpsw. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 905;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
2014-09-03 15:40:41 +02:00
|
|
|
if (((word >> 15) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
2015-06-02 12:29:15 +02:00
|
|
|
if (((word >> 21) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
2015-06-02 12:29:15 +02:00
|
|
|
if (((word >> 31) & 0x1) == 0)
|
2014-09-03 15:40:41 +02:00
|
|
|
{
|
2015-06-02 12:29:15 +02:00
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxx0xxxxx011x0010000
|
|
|
|
ldlarb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 892;
|
2015-06-02 12:29:15 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxx0xxxxx011x0010010
|
|
|
|
ldlarh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 893;
|
2015-06-02 12:29:15 +02:00
|
|
|
}
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
2015-06-02 12:29:15 +02:00
|
|
|
xxxxxxxxxxxxxxx0xxxxx011x00100x1
|
|
|
|
ldlar. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 891;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2015-06-02 12:29:15 +02:00
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxx0xxxxx111x0010000
|
|
|
|
casab. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 937;
|
2015-06-02 12:29:15 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxx0xxxxx111x0010010
|
|
|
|
casah. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 940;
|
2015-06-02 12:29:15 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxx0xxxxx111x00100x1
|
|
|
|
casa. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 943;
|
2015-06-02 12:29:15 +02:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2014-09-03 15:40:41 +02:00
|
|
|
if (((word >> 21) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxx1xxxxx011x0010000
|
|
|
|
ldarb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 874;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxx1xxxxx011x0010010
|
|
|
|
ldarh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 880;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxx1xxxxx011x00100x1
|
|
|
|
ldar. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 890;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxx1xxxxx111x0010000
|
|
|
|
casalb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 939;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxx1xxxxx111x0010010
|
|
|
|
casalh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 942;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxx1xxxxx111x00100x1
|
|
|
|
casal. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 945;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxx11x001010x
|
|
|
|
ldp. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 907;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxx11x001011x
|
|
|
|
ldpsw. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 910;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 24) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxxxx000110x0
|
|
|
|
ldr. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 911;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxxxx00011001
|
|
|
|
ldrsw. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 913;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxxxx00011011
|
|
|
|
prfm. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 914;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 10) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 11) & 0x1) == 0)
|
|
|
|
{
|
2014-09-03 15:40:41 +02:00
|
|
|
if (((word >> 21) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
2014-09-03 15:40:41 +02:00
|
|
|
if (((word >> 23) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
2014-09-03 15:40:41 +02:00
|
|
|
if (((word >> 22) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
2014-09-03 15:40:41 +02:00
|
|
|
if (((word >> 31) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
2014-09-03 15:40:41 +02:00
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00xxxxxxxxx00000011100
|
|
|
|
sturb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 857;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00xxxxxxxxx00000011110
|
|
|
|
sturh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 862;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
2014-09-03 15:40:41 +02:00
|
|
|
xxxxxxxxxx00xxxxxxxxx000000111x1
|
|
|
|
stur. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 865;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2014-09-03 15:40:41 +02:00
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00xxxxxxxxx01000011100
|
|
|
|
ldurb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 858;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00xxxxxxxxx01000011110
|
|
|
|
ldurh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 863;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00xxxxxxxxx010000111x1
|
|
|
|
ldur. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 866;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2014-09-03 15:40:41 +02:00
|
|
|
if (((word >> 30) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
2014-09-03 15:40:41 +02:00
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00xxxxxxxxx0x100011100
|
|
|
|
ldursb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 859;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00xxxxxxxxx0x100011101
|
|
|
|
ldursw. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 867;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00xxxxxxxxx0x100011110
|
|
|
|
ldursh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 864;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
2014-09-03 15:40:41 +02:00
|
|
|
xxxxxxxxxx00xxxxxxxxx0x100011111
|
|
|
|
prfum. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 868;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 12) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 22) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000000xxxxx10000011100
|
|
|
|
ldaddb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 962;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000000xxxxx10000011110
|
|
|
|
ldaddh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 963;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000000xxxxx100000111x1
|
|
|
|
ldadd. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 964;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000000xxxxx10100011100
|
|
|
|
ldaddab. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 965;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000000xxxxx10100011110
|
|
|
|
ldaddah. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 968;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000000xxxxx101000111x1
|
|
|
|
ldadda. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 971;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000000xxxxx11000011100
|
|
|
|
ldaddlb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 966;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000000xxxxx11000011110
|
|
|
|
ldaddlh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 969;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000000xxxxx110000111x1
|
|
|
|
ldaddl. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 972;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000000xxxxx11100011100
|
|
|
|
ldaddalb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 967;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000000xxxxx11100011110
|
|
|
|
ldaddalh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 970;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000000xxxxx111000111x1
|
|
|
|
ldaddal. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 973;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 22) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000001xxxxx10000011100
|
|
|
|
swpb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 950;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000001xxxxx10000011110
|
|
|
|
swph. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 951;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000001xxxxx100000111x1
|
|
|
|
swp. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 952;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000001xxxxx10100011100
|
|
|
|
swpab. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 953;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000001xxxxx10100011110
|
|
|
|
swpah. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 956;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000001xxxxx101000111x1
|
|
|
|
swpa. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 959;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000001xxxxx11000011100
|
|
|
|
swplb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 954;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000001xxxxx11000011110
|
|
|
|
swplh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 957;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000001xxxxx110000111x1
|
|
|
|
swpl. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 960;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000001xxxxx11100011100
|
|
|
|
swpalb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 955;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000001xxxxx11100011110
|
|
|
|
swpalh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 958;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000001xxxxx111000111x1
|
|
|
|
swpal. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 961;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 22) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00001xxxxxx10000011100
|
|
|
|
ldsmaxb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1010;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00001xxxxxx10000011110
|
|
|
|
ldsmaxh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1011;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00001xxxxxx100000111x1
|
|
|
|
ldsmax. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1012;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00001xxxxxx10100011100
|
|
|
|
ldsmaxab. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1013;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00001xxxxxx10100011110
|
|
|
|
ldsmaxah. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1016;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00001xxxxxx101000111x1
|
|
|
|
ldsmaxa. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1019;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00001xxxxxx11000011100
|
|
|
|
ldsmaxlb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1014;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00001xxxxxx11000011110
|
|
|
|
ldsmaxlh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1017;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00001xxxxxx110000111x1
|
|
|
|
ldsmaxl. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1020;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00001xxxxxx11100011100
|
|
|
|
ldsmaxalb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1015;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00001xxxxxx11100011110
|
|
|
|
ldsmaxalh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1018;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00001xxxxxx111000111x1
|
|
|
|
ldsmaxal. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1021;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 22) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00010xxxxxx10000011100
|
|
|
|
ldeorb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 986;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00010xxxxxx10000011110
|
|
|
|
ldeorh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 987;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00010xxxxxx100000111x1
|
|
|
|
ldeor. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 988;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00010xxxxxx10100011100
|
|
|
|
ldeorab. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 989;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00010xxxxxx10100011110
|
|
|
|
ldeorah. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 992;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00010xxxxxx101000111x1
|
|
|
|
ldeora. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 995;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00010xxxxxx11000011100
|
|
|
|
ldeorlb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 990;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00010xxxxxx11000011110
|
|
|
|
ldeorlh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 993;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00010xxxxxx110000111x1
|
|
|
|
ldeorl. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 996;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00010xxxxxx11100011100
|
|
|
|
ldeoralb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 991;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00010xxxxxx11100011110
|
|
|
|
ldeoralh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 994;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00010xxxxxx111000111x1
|
|
|
|
ldeoral. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 997;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 22) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00011xxxxxx10000011100
|
|
|
|
ldumaxb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1034;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00011xxxxxx10000011110
|
|
|
|
ldumaxh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1035;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00011xxxxxx100000111x1
|
|
|
|
ldumax. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1036;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00011xxxxxx10100011100
|
|
|
|
ldumaxab. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1037;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00011xxxxxx10100011110
|
|
|
|
ldumaxah. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1040;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00011xxxxxx101000111x1
|
|
|
|
ldumaxa. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1043;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00011xxxxxx11000011100
|
|
|
|
ldumaxlb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1038;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00011xxxxxx11000011110
|
|
|
|
ldumaxlh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1041;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00011xxxxxx110000111x1
|
|
|
|
ldumaxl. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1044;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00011xxxxxx11100011100
|
|
|
|
ldumaxalb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1039;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00011xxxxxx11100011110
|
|
|
|
ldumaxalh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1042;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00011xxxxxx111000111x1
|
|
|
|
ldumaxal. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1045;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 22) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00100xxxxxx10000011100
|
|
|
|
ldclrb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 974;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00100xxxxxx10000011110
|
|
|
|
ldclrh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 975;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00100xxxxxx100000111x1
|
|
|
|
ldclr. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 976;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00100xxxxxx10100011100
|
|
|
|
ldclrab. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 977;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00100xxxxxx10100011110
|
|
|
|
ldclrah. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 980;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00100xxxxxx101000111x1
|
|
|
|
ldclra. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 983;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00100xxxxxx11000011100
|
|
|
|
ldclrlb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 978;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00100xxxxxx11000011110
|
|
|
|
ldclrlh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 981;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00100xxxxxx110000111x1
|
|
|
|
ldclrl. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 984;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00100xxxxxx11100011100
|
|
|
|
ldclralb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 979;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00100xxxxxx11100011110
|
|
|
|
ldclralh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 982;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00100xxxxxx111000111x1
|
|
|
|
ldclral. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 985;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 22) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00101xxxxxx10000011100
|
|
|
|
ldsminb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1022;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00101xxxxxx10000011110
|
|
|
|
ldsminh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1023;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00101xxxxxx100000111x1
|
|
|
|
ldsmin. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1024;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00101xxxxxx10100011100
|
|
|
|
ldsminab. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1025;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00101xxxxxx10100011110
|
|
|
|
ldsminah. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1028;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00101xxxxxx101000111x1
|
|
|
|
ldsmina. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1031;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00101xxxxxx11000011100
|
|
|
|
ldsminlb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1026;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00101xxxxxx11000011110
|
|
|
|
ldsminlh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1029;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00101xxxxxx110000111x1
|
|
|
|
ldsminl. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1032;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00101xxxxxx11100011100
|
|
|
|
ldsminalb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1027;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00101xxxxxx11100011110
|
|
|
|
ldsminalh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1030;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00101xxxxxx111000111x1
|
|
|
|
ldsminal. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1033;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 22) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00110xxxxxx10000011100
|
|
|
|
ldsetb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 998;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00110xxxxxx10000011110
|
|
|
|
ldseth. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 999;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00110xxxxxx100000111x1
|
|
|
|
ldset. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1000;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00110xxxxxx10100011100
|
|
|
|
ldsetab. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1001;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00110xxxxxx10100011110
|
|
|
|
ldsetah. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1004;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00110xxxxxx101000111x1
|
|
|
|
ldseta. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1007;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00110xxxxxx11000011100
|
|
|
|
ldsetlb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1002;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00110xxxxxx11000011110
|
|
|
|
ldsetlh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1005;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00110xxxxxx110000111x1
|
|
|
|
ldsetl. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1008;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00110xxxxxx11100011100
|
|
|
|
ldsetalb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1003;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00110xxxxxx11100011110
|
|
|
|
ldsetalh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1006;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00110xxxxxx111000111x1
|
|
|
|
ldsetal. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1009;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2014-09-03 15:40:41 +02:00
|
|
|
if (((word >> 22) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00111xxxxxx10000011100
|
|
|
|
lduminb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1046;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00111xxxxxx10000011110
|
|
|
|
lduminh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1047;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00111xxxxxx100000111x1
|
|
|
|
ldumin. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1048;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00111xxxxxx10100011100
|
|
|
|
lduminab. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1049;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00111xxxxxx10100011110
|
|
|
|
lduminah. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1052;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00111xxxxxx101000111x1
|
|
|
|
ldumina. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1055;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00111xxxxxx11000011100
|
|
|
|
lduminlb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1050;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00111xxxxxx11000011110
|
|
|
|
lduminlh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1053;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00111xxxxxx110000111x1
|
|
|
|
lduminl. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1056;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00111xxxxxx11100011100
|
|
|
|
lduminalb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1051;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00111xxxxxx11100011110
|
|
|
|
lduminalh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1054;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00111xxxxxx111000111x1
|
|
|
|
lduminal. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1057;
|
2014-09-03 15:40:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 21) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 22) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx01xxxxxxxxx00000011100
|
|
|
|
sttrb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 848;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx01xxxxxxxxx00000011110
|
|
|
|
sttrh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 851;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx01xxxxxxxxx000000111x1
|
|
|
|
sttr. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 854;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx01xxxxxxxxx01000011100
|
|
|
|
ldtrb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 849;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx01xxxxxxxxx01000011110
|
|
|
|
ldtrh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 852;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx01xxxxxxxxx010000111x1
|
|
|
|
ldtr. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 855;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx01xxxxxxxxx0x100011100
|
|
|
|
ldtrsb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 850;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx01xxxxxxxxx0x100011101
|
|
|
|
ldtrsw. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 856;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx01xxxxxxxxx0x10001111x
|
|
|
|
ldtrsh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 853;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 22) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx01xxxxxxxxx10000011100
|
|
|
|
strb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 836;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx01xxxxxxxxx10000011110
|
|
|
|
strh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 841;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx01xxxxxxxxx100000111x1
|
|
|
|
str. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 844;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx01xxxxxxxxx11000011100
|
|
|
|
ldrb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 837;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx01xxxxxxxxx11000011110
|
|
|
|
ldrh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 842;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx01xxxxxxxxx110000111x1
|
|
|
|
ldr. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 845;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx01xxxxxxxxx1x100011100
|
|
|
|
ldrsb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 838;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx01xxxxxxxxx1x100011101
|
|
|
|
ldrsw. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 846;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx01xxxxxxxxx1x100011110
|
|
|
|
ldrsh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 843;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx01xxxxxxxxx1x100011111
|
|
|
|
prfm. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 847;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 22) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1xxxxxxxxxxx0000011100
|
|
|
|
strb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 813;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1xxxxxxxxxxx0000011110
|
|
|
|
strh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 818;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1xxxxxxxxxxx00000111x1
|
|
|
|
str. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 821;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1xxxxxxxxxxx1000011100
|
|
|
|
ldrb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 814;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1xxxxxxxxxxx1000011110
|
|
|
|
ldrh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 819;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1xxxxxxxxxxx10000111x1
|
|
|
|
ldr. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 822;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1xxxxxxxxxxxx100011100
|
|
|
|
ldrsb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 815;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1xxxxxxxxxxxx100011101
|
|
|
|
ldrsw. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 823;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1xxxxxxxxxxxx10001111x
|
|
|
|
ldrsh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 820;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 22) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxx0010011x00
|
|
|
|
strb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 824;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxx0010011x10
|
|
|
|
strh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 829;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxx0010011xx1
|
|
|
|
str. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 832;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxx1010011x00
|
|
|
|
ldrb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 825;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxx1010011x10
|
|
|
|
ldrh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 830;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxx1010011xx1
|
|
|
|
ldr. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 833;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxxx110011x00
|
|
|
|
ldrsb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 826;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxxx110011x01
|
|
|
|
ldrsw. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 834;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxxx110011x10
|
|
|
|
ldrsh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 831;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxxx110011x11
|
|
|
|
prfm. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 835;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 24) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 27) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxxx00100x00x
|
|
|
|
and. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 915;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxxx00100x01x
|
|
|
|
eor. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 919;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxxx00100x10x
|
|
|
|
orr. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 917;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxxx00100x11x
|
|
|
|
ands. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 920;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxxx10100x00x
|
|
|
|
movn. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1106;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxxx10100x01x
|
|
|
|
movz. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1108;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxxx10100x1xx
|
|
|
|
movk. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1110;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 21) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 28) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxx0xx0101000x
|
|
|
|
and. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 922;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxx0xx0101001x
|
|
|
|
eor. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 929;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxx0xx0101010x
|
|
|
|
orr. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 924;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxx0xx0101011x
|
|
|
|
ands. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 931;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 10) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 11) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 22) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00xxxxxxxxx0000101100x
|
|
|
|
adc. */
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00xxxxxxxxx0000101101x
|
|
|
|
sbc. */
|
|
|
|
return 2;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00xxxxxxxxx0000101110x
|
|
|
|
adcs. */
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00xxxxxxxxx0000101111x
|
|
|
|
sbcs. */
|
|
|
|
return 4;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00xxxxxxxxx00101011x0x
|
|
|
|
csel. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 637;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00xxxxxxxxx00101011x1x
|
|
|
|
csinv. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 641;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00xxxxxxxxx01001011x0x
|
|
|
|
ccmn. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 635;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00xxxxxxxxx01001011x1x
|
|
|
|
ccmp. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 636;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 12) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
2013-02-28 20:18:40 +01:00
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00000xxxxxx01101011xxx
|
|
|
|
rbit. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 660;
|
2013-02-28 20:18:40 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00001xxxxxx01101011xxx
|
|
|
|
crc32b. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 678;
|
2013-02-28 20:18:40 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0001xxxxxxx01101011xxx
|
|
|
|
lslv. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 670;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2013-02-28 20:18:40 +01:00
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx001x0xxxxxx01101011xxx
|
|
|
|
clz. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 665;
|
2013-02-28 20:18:40 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx001x1xxxxxx01101011xxx
|
|
|
|
crc32cb. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 682;
|
2013-02-28 20:18:40 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx01xxxxxxxxx0x001011x0x
|
|
|
|
ccmn. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 633;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx01xxxxxxxxx0x001011x1x
|
|
|
|
ccmp. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 634;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2013-02-28 20:18:40 +01:00
|
|
|
if (((word >> 12) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
2013-02-28 20:18:40 +01:00
|
|
|
if (((word >> 13) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
2013-02-28 20:18:40 +01:00
|
|
|
if (((word >> 14) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
2013-02-28 20:18:40 +01:00
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx01000xxxxxx0x101011x0x
|
|
|
|
udiv. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 668;
|
2013-02-28 20:18:40 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx01000xxxxxx0x101011x10
|
|
|
|
rev. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 662;
|
2013-02-28 20:18:40 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx01000xxxxxx0x101011x11
|
|
|
|
rev32. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 667;
|
2013-02-28 20:18:40 +01:00
|
|
|
}
|
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
2013-02-28 20:18:40 +01:00
|
|
|
xxxxxxxxxx01001xxxxxx0x101011xxx
|
|
|
|
crc32w. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 680;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
2013-02-28 20:18:40 +01:00
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0101xxxxxxx0x101011xxx
|
|
|
|
asrv. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 674;
|
2013-02-28 20:18:40 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
2013-02-28 20:18:40 +01:00
|
|
|
xxxxxxxxxx011xxxxxxxx0x101011xxx
|
|
|
|
crc32cw. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 684;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 11) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 22) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx10xxxxxxxxx00x01011x0x
|
|
|
|
csinc. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 638;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx10xxxxxxxxx00x01011x1x
|
|
|
|
csneg. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 644;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 12) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
2013-02-28 20:18:40 +01:00
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx10000xxxxxx01x01011xxx
|
|
|
|
rev16. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 661;
|
2013-02-28 20:18:40 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx10001xxxxxx01x01011xxx
|
|
|
|
crc32h. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 679;
|
2013-02-28 20:18:40 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1001xxxxxxx01x01011xxx
|
|
|
|
lsrv. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 672;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2013-02-28 20:18:40 +01:00
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx101x0xxxxxx01x01011xxx
|
|
|
|
cls. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 666;
|
2013-02-28 20:18:40 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx101x1xxxxxx01x01011xxx
|
|
|
|
crc32ch. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 683;
|
2013-02-28 20:18:40 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2013-02-28 20:18:40 +01:00
|
|
|
if (((word >> 12) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
2013-02-28 20:18:40 +01:00
|
|
|
if (((word >> 13) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
2013-02-28 20:18:40 +01:00
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx11000xxxxxx0xx01011x0x
|
|
|
|
sdiv. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 669;
|
2013-02-28 20:18:40 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx11000xxxxxx0xx01011x1x
|
|
|
|
rev. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 663;
|
2013-02-28 20:18:40 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx11001xxxxxx0xx01011xxx
|
|
|
|
crc32x. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 681;
|
2013-02-28 20:18:40 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
2013-02-28 20:18:40 +01:00
|
|
|
xxxxxxxxxx1101xxxxxxx0xx01011xxx
|
|
|
|
rorv. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 676;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
2013-02-28 20:18:40 +01:00
|
|
|
xxxxxxxxxx111xxxxxxxx0xx01011xxx
|
|
|
|
crc32cx. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 685;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxx1xx0101x00x
|
|
|
|
bic. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 923;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxx1xx0101x01x
|
|
|
|
eon. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 930;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxx1xx0101x10x
|
|
|
|
orn. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 927;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxx1xx0101x11x
|
|
|
|
bics. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 933;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 27) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxxx01100x00x
|
|
|
|
sbfm. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 605;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxxx01100x01x
|
|
|
|
ubfm. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 616;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxxx01100x1xx
|
|
|
|
bfm. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 612;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxxx11100xxxx
|
|
|
|
extr. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 708;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 21) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 28) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxx0xx1101000x
|
|
|
|
add. */
|
|
|
|
return 19;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxx0xx1101001x
|
|
|
|
sub. */
|
|
|
|
return 22;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxx0xx1101010x
|
|
|
|
adds. */
|
|
|
|
return 20;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxx0xx1101011x
|
|
|
|
subs. */
|
|
|
|
return 24;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 22) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxx0xxxxx00x11011xxx
|
|
|
|
madd. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 686;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxx0xxxxx01011011xxx
|
|
|
|
smulh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 694;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxx0xxxxx01111011xxx
|
|
|
|
umulh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 699;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxx1xxxxx0xx11011xxx
|
|
|
|
msub. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 688;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 28) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxx1x01101000x
|
|
|
|
add. */
|
|
|
|
return 6;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxx1x01101001x
|
|
|
|
sub. */
|
|
|
|
return 9;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxx1x01101010x
|
|
|
|
adds. */
|
|
|
|
return 7;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxx1x01101011x
|
|
|
|
subs. */
|
|
|
|
return 10;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxx0xxxxx1x011011xxx
|
|
|
|
smaddl. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 690;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxx1xxxxx1x011011xxx
|
|
|
|
smsubl. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 692;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxx0xxxxx1x11101xxxx
|
|
|
|
umaddl. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 695;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxx1xxxxx1x11101xxxx
|
|
|
|
umsubl. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 697;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 27) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxxxxxx10x000
|
|
|
|
b. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 623;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxxxxxx10x001
|
|
|
|
bl. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 624;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 24) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 25) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 31) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxxxx0010x010
|
|
|
|
b.c. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 632;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 0) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 1) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 21) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
00xxxxxxxxxxxxxxxxxxx0xx0010x011
|
|
|
|
hlt. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 704;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
00xxxxxxxxxxxxxxxxxxx1xx0010x011
|
|
|
|
brk. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 703;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 21) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
01xxxxxxxxxxxxxxxxxxx0xx0010x011
|
|
|
|
hvc. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 701;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
01xxxxxxxxxxxxxxxxxxx1xx0010x011
|
|
|
|
dcps2. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 706;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 1) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 21) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
10xxxxxxxxxxxxxxxxxxx0xx0010x011
|
|
|
|
svc. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 700;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
10xxxxxxxxxxxxxxxxxxx1xx0010x011
|
|
|
|
dcps1. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 705;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 21) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
11xxxxxxxxxxxxxxxxxxx0xx0010x011
|
|
|
|
smc. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 702;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
11xxxxxxxxxxxxxxxxxxx1xx0010x011
|
|
|
|
dcps3. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 707;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 21) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 22) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxx0000110x01x
|
|
|
|
br. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 625;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxx0010110x01x
|
|
|
|
eret. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 628;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxx01x0110x01x
|
|
|
|
ret. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 627;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxx1x00110x01x
|
|
|
|
blr. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 626;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxx1x10110x01x
|
|
|
|
drps. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 629;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2014-09-03 15:45:26 +02:00
|
|
|
if (((word >> 21) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
2014-09-03 15:45:26 +02:00
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxx0xx1x10x01x
|
|
|
|
msr. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1113;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2014-09-03 15:45:26 +02:00
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxx1xx1x10x01x
|
|
|
|
sysl. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1133;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 24) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 25) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxxxx0010x1xx
|
|
|
|
cbz. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 630;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxxxx0110x1xx
|
|
|
|
tbz. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1135;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 25) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxxxx1010x1xx
|
|
|
|
cbnz. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 631;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxxxx1110x1xx
|
|
|
|
tbnz. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 1136;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 25) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 28) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 22) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 24) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxx00001100xx
|
|
|
|
st4. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 431;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxx00001101xx
|
|
|
|
stnp. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 899;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 21) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxx0xxxxxxx000101100xx
|
|
|
|
st1. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 447;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxx0xxxxxxx100101100xx
|
|
|
|
st2. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 449;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 21) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxx1xxxxxxx000101100xx
|
|
|
|
st3. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 448;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxx1xxxxxxx100101100xx
|
|
|
|
st4. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 450;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxx00101101xx
|
|
|
|
stp. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 903;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 21) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 24) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxx001001100xx
|
|
|
|
st4. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 439;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxx0xxxxxxx001101100xx
|
|
|
|
st1. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 459;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxx1xxxxxxx001101100xx
|
|
|
|
st3. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 460;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxx0xxxxxxx101x01100xx
|
|
|
|
st2. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 461;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxx1xxxxxxx101x01100xx
|
|
|
|
st4. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 462;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxx01x01101xx
|
|
|
|
stp. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 908;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 24) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxx10001100xx
|
|
|
|
ld4. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 435;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxx10001101xx
|
|
|
|
ldnp. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 900;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 21) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxx0xxxxxxx010101100xx
|
|
|
|
ld1. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 451;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxx0xxxxxxx110101100xx
|
|
|
|
ld2. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 455;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 21) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxx1xxxxxxx010101100xx
|
|
|
|
ld3. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 452;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxx1xxxxxxx110101100xx
|
|
|
|
ld4. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 456;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxx10101101xx
|
|
|
|
ldp. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 904;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 21) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 24) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxx011001100xx
|
|
|
|
ld4. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 443;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxx0xxxxxxx011101100xx
|
|
|
|
ld1. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 463;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxx1xxxxxxx011101100xx
|
|
|
|
ld3. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 464;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxx0xxxxxxx111x01100xx
|
|
|
|
ld2. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 467;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxx1xxxxxxx111x01100xx
|
|
|
|
ld4. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 468;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxx11x01101xx
|
|
|
|
ldp. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 909;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 24) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxxxx001110xx
|
|
|
|
ldr. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 912;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 10) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 11) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 22) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00xxxxxxxxxx0x001111xx
|
|
|
|
stur. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 860;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00xxxxxxxxxx1x001111xx
|
|
|
|
ldur. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 861;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 22) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx01xxxxxxxxxx0x001111xx
|
|
|
|
str. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 839;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx01xxxxxxxxxx1x001111xx
|
|
|
|
ldr. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 840;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 22) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1xxxxxxxxxxx0x001111xx
|
|
|
|
str. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 816;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1xxxxxxxxxxx1x001111xx
|
|
|
|
ldr. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 817;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 22) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxx0x10111xxx
|
|
|
|
str. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 827;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxxxxxxxx1x10111xxx
|
|
|
|
ldr. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 828;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 24) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 21) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 28) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 10) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 11) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 12) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000xxxxxxxx0xx011100xx
|
|
|
|
tbl. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 411;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx001xxxxxxxx0xx011100xx
|
|
|
|
tbx. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 412;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 12) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx010x0xxxxxx0xx011100xx
|
|
|
|
trn1. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 256;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx010x1xxxxxx0xx011100xx
|
|
|
|
trn2. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 259;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx01100xxxxxx0xx011100xx
|
|
|
|
uzp1. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 255;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx01101xxxxxx0xx011100xx
|
|
|
|
uzp2. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 258;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx01110xxxxxx0xx011100xx
|
|
|
|
zip1. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 257;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx01111xxxxxx0xx011100xx
|
|
|
|
zip2. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 260;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0xxxxxxxxxx0xx011101xx
|
|
|
|
ext. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 129;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2015-06-02 13:20:00 +02:00
|
|
|
if (((word >> 15) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14 17:44:02 +01:00
|
|
|
if (((word >> 22) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14 17:44:02 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 11) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx10xxx0xxxxx00x011100xx
|
|
|
|
dup. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 146;
|
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14 17:44:02 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 12) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1100x0xxxxx00x011100xx
|
|
|
|
dup. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 147;
|
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14 17:44:02 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1101x0xxxxx00x011100xx
|
|
|
|
smov. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 148;
|
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14 17:44:02 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1110x0xxxxx00x011100xx
|
|
|
|
ins. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 151;
|
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14 17:44:02 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1111x0xxxxx00x011100xx
|
|
|
|
umov. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 149;
|
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14 17:44:02 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
2015-06-02 13:20:00 +02:00
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14 17:44:02 +01:00
|
|
|
xxxxxxxxxx1xxxx0xxxxx00x011101xx
|
|
|
|
ins. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 153;
|
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14 17:44:02 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 11) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 12) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1000x0xxxxx010011100xx
|
|
|
|
fmaxnm. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 285;
|
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14 17:44:02 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1000x0xxxxx010011101xx
|
|
|
|
fmaxnmp. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 336;
|
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14 17:44:02 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1000x0xxxxx011011100xx
|
|
|
|
fminnm. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 301;
|
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14 17:44:02 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1000x0xxxxx011011101xx
|
|
|
|
fminnmp. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 352;
|
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14 17:44:02 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1001x0xxxxx010011100xx
|
|
|
|
fcmeq. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 293;
|
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14 17:44:02 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1001x0xxxxx010011101xx
|
|
|
|
fcmge. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 342;
|
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14 17:44:02 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1001x0xxxxx01101110xxx
|
|
|
|
fcmgt. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 356;
|
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14 17:44:02 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1010x0xxxxx010011100xx
|
|
|
|
fadd. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 289;
|
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14 17:44:02 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1010x0xxxxx010011101xx
|
|
|
|
faddp. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 338;
|
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14 17:44:02 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1010x0xxxxx011011100xx
|
|
|
|
fsub. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 305;
|
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14 17:44:02 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1010x0xxxxx011011101xx
|
|
|
|
fabd. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 354;
|
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14 17:44:02 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1011x0xxxxx010011100xx
|
|
|
|
fmax. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 295;
|
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14 17:44:02 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1011x0xxxxx010011101xx
|
|
|
|
fmaxp. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 346;
|
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14 17:44:02 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1011x0xxxxx011011100xx
|
|
|
|
fmin. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 307;
|
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14 17:44:02 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1011x0xxxxx011011101xx
|
|
|
|
fminp. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 360;
|
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14 17:44:02 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2015-06-02 13:20:00 +02:00
|
|
|
if (((word >> 12) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
2015-06-02 13:20:00 +02:00
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14 17:44:02 +01:00
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1100x0xxxxx01001110xxx
|
|
|
|
fmla. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 287;
|
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14 17:44:02 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1100x0xxxxx01101110xxx
|
|
|
|
fmls. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 303;
|
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14 17:44:02 +01:00
|
|
|
}
|
2015-06-02 13:20:00 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14 17:44:02 +01:00
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1101x0xxxxx01001110xxx
|
|
|
|
facge. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 344;
|
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14 17:44:02 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1101x0xxxxx01101110xxx
|
|
|
|
facgt. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 358;
|
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14 17:44:02 +01:00
|
|
|
}
|
2015-06-02 13:20:00 +02:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2015-06-02 13:20:00 +02:00
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14 17:44:02 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1110x0xxxxx01x011100xx
|
|
|
|
fmulx. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 291;
|
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14 17:44:02 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1110x0xxxxx01x011101xx
|
|
|
|
fmul. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 340;
|
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14 17:44:02 +01:00
|
|
|
}
|
2015-06-02 13:20:00 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14 17:44:02 +01:00
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1111x0xxxxx010011100xx
|
|
|
|
frecps. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 297;
|
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14 17:44:02 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1111x0xxxxx010011101xx
|
|
|
|
fdiv. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 348;
|
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14 17:44:02 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1111x0xxxxx01101110xxx
|
|
|
|
frsqrts. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 309;
|
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14 17:44:02 +01:00
|
|
|
}
|
2015-06-02 13:20:00 +02:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2015-06-02 13:20:00 +02:00
|
|
|
if (((word >> 11) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
2015-06-02 13:20:00 +02:00
|
|
|
xxxxxxxxxx10xxx1xxxxx0xx01110xxx
|
|
|
|
sqrdmlah. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 363;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
2015-06-02 13:20:00 +02:00
|
|
|
xxxxxxxxxx11xxx1xxxxx0xx01110xxx
|
|
|
|
sqrdmlsh. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 364;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2015-06-02 13:20:00 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
2015-06-02 13:20:00 +02:00
|
|
|
if (((word >> 30) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
2015-06-02 13:20:00 +02:00
|
|
|
if (((word >> 16) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
2015-06-02 13:20:00 +02:00
|
|
|
if (((word >> 17) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
2015-06-02 13:20:00 +02:00
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxx00xxx0xx0111100x
|
|
|
|
fcvtzs. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 714;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2015-06-02 13:20:00 +02:00
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxx01xxx0xx0111100x
|
|
|
|
scvtf. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 710;
|
2015-06-02 13:20:00 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 17) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxx10xxx0xx0111100x
|
|
|
|
fcvtzu. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 716;
|
2015-06-02 13:20:00 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxxx11xxx0xx0111100x
|
|
|
|
ucvtf. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 712;
|
2015-06-02 13:20:00 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 10) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 12) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
2015-06-02 13:20:00 +02:00
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x000xxxxxx0xx0111101x
|
|
|
|
sha1c. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 653;
|
2015-06-02 13:20:00 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x001xxxxxx0xx0111101x
|
|
|
|
sha256h. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 657;
|
2015-06-02 13:20:00 +02:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2015-06-02 13:20:00 +02:00
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x010xxxxxx0xx0111101x
|
|
|
|
sha1m. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 655;
|
2015-06-02 13:20:00 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x011xxxxxx0xx0111101x
|
|
|
|
sha256su1. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 659;
|
2015-06-02 13:20:00 +02:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
2015-06-02 13:20:00 +02:00
|
|
|
else
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
2015-06-02 13:20:00 +02:00
|
|
|
if (((word >> 13) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
2015-06-02 13:20:00 +02:00
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x100xxxxxx0xx0111101x
|
|
|
|
sha1p. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 654;
|
2015-06-02 13:20:00 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x101xxxxxx0xx0111101x
|
|
|
|
sha256h2. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 658;
|
2015-06-02 13:20:00 +02:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
2015-06-02 13:20:00 +02:00
|
|
|
xxxxxxxxxx0x11xxxxxxx0xx0111101x
|
|
|
|
sha1su0. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 656;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
2015-06-02 13:20:00 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FABD, FMULX, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FRECPS and FRSQRTS.
The general form for these instructions is
<OP> <Hd>, <Hs>, <Hm>
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar three register same
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and
facgt to the scalar three same group.
Change-Id: I155eb8d7c1e9a7c89d691d7e4aae83be51ff1238
2015-12-14 17:49:34 +01:00
|
|
|
if (((word >> 11) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx10x0xxxxxxx0xx0111101x
|
|
|
|
dup. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 526;
|
[AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FABD, FMULX, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FRECPS and FRSQRTS.
The general form for these instructions is
<OP> <Hd>, <Hs>, <Hm>
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar three register same
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and
facgt to the scalar three same group.
Change-Id: I155eb8d7c1e9a7c89d691d7e4aae83be51ff1238
2015-12-14 17:49:34 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx10x1xxxxxxx0xx0111101x
|
|
|
|
fcmeq. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 547;
|
[AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FABD, FMULX, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FRECPS and FRSQRTS.
The general form for these instructions is
<OP> <Hd>, <Hs>, <Hm>
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar three register same
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and
facgt to the scalar three same group.
Change-Id: I155eb8d7c1e9a7c89d691d7e4aae83be51ff1238
2015-12-14 17:49:34 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx11x0xxxxxxx0xx0111101x
|
|
|
|
fmulx. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 545;
|
[AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FABD, FMULX, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FRECPS and FRSQRTS.
The general form for these instructions is
<OP> <Hd>, <Hs>, <Hm>
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar three register same
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and
facgt to the scalar three same group.
Change-Id: I155eb8d7c1e9a7c89d691d7e4aae83be51ff1238
2015-12-14 17:49:34 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx11x1xxxxxxx0x00111101x
|
|
|
|
frecps. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 549;
|
[AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FABD, FMULX, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FRECPS and FRSQRTS.
The general form for these instructions is
<OP> <Hd>, <Hs>, <Hm>
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar three register same
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and
facgt to the scalar three same group.
Change-Id: I155eb8d7c1e9a7c89d691d7e4aae83be51ff1238
2015-12-14 17:49:34 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx11x1xxxxxxx0x10111101x
|
|
|
|
frsqrts. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 551;
|
[AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FABD, FMULX, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FRECPS and FRSQRTS.
The general form for these instructions is
<OP> <Hd>, <Hs>, <Hm>
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar three register same
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and
facgt to the scalar three same group.
Change-Id: I155eb8d7c1e9a7c89d691d7e4aae83be51ff1238
2015-12-14 17:49:34 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
2015-06-02 13:20:00 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 11) & 0x1) == 0)
|
|
|
|
{
|
[AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FABD, FMULX, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FRECPS and FRSQRTS.
The general form for these instructions is
<OP> <Hd>, <Hs>, <Hm>
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar three register same
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and
facgt to the scalar three same group.
Change-Id: I155eb8d7c1e9a7c89d691d7e4aae83be51ff1238
2015-12-14 17:49:34 +01:00
|
|
|
if (((word >> 12) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxx000xxxxxxx0xx011111xx
|
|
|
|
sqrdmlah. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 579;
|
[AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FABD, FMULX, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FRECPS and FRSQRTS.
The general form for these instructions is
<OP> <Hd>, <Hs>, <Hm>
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar three register same
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and
facgt to the scalar three same group.
Change-Id: I155eb8d7c1e9a7c89d691d7e4aae83be51ff1238
2015-12-14 17:49:34 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxx001xxxxxxx0x0011111xx
|
|
|
|
fcmge. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 564;
|
[AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FABD, FMULX, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FRECPS and FRSQRTS.
The general form for these instructions is
<OP> <Hd>, <Hs>, <Hm>
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar three register same
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and
facgt to the scalar three same group.
Change-Id: I155eb8d7c1e9a7c89d691d7e4aae83be51ff1238
2015-12-14 17:49:34 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxx001xxxxxxx0x1011111xx
|
|
|
|
fcmgt. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 570;
|
[AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FABD, FMULX, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FRECPS and FRSQRTS.
The general form for these instructions is
<OP> <Hd>, <Hs>, <Hm>
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar three register same
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and
facgt to the scalar three same group.
Change-Id: I155eb8d7c1e9a7c89d691d7e4aae83be51ff1238
2015-12-14 17:49:34 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxx01xxxxxxxx0xx011111xx
|
|
|
|
fabd. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 568;
|
[AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FABD, FMULX, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FRECPS and FRSQRTS.
The general form for these instructions is
<OP> <Hd>, <Hs>, <Hm>
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar three register same
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and
facgt to the scalar three same group.
Change-Id: I155eb8d7c1e9a7c89d691d7e4aae83be51ff1238
2015-12-14 17:49:34 +01:00
|
|
|
}
|
2015-06-02 13:20:00 +02:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FABD, FMULX, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FRECPS and FRSQRTS.
The general form for these instructions is
<OP> <Hd>, <Hs>, <Hm>
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar three register same
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and
facgt to the scalar three same group.
Change-Id: I155eb8d7c1e9a7c89d691d7e4aae83be51ff1238
2015-12-14 17:49:34 +01:00
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxx1x0xxxxxxx0xx011111xx
|
|
|
|
sqrdmlsh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 580;
|
[AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FABD, FMULX, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FRECPS and FRSQRTS.
The general form for these instructions is
<OP> <Hd>, <Hs>, <Hm>
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar three register same
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and
facgt to the scalar three same group.
Change-Id: I155eb8d7c1e9a7c89d691d7e4aae83be51ff1238
2015-12-14 17:49:34 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxx1x1xxxxxxx0x0011111xx
|
|
|
|
facge. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 566;
|
[AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FABD, FMULX, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FRECPS and FRSQRTS.
The general form for these instructions is
<OP> <Hd>, <Hs>, <Hm>
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar three register same
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and
facgt to the scalar three same group.
Change-Id: I155eb8d7c1e9a7c89d691d7e4aae83be51ff1238
2015-12-14 17:49:34 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxx1x1xxxxxxx0x1011111xx
|
|
|
|
facgt. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 572;
|
[AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FABD, FMULX, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FRECPS and FRSQRTS.
The general form for these instructions is
<OP> <Hd>, <Hs>, <Hm>
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar three register same
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and
facgt to the scalar three same group.
Change-Id: I155eb8d7c1e9a7c89d691d7e4aae83be51ff1238
2015-12-14 17:49:34 +01:00
|
|
|
}
|
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 10) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 11) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 12) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 28) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000000xxxxx1xx0111000x
|
|
|
|
saddl. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 42;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000000xxxxx1xx0111001x
|
|
|
|
saddl2. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 43;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000000xxxxx1xx0111010x
|
|
|
|
uaddl. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 74;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000000xxxxx1xx0111011x
|
|
|
|
uaddl2. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 75;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 16) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 17) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 18) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 19) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 20) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000000000001xx01111xxx
|
|
|
|
fcvtns. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 718;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000000000011xx01111xxx
|
|
|
|
fcvtms. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 738;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 20) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000000000101xx01111xxx
|
|
|
|
fcvtps. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 734;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000000000111xx01111xxx
|
|
|
|
fcvtzs. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 742;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000000001xx1xx01111xxx
|
|
|
|
fcvtas. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 726;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 18) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000000010xx1xx01111xxx
|
|
|
|
scvtf. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 722;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 19) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0000000110x1xx01111xxx
|
|
|
|
fmov. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 730;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0000000111x1xx01111xxx
|
|
|
|
fmov. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 746;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 17) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 18) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 19) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 20) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000000100001xx01111xxx
|
|
|
|
fcvtnu. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 720;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000000100011xx01111xxx
|
|
|
|
fcvtmu. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 740;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 20) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000000100101xx01111xxx
|
|
|
|
fcvtpu. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 736;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000000100111xx01111xxx
|
|
|
|
fcvtzu. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 744;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000000101xx1xx01111xxx
|
|
|
|
fcvtau. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 728;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 18) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000000110xx1xx01111xxx
|
|
|
|
ucvtf. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 724;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 19) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0000001110x1xx01111xxx
|
|
|
|
fmov. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 732;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0000001111x1xx01111xxx
|
|
|
|
fmov. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 747;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000001xxxxx1xx0111x00x
|
|
|
|
smlal. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 58;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000001xxxxx1xx0111x01x
|
|
|
|
smlal2. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 59;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000001xxxxx1xx0111x10x
|
|
|
|
umlal. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 90;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000001xxxxx1xx0111x11x
|
|
|
|
umlal2. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 91;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 28) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000010xxxxx1xx0111000x
|
|
|
|
addhn. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 50;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000010xxxxx1xx0111001x
|
|
|
|
addhn2. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 51;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000010xxxxx1xx0111010x
|
|
|
|
raddhn. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 82;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000010xxxxx1xx0111011x
|
|
|
|
raddhn2. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 83;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000011xxxxx1xx0111000x
|
|
|
|
smull. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 66;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000011xxxxx1xx0111001x
|
|
|
|
smull2. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 67;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000011xxxxx1xx0111010x
|
|
|
|
umull. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 94;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000011xxxxx1xx0111011x
|
|
|
|
umull2. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 95;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 17) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 16) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 18) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000010000xx1xx01111xxx
|
|
|
|
fmov. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 760;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000010001xx1xx01111xxx
|
|
|
|
frintn. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 769;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 18) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000010100xx1xx01111xxx
|
|
|
|
fneg. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 764;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000010101xx1xx01111xxx
|
|
|
|
frintm. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 773;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 16) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 18) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000011000xx1xx01111xxx
|
|
|
|
fabs. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 762;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000011001xx1xx01111xxx
|
|
|
|
frintp. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 771;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 18) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000011100xx1xx01111xxx
|
|
|
|
fsqrt. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 766;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000011101xx1xx01111xxx
|
|
|
|
frintz. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 775;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 18) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00001xx10xx1xx01111xxx
|
|
|
|
fcvt. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 768;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 16) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000010011xx1xx01111xxx
|
|
|
|
frinta. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 777;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000010111xx1xx01111xxx
|
|
|
|
frintx. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 779;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000011x11xx1xx01111xxx
|
|
|
|
frinti. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 781;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 28) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000100xxxxx1xx0111000x
|
|
|
|
ssubl. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 46;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000100xxxxx1xx0111001x
|
|
|
|
ssubl2. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 47;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000100xxxxx1xx0111010x
|
|
|
|
usubl. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 78;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000100xxxxx1xx0111011x
|
|
|
|
usubl2. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 79;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 3) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 4) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxx00xxxxx000100xxxxx1xx01111xxx
|
|
|
|
fcmp. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 752;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxx01xxxxx000100xxxxx1xx01111xxx
|
|
|
|
fcmpe. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 754;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 4) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxx10xxxxx000100xxxxx1xx01111xxx
|
|
|
|
fcmp. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 756;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxx11xxxxx000100xxxxx1xx01111xxx
|
|
|
|
fcmpe. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 758;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000101xxxxx1xx0111x00x
|
|
|
|
smlsl. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 62;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000101xxxxx1xx0111x01x
|
|
|
|
smlsl2. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 63;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000101xxxxx1xx0111x10x
|
|
|
|
umlsl. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 92;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000101xxxxx1xx0111x11x
|
|
|
|
umlsl2. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 93;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000110xxxxx1xx0111x00x
|
|
|
|
subhn. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 54;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000110xxxxx1xx0111x01x
|
|
|
|
subhn2. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 55;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000110xxxxx1xx0111x10x
|
|
|
|
rsubhn. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 86;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000110xxxxx1xx0111x11x
|
|
|
|
rsubhn2. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 87;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 22) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000111xxxxx10x0111xx0x
|
|
|
|
pmull. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 70;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000111xxxxx10x0111xx1x
|
|
|
|
pmull2. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 72;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000111xxxxx11x0111xx0x
|
|
|
|
pmull. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 71;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx000111xxxxx11x0111xx1x
|
|
|
|
pmull2. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 73;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 28) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx001000xxxxx1xx0111000x
|
|
|
|
saddw. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 44;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx001000xxxxx1xx0111001x
|
|
|
|
saddw2. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 45;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx001000xxxxx1xx0111010x
|
|
|
|
uaddw. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 76;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx001000xxxxx1xx0111011x
|
|
|
|
uaddw2. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 77;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx001001xxxxx1xx01110x0x
|
|
|
|
sqdmlal. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 60;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx001001xxxxx1xx01110x1x
|
|
|
|
sqdmlal2. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 61;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx001010xxxxx1xx0111000x
|
|
|
|
sabal. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 52;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx001010xxxxx1xx0111001x
|
|
|
|
sabal2. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 53;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx001010xxxxx1xx0111010x
|
|
|
|
uabal. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 84;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx001010xxxxx1xx0111011x
|
|
|
|
uabal2. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 85;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx001011xxxxx1xx01110x0x
|
|
|
|
sqdmull. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 68;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx001011xxxxx1xx01110x1x
|
|
|
|
sqdmull2. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 69;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx001100xxxxx1xx0111000x
|
|
|
|
ssubw. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 48;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx001100xxxxx1xx0111001x
|
|
|
|
ssubw2. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 49;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx001100xxxxx1xx0111010x
|
|
|
|
usubw. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 80;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx001100xxxxx1xx0111011x
|
|
|
|
usubw2. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 81;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx001101xxxxx1xx01110x0x
|
|
|
|
sqdmlsl. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 64;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx001101xxxxx1xx01110x1x
|
|
|
|
sqdmlsl2. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 65;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00111xxxxxx1xx0111000x
|
|
|
|
sabdl. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 56;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00111xxxxxx1xx0111001x
|
|
|
|
sabdl2. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 57;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00111xxxxxx1xx0111010x
|
|
|
|
uabdl. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 88;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00111xxxxxx1xx0111011x
|
|
|
|
uabdl2. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 89;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx001xxxxxxxx1xx01111x0x
|
|
|
|
fmov. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 809;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00100xxxxxx1xx01111x1x
|
|
|
|
sqdmlal. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 413;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx00101xxxxxx1xx01111x1x
|
|
|
|
sqdmull. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 415;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0011xxxxxxx1xx01111x1x
|
|
|
|
sqdmlsl. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 414;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 12) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 28) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx010000xxxxx1xx011100xx
|
|
|
|
rev64. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 155;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx010000xxxxx1xx011101xx
|
|
|
|
rev32. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 206;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx010000xxxxx1xx01111x0x
|
|
|
|
fmul. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 783;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx010000xxxxx1xx01111x1x
|
|
|
|
sha1h. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 650;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 28) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 16) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0100010xxxx1xx011100xx
|
|
|
|
cmgt. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 163;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0100010xxxx1xx011101xx
|
|
|
|
cmge. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 212;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 19) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 23) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0100011xx0x1x0011100xx
|
|
|
|
frintn. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 175;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0100011xx0x1x0011101xx
|
|
|
|
frinta. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 223;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
xxxxxxxxxx0100011xx0x1x101110xxx
|
|
|
|
frintp. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 195;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0100011xx1x1x0011100xx
|
|
|
|
frintn. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 176;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0100011xx1x1x0011101xx
|
|
|
|
frinta. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 224;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0100011xx1x1x101110xxx
|
|
|
|
frintp. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 196;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx010001xxxxx1xx0111100x
|
|
|
|
fnmul. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 799;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx010001xxxxx1xx0111101x
|
|
|
|
cmgt. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 473;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx010001xxxxx1xx011111xx
|
|
|
|
cmge. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 502;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 28) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 16) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 19) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0100100xx0x1xx011100xx
|
|
|
|
cls. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 159;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0100100xx0x1xx011101xx
|
|
|
|
clz. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 209;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0100100xx1x1xx01110xxx
|
|
|
|
aese. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 646;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0100101xxxx1xx0111000x
|
|
|
|
sqxtn. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 169;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0100101xxxx1xx0111001x
|
|
|
|
sqxtn2. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 170;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0100101xxxx1xx0111010x
|
|
|
|
uqxtn. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 219;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0100101xxxx1xx0111011x
|
|
|
|
uqxtn2. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 220;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx010010xxxxx1xx0111100x
|
|
|
|
fmax. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 791;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx010010xxxxx1xx0111101x
|
|
|
|
sqxtn. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 477;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx010010xxxxx1xx011111xx
|
|
|
|
uqxtn. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 506;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 16) & 0x1) == 0)
|
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 19) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 20) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 28) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0100110xx001xx011100xx
|
|
|
|
fcmgt. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 187;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0100110xx001xx011101xx
|
|
|
|
fcmge. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 238;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0100110xx001xx011110xx
|
|
|
|
fcmgt. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 486;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0100110xx001xx011111xx
|
|
|
|
fcmge. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 516;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 23) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 28) & 0x1) == 0)
|
|
|
|
{
|
2015-12-14 18:16:50 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0100110xx011x0011100xx
|
|
|
|
fmaxnmv. */
|
|
|
|
return 35;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0100110xx011x0011101xx
|
|
|
|
fmaxnmv. */
|
|
|
|
return 34;
|
|
|
|
}
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2015-12-14 18:35:47 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0100110xx011x0011110xx
|
|
|
|
fmaxnmp. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 530;
|
2015-12-14 18:35:47 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0100110xx011x0011111xx
|
|
|
|
fmaxnmp. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 529;
|
2015-12-14 18:35:47 +01:00
|
|
|
}
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 28) & 0x1) == 0)
|
|
|
|
{
|
2015-12-14 18:16:50 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0100110xx011x1011100xx
|
|
|
|
fminnmv. */
|
|
|
|
return 39;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0100110xx011x1011101xx
|
|
|
|
fminnmv. */
|
|
|
|
return 38;
|
|
|
|
}
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2015-12-14 18:35:47 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0100110xx011x1011110xx
|
|
|
|
fminnmp. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 536;
|
2015-12-14 18:35:47 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0100110xx011x1011111xx
|
|
|
|
fminnmp. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 535;
|
2015-12-14 18:35:47 +01:00
|
|
|
}
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
{
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
if (((word >> 28) & 0x1) == 0)
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
{
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0100110xx1x1xx011100xx
|
|
|
|
fcmgt. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 188;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0100110xx1x1xx011101xx
|
|
|
|
fcmge. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 239;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0100110xx1x1xx011110xx
|
|
|
|
fcmgt. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 487;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0100110xx1x1xx011111xx
|
|
|
|
fcmge. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 517;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 19) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 28) & 0x1) == 0)
|
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0100111xx0x1x0011100xx
|
|
|
|
fcvtas. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 183;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0100111xx0x1x0011101xx
|
|
|
|
fcvtau. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 231;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0100111xx0x1x0011110xx
|
|
|
|
fcvtas. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 482;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0100111xx0x1x0011111xx
|
|
|
|
fcvtau. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 512;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
xxxxxxxxxx0100111xx0x1x10111x0xx
|
|
|
|
urecpe. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 203;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
xxxxxxxxxx0100111xx0x1x10111x1xx
|
|
|
|
ursqrte. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 250;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
else
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
if (((word >> 28) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0100111xx1x1xx011100xx
|
|
|
|
fcvtas. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 184;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0100111xx1x1xx011101xx
|
|
|
|
fcvtau. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 232;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0100111xx1x1xx011110xx
|
|
|
|
fcvtas. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 483;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0100111xx1x1xx011111xx
|
|
|
|
fcvtau. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 513;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 28) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 16) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0101000xxxx1xx011100xx
|
|
|
|
saddlp. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 157;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0101000xxxx1xx011101xx
|
|
|
|
uaddlp. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 207;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0101001xxxx1xx0111000x
|
|
|
|
xtn. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 167;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0101001xxxx1xx0111001x
|
|
|
|
xtn2. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 168;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0101001xxxx1xx0111010x
|
|
|
|
sqxtun. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 215;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0101001xxxx1xx0111011x
|
|
|
|
sqxtun2. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 216;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx010100xxxxx1xx0111100x
|
|
|
|
fadd. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 787;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx010100xxxxx1xx0111101x
|
|
|
|
sha256su0. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 652;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx010100xxxxx1xx011111xx
|
|
|
|
sqxtun. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 505;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 16) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 20) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 28) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0101010xxx01xx01110xxx
|
|
|
|
cmlt. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 165;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0101010xxx01xx01111xxx
|
|
|
|
cmlt. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 475;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0101010xxx11xx0111x0xx
|
|
|
|
smaxv. */
|
|
|
|
return 28;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0101010xxx11xx0111x1xx
|
|
|
|
umaxv. */
|
|
|
|
return 32;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 19) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 20) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 23) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 28) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0101011xx001x0011100xx
|
|
|
|
fcvtns. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 179;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0101011xx001x0011101xx
|
|
|
|
fcvtnu. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 227;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0101011xx001x0011110xx
|
|
|
|
fcvtns. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 478;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0101011xx001x0011111xx
|
|
|
|
fcvtnu. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 508;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 28) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0101011xx001x1011100xx
|
|
|
|
fcvtps. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 199;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0101011xx001x1011101xx
|
|
|
|
fcvtpu. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 246;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0101011xx001x1011110xx
|
|
|
|
fcvtps. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 492;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0101011xx001x1011111xx
|
|
|
|
fcvtpu. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 520;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0101011xx011xx0111x0xx
|
|
|
|
sminv. */
|
|
|
|
return 29;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0101011xx011xx0111x1xx
|
|
|
|
uminv. */
|
|
|
|
return 33;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 23) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
if (((word >> 28) & 0x1) == 0)
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
{
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0101011xx1x1x0011100xx
|
|
|
|
fcvtns. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 180;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0101011xx1x1x0011101xx
|
|
|
|
fcvtnu. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 228;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0101011xx1x1x0011110xx
|
|
|
|
fcvtns. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 479;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0101011xx1x1x0011111xx
|
|
|
|
fcvtnu. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 509;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
if (((word >> 28) & 0x1) == 0)
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
{
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0101011xx1x1x1011100xx
|
|
|
|
fcvtps. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 200;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0101011xx1x1x1011101xx
|
|
|
|
fcvtpu. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 247;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0101011xx1x1x1011110xx
|
|
|
|
fcvtps. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 493;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0101011xx1x1x1011111xx
|
|
|
|
fcvtpu. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 521;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 28) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 16) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 19) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0101100xx0x1xx011100xx
|
|
|
|
sadalp. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 161;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0101100xx0x1xx011101xx
|
|
|
|
uadalp. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 210;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0101100xx1x1xx01110xxx
|
|
|
|
aesmc. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 648;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0101101xxxx1xx0111000x
|
|
|
|
fcvtn. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 171;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0101101xxxx1xx0111001x
|
|
|
|
fcvtn2. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 172;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0101101xxxx1xx0111010x
|
|
|
|
fcvtxn. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 221;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0101101xxxx1xx0111011x
|
|
|
|
fcvtxn2. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 222;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx010110xxxxx1xx011110xx
|
|
|
|
fmaxnm. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 795;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx010110xxxxx1xx011111xx
|
|
|
|
fcvtxn. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 507;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 19) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 28) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx010111xxx0x1xx01110xxx
|
|
|
|
fcmlt. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 191;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx010111xxx0x1xx01111xxx
|
|
|
|
fcmlt. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 490;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
if (((word >> 28) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx010111xxx1x1xx01110xxx
|
|
|
|
fcmlt. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 192;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx010111xxx1x1xx01111xxx
|
|
|
|
fcmlt. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 491;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 28) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx011000xxxxx1xx01110xxx
|
|
|
|
rev16. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 156;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx011000xxxxx1xx01111x0x
|
|
|
|
fdiv. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 785;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx011000xxxxx1xx01111x1x
|
|
|
|
sha1su1. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 651;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 16) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 28) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0110010xxxx1xx011100xx
|
|
|
|
cmeq. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 164;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0110010xxxx1xx011101xx
|
|
|
|
cmle. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 213;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0110010xxxx1xx011110xx
|
|
|
|
cmeq. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 474;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0110010xxxx1xx011111xx
|
|
|
|
cmle. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 503;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 19) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 23) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0110011xx0x1x00111x0xx
|
|
|
|
frintm. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 177;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0110011xx0x1x00111x1xx
|
|
|
|
frintx. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 225;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0110011xx0x1x10111x0xx
|
|
|
|
frintz. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 197;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0110011xx0x1x10111x1xx
|
|
|
|
frinti. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 244;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 23) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0110011xx1x1x00111x0xx
|
|
|
|
frintm. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 178;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0110011xx1x1x00111x1xx
|
|
|
|
frintx. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 226;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0110011xx1x1x10111x0xx
|
|
|
|
frintz. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 198;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0110011xx1x1x10111x1xx
|
|
|
|
frinti. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 245;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 28) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 19) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx011010xxx0x1xx011100xx
|
|
|
|
cnt. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 160;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 22) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx011010xxx0x10x011101xx
|
|
|
|
not. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 235;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx011010xxx0x11x011101xx
|
|
|
|
rbit. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 237;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx011010xxx1x1xx01110xxx
|
|
|
|
aesd. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 647;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx011010xxxxx1xx01111xxx
|
|
|
|
fmin. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 793;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 16) & 0x1) == 0)
|
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 19) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 20) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 28) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0110110xx001xx011100xx
|
|
|
|
fcmeq. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 189;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0110110xx001xx011101xx
|
|
|
|
fcmle. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 240;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0110110xx001xx011110xx
|
|
|
|
fcmeq. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 488;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0110110xx001xx011111xx
|
|
|
|
fcmle. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 518;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2015-12-14 18:35:47 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0110110xx011xx0111x0xx
|
|
|
|
faddp. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 532;
|
2015-12-14 18:35:47 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0110110xx011xx0111x1xx
|
|
|
|
faddp. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 531;
|
2015-12-14 18:35:47 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
if (((word >> 28) & 0x1) == 0)
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
{
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0110110xx1x1xx011100xx
|
|
|
|
fcmeq. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 190;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0110110xx1x1xx011101xx
|
|
|
|
fcmle. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 241;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0110110xx1x1xx011110xx
|
|
|
|
fcmeq. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 489;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0110110xx1x1xx011111xx
|
|
|
|
fcmle. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 519;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 19) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 23) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 28) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0110111xx0x1x0011100xx
|
|
|
|
scvtf. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 185;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0110111xx0x1x0011101xx
|
|
|
|
ucvtf. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 233;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0110111xx0x1x0011110xx
|
|
|
|
scvtf. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 484;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0110111xx0x1x0011111xx
|
|
|
|
ucvtf. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 514;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 28) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0110111xx0x1x1011100xx
|
|
|
|
frecpe. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 204;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0110111xx0x1x1011101xx
|
|
|
|
frsqrte. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 251;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0110111xx0x1x1011110xx
|
|
|
|
frecpe. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 496;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0110111xx0x1x1011111xx
|
|
|
|
frsqrte. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 524;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 23) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
if (((word >> 28) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0110111xx1x1x0011100xx
|
|
|
|
scvtf. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 186;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0110111xx1x1x0011101xx
|
|
|
|
ucvtf. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 234;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0110111xx1x1x0011110xx
|
|
|
|
scvtf. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 485;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0110111xx1x1x0011111xx
|
|
|
|
ucvtf. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 515;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
if (((word >> 28) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0110111xx1x1x1011100xx
|
|
|
|
frecpe. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 205;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0110111xx1x1x1011101xx
|
|
|
|
frsqrte. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 252;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0110111xx1x1x1011110xx
|
|
|
|
frecpe. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 497;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0110111xx1x1x1011111xx
|
|
|
|
frsqrte. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 525;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 28) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 16) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 20) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111000xxx01xx011100xx
|
|
|
|
suqadd. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 158;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111000xxx01xx011101xx
|
|
|
|
usqadd. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 208;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111000xxx11xx011100xx
|
|
|
|
saddlv. */
|
|
|
|
return 27;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111000xxx11xx011101xx
|
|
|
|
uaddlv. */
|
|
|
|
return 31;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111001xxxx1xx01110x0x
|
|
|
|
shll. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 217;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111001xxxx1xx01110x1x
|
|
|
|
shll2. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 218;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx011100xxxxx1xx0111100x
|
|
|
|
fsub. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 789;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx011100xxxxx1xx0111101x
|
|
|
|
suqadd. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 471;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx011100xxxxx1xx011111xx
|
|
|
|
usqadd. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 500;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 16) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 28) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111010xxxx1xx011100xx
|
|
|
|
abs. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 166;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111010xxxx1xx011101xx
|
|
|
|
neg. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 214;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111010xxxx1xx011110xx
|
|
|
|
abs. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 476;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111010xxxx1xx011111xx
|
|
|
|
neg. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 504;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 19) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 20) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 23) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 28) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111011xx001x0011100xx
|
|
|
|
fcvtms. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 181;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111011xx001x0011101xx
|
|
|
|
fcvtmu. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 229;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111011xx001x0011110xx
|
|
|
|
fcvtms. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 480;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111011xx001x0011111xx
|
|
|
|
fcvtmu. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 510;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 28) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111011xx001x1011100xx
|
|
|
|
fcvtzs. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 201;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111011xx001x1011101xx
|
|
|
|
fcvtzu. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 248;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111011xx001x1011110xx
|
|
|
|
fcvtzs. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 494;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111011xx001x1011111xx
|
|
|
|
fcvtzu. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 522;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 28) & 0x1) == 0)
|
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111011xx011xx01110xxx
|
|
|
|
addv. */
|
|
|
|
return 30;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111011xx011xx01111xxx
|
|
|
|
addp. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 528;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 23) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
if (((word >> 28) & 0x1) == 0)
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
{
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111011xx1x1x0011100xx
|
|
|
|
fcvtms. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 182;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111011xx1x1x0011101xx
|
|
|
|
fcvtmu. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 230;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111011xx1x1x0011110xx
|
|
|
|
fcvtms. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 481;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111011xx1x1x0011111xx
|
|
|
|
fcvtmu. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 511;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
if (((word >> 28) & 0x1) == 0)
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
{
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111011xx1x1x1011100xx
|
|
|
|
fcvtzs. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 202;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111011xx1x1x1011101xx
|
|
|
|
fcvtzu. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 249;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111011xx1x1x1011110xx
|
|
|
|
fcvtzs. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 495;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111011xx1x1x1011111xx
|
|
|
|
fcvtzu. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 523;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 28) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 16) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 19) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111100xx0x1xx011100xx
|
|
|
|
sqabs. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 162;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111100xx0x1xx011101xx
|
|
|
|
sqneg. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 211;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111100xx1x1xx01110xxx
|
|
|
|
aesimc. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 649;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111101xxxx1xx01110x0x
|
|
|
|
fcvtl. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 173;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111101xxxx1xx01110x1x
|
|
|
|
fcvtl2. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 174;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx011110xxxxx1xx0111100x
|
|
|
|
fminnm. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 797;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx011110xxxxx1xx0111101x
|
|
|
|
sqabs. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 472;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx011110xxxxx1xx011111xx
|
|
|
|
sqneg. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 501;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 16) & 0x1) == 0)
|
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 19) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 20) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
xxxxxxxxxx0111110xx001xx0111x0xx
|
|
|
|
fabs. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 193;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
xxxxxxxxxx0111110xx001xx0111x1xx
|
|
|
|
fneg. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 242;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 23) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 28) & 0x1) == 0)
|
|
|
|
{
|
2015-12-14 18:16:50 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111110xx011x0011100xx
|
|
|
|
fmaxv. */
|
|
|
|
return 37;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111110xx011x0011101xx
|
|
|
|
fmaxv. */
|
|
|
|
return 36;
|
|
|
|
}
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2015-12-14 18:35:47 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111110xx011x0011110xx
|
|
|
|
fmaxp. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 534;
|
2015-12-14 18:35:47 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111110xx011x0011111xx
|
|
|
|
fmaxp. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 533;
|
2015-12-14 18:35:47 +01:00
|
|
|
}
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 28) & 0x1) == 0)
|
|
|
|
{
|
2015-12-14 18:16:50 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111110xx011x1011100xx
|
|
|
|
fminv. */
|
|
|
|
return 41;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111110xx011x1011101xx
|
|
|
|
fminv. */
|
|
|
|
return 40;
|
|
|
|
}
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2015-12-14 18:35:47 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111110xx011x1011110xx
|
|
|
|
fminp. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 538;
|
2015-12-14 18:35:47 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111110xx011x1011111xx
|
|
|
|
fminp. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 537;
|
2015-12-14 18:35:47 +01:00
|
|
|
}
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111110xx1x1xx0111x0xx
|
|
|
|
fabs. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 194;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111110xx1x1xx0111x1xx
|
|
|
|
fneg. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 243;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 19) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
if (((word >> 28) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111111xx0x1xx01110xxx
|
|
|
|
fsqrt. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 253;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111111xx0x1xx01111xxx
|
|
|
|
frecpx. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 498;
|
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14 17:54:38 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
if (((word >> 28) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111111xx1x1xx01110xxx
|
|
|
|
fsqrt. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 254;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0111111xx1x1xx01111xxx
|
|
|
|
frecpx. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 499;
|
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14 17:57:04 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 11) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 28) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 12) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx100000xxxxx1xx011100xx
|
|
|
|
shadd. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 261;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx100000xxxxx1xx011101xx
|
|
|
|
uhadd. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 313;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx100001xxxxx1xx011100xx
|
|
|
|
add. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 276;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx100001xxxxx1xx011101xx
|
|
|
|
sub. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 328;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx100010xxxxx1xx011100xx
|
|
|
|
sshl. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 268;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx100010xxxxx1xx011101xx
|
|
|
|
ushl. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 320;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx100011xxxxx1x0011100xx
|
|
|
|
fmaxnm. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 284;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx100011xxxxx1x0011101xx
|
|
|
|
fmaxnmp. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 335;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx100011xxxxx1x1011100xx
|
|
|
|
fminnm. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 300;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx100011xxxxx1x1011101xx
|
|
|
|
fminnmp. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 351;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx100100xxxxx1xx011100xx
|
|
|
|
shsub. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 264;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx100100xxxxx1xx011101xx
|
|
|
|
uhsub. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 316;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx100101xxxxx1xx011100xx
|
|
|
|
smaxp. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 280;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx100101xxxxx1xx011101xx
|
|
|
|
umaxp. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 332;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx100110xxxxx1xx011100xx
|
|
|
|
smax. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 272;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx100110xxxxx1xx011101xx
|
|
|
|
umax. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 324;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx100111xxxxx1x0011100xx
|
|
|
|
fcmeq. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 292;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx100111xxxxx1x0011101xx
|
|
|
|
fcmge. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 341;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx100111xxxxx1x101110xxx
|
|
|
|
fcmgt. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 355;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx101000xxxxx1xx011100xx
|
|
|
|
srhadd. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 263;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx101000xxxxx1xx011101xx
|
|
|
|
urhadd. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 315;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx101001xxxxx1xx011100xx
|
|
|
|
mla. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 278;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx101001xxxxx1xx011101xx
|
|
|
|
mls. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 330;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx101010xxxxx1xx011100xx
|
|
|
|
srshl. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 270;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx101010xxxxx1xx011101xx
|
|
|
|
urshl. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 322;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx101011xxxxx1x0011100xx
|
|
|
|
fadd. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 288;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx101011xxxxx1x0011101xx
|
|
|
|
faddp. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 337;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx101011xxxxx1x1011100xx
|
|
|
|
fsub. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 304;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx101011xxxxx1x1011101xx
|
|
|
|
fabd. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 353;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx101100xxxxx1xx011100xx
|
|
|
|
cmgt. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 266;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx101100xxxxx1xx011101xx
|
|
|
|
cmhi. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 318;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx101101xxxxx1xx011100xx
|
|
|
|
sqdmulh. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 282;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx101101xxxxx1xx011101xx
|
|
|
|
sqrdmulh. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 334;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx101110xxxxx1xx011100xx
|
|
|
|
sabd. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 274;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx101110xxxxx1xx011101xx
|
|
|
|
uabd. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 326;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx101111xxxxx1x0011100xx
|
|
|
|
fmax. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 294;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx101111xxxxx1x0011101xx
|
|
|
|
fmaxp. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 345;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx101111xxxxx1x1011100xx
|
|
|
|
fmin. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 306;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx101111xxxxx1x1011101xx
|
|
|
|
fminp. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 359;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 4) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxx0xxxxx10xxxxxxxxx1xx0111100x
|
|
|
|
fccmp. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 748;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxx1xxxxx10xxxxxxxxx1xx0111100x
|
|
|
|
fccmpe. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 750;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 12) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx10000xxxxxx1xx0111101x
|
|
|
|
add. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 556;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx10001xxxxxx1xx0111101x
|
|
|
|
sshl. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 554;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1001xxxxxxx1xx0111101x
|
|
|
|
fcmeq. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 546;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1010xxxxxxx1xx0111101x
|
|
|
|
srshl. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 555;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1011x0xxxxx1xx0111101x
|
|
|
|
cmgt. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 552;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1011x1xxxxx1xx0111101x
|
|
|
|
sqdmulh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 543;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 12) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx10000xxxxxx1xx011111xx
|
|
|
|
sub. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 577;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx10001xxxxxx1xx011111xx
|
|
|
|
ushl. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 575;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1001xxxxxxx1x0011111xx
|
|
|
|
fcmge. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 563;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1001xxxxxxx1x1011111xx
|
|
|
|
fcmgt. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 569;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1010x0xxxxx1xx011111xx
|
|
|
|
urshl. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 576;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1010x1xxxxx1xx011111xx
|
|
|
|
fabd. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 567;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1011x0xxxxx1xx011111xx
|
|
|
|
cmhi. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 573;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1011x1xxxxx1xx011111xx
|
|
|
|
sqrdmulh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 562;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 28) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 12) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx110000xxxxx1xx011100xx
|
|
|
|
sqadd. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 262;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx110000xxxxx1xx011101xx
|
|
|
|
uqadd. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 314;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx110001xxxxx1xx011100xx
|
|
|
|
cmtst. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 277;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx110001xxxxx1xx011101xx
|
|
|
|
cmeq. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 329;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx110010xxxxx1xx011100xx
|
|
|
|
sqshl. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 269;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx110010xxxxx1xx011101xx
|
|
|
|
uqshl. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 321;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx110011xxxxx1x001110xxx
|
|
|
|
fmla. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 286;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx110011xxxxx1x101110xxx
|
|
|
|
fmls. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 302;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx110100xxxxx1xx011100xx
|
|
|
|
sqsub. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 265;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx110100xxxxx1xx011101xx
|
|
|
|
uqsub. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 317;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx110101xxxxx1xx011100xx
|
|
|
|
sminp. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 281;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx110101xxxxx1xx011101xx
|
|
|
|
uminp. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 333;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx110110xxxxx1xx011100xx
|
|
|
|
smin. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 273;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx110110xxxxx1xx011101xx
|
|
|
|
umin. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 325;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx110111xxxxx1x001110xxx
|
|
|
|
facge. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 343;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx110111xxxxx1x101110xxx
|
|
|
|
facgt. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 357;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 22) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx111000xxxxx100011100xx
|
|
|
|
and. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 298;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx111000xxxxx100011101xx
|
|
|
|
eor. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 349;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx111000xxxxx101011100xx
|
|
|
|
orr. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 310;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx111000xxxxx101011101xx
|
|
|
|
bit. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 361;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx111000xxxxx110011100xx
|
|
|
|
bic. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 299;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx111000xxxxx110011101xx
|
|
|
|
bsl. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 350;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx111000xxxxx111011100xx
|
|
|
|
orn. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 312;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx111000xxxxx111011101xx
|
|
|
|
bif. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 362;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx111001xxxxx1xx011100xx
|
|
|
|
mul. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 279;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx111001xxxxx1xx011101xx
|
|
|
|
pmul. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 331;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx111010xxxxx1xx011100xx
|
|
|
|
sqrshl. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 271;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx111010xxxxx1xx011101xx
|
|
|
|
uqrshl. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 323;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx111011xxxxx1xx011100xx
|
|
|
|
fmulx. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 290;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx111011xxxxx1xx011101xx
|
|
|
|
fmul. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 339;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx111100xxxxx1xx011100xx
|
|
|
|
cmge. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 267;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx111100xxxxx1xx011101xx
|
|
|
|
cmhs. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 319;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx111101xxxxx1xx01110xxx
|
|
|
|
addp. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 283;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx111110xxxxx1xx011100xx
|
|
|
|
saba. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 275;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx111110xxxxx1xx011101xx
|
|
|
|
uaba. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 327;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx111111xxxxx1x0011100xx
|
|
|
|
frecps. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 296;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx111111xxxxx1x0011101xx
|
|
|
|
fdiv. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 347;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx111111xxxxx1x101110xxx
|
|
|
|
frsqrts. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 308;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx11xxxxxxxxx1xx0111100x
|
|
|
|
fcsel. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 811;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 12) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx110000xxxxx1xx0111101x
|
|
|
|
sqadd. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 539;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx110001xxxxx1xx0111101x
|
|
|
|
cmtst. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 557;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx11001xxxxxx1xx0111101x
|
|
|
|
sqshl. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 541;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1101xxxxxxx1xx0111101x
|
|
|
|
sqsub. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 540;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1110x0xxxxx1xx0111101x
|
|
|
|
sqrshl. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 542;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1110x1xxxxx1xx0111101x
|
|
|
|
fmulx. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 544;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx11110xxxxxx1xx0111101x
|
|
|
|
cmge. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 553;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx11111xxxxxx1x00111101x
|
|
|
|
frecps. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 548;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx11111xxxxxx1x10111101x
|
|
|
|
frsqrts. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 550;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 12) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx110000xxxxx1xx011111xx
|
|
|
|
uqadd. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 558;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx110001xxxxx1xx011111xx
|
|
|
|
cmeq. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 578;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx11001xxxxxx1xx011111xx
|
|
|
|
uqshl. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 560;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx11010xxxxxx1xx011111xx
|
|
|
|
uqsub. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 559;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx11011xxxxxx1x0011111xx
|
|
|
|
facge. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 565;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx11011xxxxxx1x1011111xx
|
|
|
|
facgt. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 571;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1110xxxxxxx1xx011111xx
|
|
|
|
uqrshl. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 561;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1111xxxxxxx1xx011111xx
|
|
|
|
cmhs. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 574;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 15) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 28) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 10) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 12) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x0000xxxxxxxx11110xxx
|
|
|
|
mla. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 117;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x0010xxxxxxxx11110xxx
|
|
|
|
mls. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 120;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x0100xxxxxxxx1111000x
|
|
|
|
smlal. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 96;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x0100xxxxxxxx1111001x
|
|
|
|
smlal2. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 97;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x0100xxxxxxxx1111010x
|
|
|
|
umlal. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 118;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x0100xxxxxxxx1111011x
|
|
|
|
umlal2. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 119;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x0110xxxxxxxx1111000x
|
|
|
|
smlsl. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 100;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x0110xxxxxxxx1111001x
|
|
|
|
smlsl2. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 101;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x0110xxxxxxxx1111010x
|
|
|
|
umlsl. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 121;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x0110xxxxxxxx1111011x
|
|
|
|
umlsl2. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 122;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
2015-12-14 18:01:56 +01:00
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x1000xxxxxxx011110xxx
|
|
|
|
fmla. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 112;
|
2015-12-14 18:01:56 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x1000xxxxxxx111110xxx
|
|
|
|
fmla. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 111;
|
2015-12-14 18:01:56 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2015-12-14 18:01:56 +01:00
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x1010xxxxxxx011110xxx
|
|
|
|
fmls. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 114;
|
2015-12-14 18:01:56 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x1010xxxxxxx111110xxx
|
|
|
|
fmls. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 113;
|
2015-12-14 18:01:56 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x1100xxxxxxxx11110x0x
|
|
|
|
sqdmlal. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 98;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x1100xxxxxxxx11110x1x
|
|
|
|
sqdmlal2. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 99;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x1110xxxxxxxx11110x0x
|
|
|
|
sqdmlsl. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 102;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x1110xxxxxxxx11110x1x
|
|
|
|
sqdmlsl2. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 103;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 12) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1x0xx0xxxxxxxx111100xx
|
|
|
|
movi. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 130;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1x0xx0xxxxxxxx111101xx
|
|
|
|
mvni. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 138;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1x1xx0xxxxxxxx111100xx
|
|
|
|
orr. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 131;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1x1xx0xxxxxxxx111101xx
|
|
|
|
bic. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 139;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 21) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxx0xxxxx0xx1111100x
|
|
|
|
fmadd. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 801;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxx0xxxxx1xx1111100x
|
|
|
|
fnmadd. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 805;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 10) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
2015-12-14 18:07:51 +01:00
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0xx000xxxxxxx01111101x
|
|
|
|
fmla. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 422;
|
2015-12-14 18:07:51 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0xx000xxxxxxx11111101x
|
|
|
|
fmla. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 421;
|
2015-12-14 18:07:51 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2015-12-14 18:07:51 +01:00
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0xx010xxxxxxx01111101x
|
|
|
|
fmls. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 424;
|
2015-12-14 18:07:51 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0xx010xxxxxxx11111101x
|
|
|
|
fmls. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 423;
|
2015-12-14 18:07:51 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0xx100xxxxxxxx1111101x
|
|
|
|
sqdmlal. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 416;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0xx110xxxxxxxx1111101x
|
|
|
|
sqdmlsl. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 417;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 12) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1x00x0xxxxxxxx1111101x
|
|
|
|
sshr. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 581;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1x01x0xxxxxxxx1111101x
|
|
|
|
srshr. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 583;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1x1000xxxxxxxx1111101x
|
|
|
|
ssra. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 582;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1x1010xxxxxxxx1111101x
|
|
|
|
shl. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 585;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1x1100xxxxxxxx1111101x
|
|
|
|
srsra. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 584;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1x1110xxxxxxxx1111101x
|
|
|
|
sqshl. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 586;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 12) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxx0000xxxxxxxx111111xx
|
|
|
|
ushr. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 591;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxx0010xxxxxxxx111111xx
|
|
|
|
sri. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 595;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxx0100xxxxxxxx111111xx
|
|
|
|
urshr. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 593;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxx0110xxxxxxxx111111xx
|
|
|
|
sqshlu. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 597;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxx1000xxxxxxxx111111xx
|
|
|
|
usra. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 592;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxx1010xxxxxxxx111111xx
|
|
|
|
sli. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 596;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxx1100xxxxxxxx111111xx
|
|
|
|
ursra. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 594;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxx1110xxxxxxxx111111xx
|
|
|
|
uqshl. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 598;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 28) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 10) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 12) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x0001xxxxxxxx11110xxx
|
|
|
|
mul. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 104;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x0011xxxxxxxx11110xxx
|
|
|
|
sqdmulh. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 109;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x01x1xxxxxxxx1111000x
|
|
|
|
smull. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 105;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x01x1xxxxxxxx1111001x
|
|
|
|
smull2. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 106;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x01x1xxxxxxxx1111010x
|
|
|
|
umull. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 123;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x01x1xxxxxxxx1111011x
|
|
|
|
umull2. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 124;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
2015-12-14 18:01:56 +01:00
|
|
|
if (((word >> 23) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
2015-12-14 18:01:56 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x1001xxxxxxx0111100xx
|
|
|
|
fmul. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 116;
|
2015-12-14 18:01:56 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x1001xxxxxxx0111101xx
|
|
|
|
fmulx. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 126;
|
2015-12-14 18:01:56 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2015-12-14 18:01:56 +01:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x1001xxxxxxx1111100xx
|
|
|
|
fmul. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 115;
|
2015-12-14 18:01:56 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x1001xxxxxxx1111101xx
|
|
|
|
fmulx. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 125;
|
2015-12-14 18:01:56 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2015-06-02 13:20:00 +02:00
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x1011xxxxxxxx111100xx
|
|
|
|
sqrdmulh. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 110;
|
2015-06-02 13:20:00 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x1011xxxxxxxx111101xx
|
|
|
|
sqrdmlah. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 127;
|
2015-06-02 13:20:00 +02:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2015-06-02 13:20:00 +02:00
|
|
|
if (((word >> 14) & 0x1) == 0)
|
2012-08-13 16:52:54 +02:00
|
|
|
{
|
2015-06-02 13:20:00 +02:00
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x1101xxxxxxxx11110x0x
|
|
|
|
sqdmull. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 107;
|
2015-06-02 13:20:00 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x1101xxxxxxxx11110x1x
|
|
|
|
sqdmull2. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 108;
|
2015-06-02 13:20:00 +02:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
2015-06-02 13:20:00 +02:00
|
|
|
xxxxxxxxxx0x1111xxxxxxxx11110xxx
|
|
|
|
sqrdmlsh. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 128;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 11) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 12) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx100x01xxxxxxxx111100xx
|
|
|
|
movi. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 132;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx100x01xxxxxxxx111101xx
|
|
|
|
mvni. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 140;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx101x01xxxxxxxx111100xx
|
|
|
|
orr. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 133;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx101x01xxxxxxxx111101xx
|
|
|
|
bic. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 141;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx10x011xxxxxxxx111100xx
|
|
|
|
movi. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 134;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx10x011xxxxxxxx111101xx
|
|
|
|
mvni. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 142;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 12) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx100111xxxxxxxx111100xx
|
|
|
|
movi. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 135;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx100111xxxxxxxx111101xx
|
|
|
|
movi. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 143;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx101111xxxxxxxx111100xx
|
|
|
|
fmov. */
|
2015-12-14 18:16:50 +01:00
|
|
|
return 136;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx101111xxxxxxxx111101xx
|
|
|
|
fmov. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 145;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 12) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx110xx1xxxxxxxx1111000x
|
|
|
|
rshrn. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 373;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx110xx1xxxxxxxx1111001x
|
|
|
|
rshrn2. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 374;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx110xx1xxxxxxxx1111010x
|
|
|
|
sqrshrun. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 397;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx110xx1xxxxxxxx1111011x
|
|
|
|
sqrshrun2. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 398;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1110x1xxxxxxxx1111000x
|
|
|
|
sqrshrn. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 377;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1110x1xxxxxxxx1111001x
|
|
|
|
sqrshrn2. */
|
2015-12-14 18:22:36 +01:00
|
|
|
return 378;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1110x1xxxxxxxx1111010x
|
|
|
|
uqrshrn. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 401;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1110x1xxxxxxxx1111011x
|
|
|
|
uqrshrn2. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 402;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1111x1xxxxxxxx111100xx
|
2015-12-14 18:22:36 +01:00
|
|
|
fmov. */
|
|
|
|
return 137;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1111x1xxxxxxxx111101xx
|
|
|
|
fcvtzu. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 409;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 29) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 30) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 21) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxx1xxxxx0xx1111100x
|
|
|
|
fmsub. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 803;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxxxxxxx1xxxxx1xx1111100x
|
|
|
|
fnmsub. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 807;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 10) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 12) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x0xx1xxxxxxxx1111101x
|
|
|
|
sqdmulh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 419;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
2015-12-14 18:07:51 +01:00
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x1001xxxxxxx01111101x
|
|
|
|
fmul. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 426;
|
2015-12-14 18:07:51 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x1001xxxxxxx11111101x
|
|
|
|
fmul. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 425;
|
2015-12-14 18:07:51 +01:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x1011xxxxxxxx1111101x
|
|
|
|
sqrdmulh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 420;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0x11x1xxxxxxxx1111101x
|
|
|
|
sqdmull. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 418;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 11) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 12) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx100xx1xxxxxxxx1111101x
|
|
|
|
scvtf. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 589;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx101xx1xxxxxxxx1111101x
|
|
|
|
sqshrn. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 587;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx11x0x1xxxxxxxx1111101x
|
|
|
|
sqrshrn. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 588;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx11x1x1xxxxxxxx1111101x
|
|
|
|
fcvtzs. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 590;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 10) & 0x1) == 0)
|
|
|
|
{
|
2015-06-02 13:20:00 +02:00
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 14) & 0x1) == 0)
|
|
|
|
{
|
2015-12-14 18:07:51 +01:00
|
|
|
if (((word >> 23) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0xx001xxxxxxx0111111xx
|
|
|
|
fmulx. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 428;
|
2015-12-14 18:07:51 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0xx001xxxxxxx1111111xx
|
|
|
|
fmulx. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 427;
|
2015-12-14 18:07:51 +01:00
|
|
|
}
|
2015-06-02 13:20:00 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0xx011xxxxxxxx111111xx
|
|
|
|
sqrdmlah. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 429;
|
2015-06-02 13:20:00 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx0xx1x1xxxxxxxx111111xx
|
|
|
|
sqrdmlsh. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 430;
|
2015-06-02 13:20:00 +02:00
|
|
|
}
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 11) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 12) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1000x1xxxxxxxx111111xx
|
|
|
|
sqshrun. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 599;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1001x1xxxxxxxx111111xx
|
|
|
|
ucvtf. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 603;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx101xx1xxxxxxxx111111xx
|
|
|
|
uqshrn. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 601;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 12) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx110xx1xxxxxxxx111111xx
|
|
|
|
sqrshrun. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 600;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (((word >> 13) & 0x1) == 0)
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1110x1xxxxxxxx111111xx
|
|
|
|
uqrshrn. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 602;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* 33222222222211111111110000000000
|
|
|
|
10987654321098765432109876543210
|
|
|
|
xxxxxxxxxx1111x1xxxxxxxx111111xx
|
|
|
|
fcvtzu. */
|
2015-12-14 18:40:03 +01:00
|
|
|
return 604;
|
2012-08-13 16:52:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Lookup opcode WORD in the opcode table. N.B. all alias
|
|
|
|
opcodes are ignored here. */
|
|
|
|
|
|
|
|
const aarch64_opcode *
|
|
|
|
aarch64_opcode_lookup (uint32_t word)
|
|
|
|
{
|
|
|
|
return aarch64_opcode_table + aarch64_opcode_lookup_1 (word);
|
|
|
|
}
|
|
|
|
|
|
|
|
const aarch64_opcode *
|
|
|
|
aarch64_find_next_opcode (const aarch64_opcode *opcode)
|
|
|
|
{
|
|
|
|
/* Use the index as the key to locate the next opcode. */
|
|
|
|
int key = opcode - aarch64_opcode_table;
|
|
|
|
int value;
|
|
|
|
switch (key)
|
|
|
|
{
|
2015-12-14 18:40:03 +01:00
|
|
|
case 897: value = 901; break; /* stnp --> stp. */
|
|
|
|
case 901: return NULL; /* stp --> NULL. */
|
|
|
|
case 895: value = 896; break; /* stllrb --> stllrh. */
|
|
|
|
case 896: return NULL; /* stllrh --> NULL. */
|
|
|
|
case 898: value = 902; break; /* ldnp --> ldp. */
|
|
|
|
case 902: return NULL; /* ldp --> NULL. */
|
|
|
|
case 1113: value = 1114; break; /* msr --> hint. */
|
|
|
|
case 1114: value = 1123; break; /* hint --> clrex. */
|
|
|
|
case 1123: value = 1124; break; /* clrex --> dsb. */
|
|
|
|
case 1124: value = 1125; break; /* dsb --> dmb. */
|
|
|
|
case 1125: value = 1126; break; /* dmb --> isb. */
|
|
|
|
case 1126: value = 1127; break; /* isb --> sys. */
|
|
|
|
case 1127: value = 1132; break; /* sys --> msr. */
|
|
|
|
case 1132: return NULL; /* msr --> NULL. */
|
|
|
|
case 1133: value = 1134; break; /* sysl --> mrs. */
|
|
|
|
case 1134: return NULL; /* mrs --> NULL. */
|
|
|
|
case 431: value = 432; break; /* st4 --> st1. */
|
|
|
|
case 432: value = 433; break; /* st1 --> st2. */
|
|
|
|
case 433: value = 434; break; /* st2 --> st3. */
|
|
|
|
case 434: return NULL; /* st3 --> NULL. */
|
|
|
|
case 439: value = 440; break; /* st4 --> st1. */
|
|
|
|
case 440: value = 441; break; /* st1 --> st2. */
|
|
|
|
case 441: value = 442; break; /* st2 --> st3. */
|
|
|
|
case 442: return NULL; /* st3 --> NULL. */
|
|
|
|
case 435: value = 436; break; /* ld4 --> ld1. */
|
|
|
|
case 436: value = 437; break; /* ld1 --> ld2. */
|
|
|
|
case 437: value = 438; break; /* ld2 --> ld3. */
|
|
|
|
case 438: return NULL; /* ld3 --> NULL. */
|
|
|
|
case 451: value = 453; break; /* ld1 --> ld1r. */
|
|
|
|
case 453: return NULL; /* ld1r --> NULL. */
|
|
|
|
case 455: value = 457; break; /* ld2 --> ld2r. */
|
|
|
|
case 457: return NULL; /* ld2r --> NULL. */
|
|
|
|
case 452: value = 454; break; /* ld3 --> ld3r. */
|
|
|
|
case 454: return NULL; /* ld3r --> NULL. */
|
|
|
|
case 456: value = 458; break; /* ld4 --> ld4r. */
|
|
|
|
case 458: return NULL; /* ld4r --> NULL. */
|
|
|
|
case 443: value = 444; break; /* ld4 --> ld1. */
|
|
|
|
case 444: value = 445; break; /* ld1 --> ld2. */
|
|
|
|
case 445: value = 446; break; /* ld2 --> ld3. */
|
|
|
|
case 446: return NULL; /* ld3 --> NULL. */
|
|
|
|
case 463: value = 465; break; /* ld1 --> ld1r. */
|
|
|
|
case 465: return NULL; /* ld1r --> NULL. */
|
|
|
|
case 464: value = 466; break; /* ld3 --> ld3r. */
|
|
|
|
case 466: return NULL; /* ld3r --> NULL. */
|
|
|
|
case 467: value = 469; break; /* ld2 --> ld2r. */
|
|
|
|
case 469: return NULL; /* ld2r --> NULL. */
|
|
|
|
case 468: value = 470; break; /* ld4 --> ld4r. */
|
|
|
|
case 470: return NULL; /* ld4r --> NULL. */
|
|
|
|
case 714: value = 715; break; /* fcvtzs --> fcvtzs. */
|
|
|
|
case 715: return NULL; /* fcvtzs --> NULL. */
|
|
|
|
case 710: value = 711; break; /* scvtf --> scvtf. */
|
|
|
|
case 711: return NULL; /* scvtf --> NULL. */
|
|
|
|
case 716: value = 717; break; /* fcvtzu --> fcvtzu. */
|
|
|
|
case 717: return NULL; /* fcvtzu --> NULL. */
|
|
|
|
case 712: value = 713; break; /* ucvtf --> ucvtf. */
|
|
|
|
case 713: return NULL; /* ucvtf --> NULL. */
|
|
|
|
case 718: value = 719; break; /* fcvtns --> fcvtns. */
|
|
|
|
case 719: return NULL; /* fcvtns --> NULL. */
|
|
|
|
case 738: value = 739; break; /* fcvtms --> fcvtms. */
|
|
|
|
case 739: return NULL; /* fcvtms --> NULL. */
|
|
|
|
case 734: value = 735; break; /* fcvtps --> fcvtps. */
|
|
|
|
case 735: return NULL; /* fcvtps --> NULL. */
|
|
|
|
case 742: value = 743; break; /* fcvtzs --> fcvtzs. */
|
|
|
|
case 743: return NULL; /* fcvtzs --> NULL. */
|
|
|
|
case 726: value = 727; break; /* fcvtas --> fcvtas. */
|
|
|
|
case 727: return NULL; /* fcvtas --> NULL. */
|
|
|
|
case 722: value = 723; break; /* scvtf --> scvtf. */
|
|
|
|
case 723: return NULL; /* scvtf --> NULL. */
|
|
|
|
case 730: value = 731; break; /* fmov --> fmov. */
|
|
|
|
case 731: return NULL; /* fmov --> NULL. */
|
|
|
|
case 720: value = 721; break; /* fcvtnu --> fcvtnu. */
|
|
|
|
case 721: return NULL; /* fcvtnu --> NULL. */
|
|
|
|
case 740: value = 741; break; /* fcvtmu --> fcvtmu. */
|
|
|
|
case 741: return NULL; /* fcvtmu --> NULL. */
|
|
|
|
case 736: value = 737; break; /* fcvtpu --> fcvtpu. */
|
|
|
|
case 737: return NULL; /* fcvtpu --> NULL. */
|
|
|
|
case 744: value = 745; break; /* fcvtzu --> fcvtzu. */
|
|
|
|
case 745: return NULL; /* fcvtzu --> NULL. */
|
|
|
|
case 728: value = 729; break; /* fcvtau --> fcvtau. */
|
|
|
|
case 729: return NULL; /* fcvtau --> NULL. */
|
|
|
|
case 724: value = 725; break; /* ucvtf --> ucvtf. */
|
|
|
|
case 725: return NULL; /* ucvtf --> NULL. */
|
|
|
|
case 732: value = 733; break; /* fmov --> fmov. */
|
|
|
|
case 733: return NULL; /* fmov --> NULL. */
|
|
|
|
case 760: value = 761; break; /* fmov --> fmov. */
|
|
|
|
case 761: return NULL; /* fmov --> NULL. */
|
|
|
|
case 769: value = 770; break; /* frintn --> frintn. */
|
|
|
|
case 770: return NULL; /* frintn --> NULL. */
|
|
|
|
case 764: value = 765; break; /* fneg --> fneg. */
|
|
|
|
case 765: return NULL; /* fneg --> NULL. */
|
|
|
|
case 773: value = 774; break; /* frintm --> frintm. */
|
|
|
|
case 774: return NULL; /* frintm --> NULL. */
|
|
|
|
case 762: value = 763; break; /* fabs --> fabs. */
|
|
|
|
case 763: return NULL; /* fabs --> NULL. */
|
|
|
|
case 771: value = 772; break; /* frintp --> frintp. */
|
|
|
|
case 772: return NULL; /* frintp --> NULL. */
|
|
|
|
case 766: value = 767; break; /* fsqrt --> fsqrt. */
|
|
|
|
case 767: return NULL; /* fsqrt --> NULL. */
|
|
|
|
case 775: value = 776; break; /* frintz --> frintz. */
|
|
|
|
case 776: return NULL; /* frintz --> NULL. */
|
|
|
|
case 777: value = 778; break; /* frinta --> frinta. */
|
|
|
|
case 778: return NULL; /* frinta --> NULL. */
|
|
|
|
case 779: value = 780; break; /* frintx --> frintx. */
|
|
|
|
case 780: return NULL; /* frintx --> NULL. */
|
|
|
|
case 781: value = 782; break; /* frinti --> frinti. */
|
|
|
|
case 782: return NULL; /* frinti --> NULL. */
|
2015-12-14 18:35:47 +01:00
|
|
|
case 752: value = 753; break; /* fcmp --> fcmp. */
|
|
|
|
case 753: return NULL; /* fcmp --> NULL. */
|
|
|
|
case 754: value = 755; break; /* fcmpe --> fcmpe. */
|
|
|
|
case 755: return NULL; /* fcmpe --> NULL. */
|
2015-12-14 18:40:03 +01:00
|
|
|
case 756: value = 757; break; /* fcmp --> fcmp. */
|
|
|
|
case 757: return NULL; /* fcmp --> NULL. */
|
|
|
|
case 758: value = 759; break; /* fcmpe --> fcmpe. */
|
|
|
|
case 759: return NULL; /* fcmpe --> NULL. */
|
|
|
|
case 809: value = 810; break; /* fmov --> fmov. */
|
|
|
|
case 810: return NULL; /* fmov --> NULL. */
|
|
|
|
case 783: value = 784; break; /* fmul --> fmul. */
|
|
|
|
case 784: return NULL; /* fmul --> NULL. */
|
|
|
|
case 799: value = 800; break; /* fnmul --> fnmul. */
|
|
|
|
case 800: return NULL; /* fnmul --> NULL. */
|
|
|
|
case 791: value = 792; break; /* fmax --> fmax. */
|
|
|
|
case 792: return NULL; /* fmax --> NULL. */
|
|
|
|
case 787: value = 788; break; /* fadd --> fadd. */
|
|
|
|
case 788: return NULL; /* fadd --> NULL. */
|
|
|
|
case 795: value = 796; break; /* fmaxnm --> fmaxnm. */
|
|
|
|
case 796: return NULL; /* fmaxnm --> NULL. */
|
|
|
|
case 785: value = 786; break; /* fdiv --> fdiv. */
|
|
|
|
case 786: return NULL; /* fdiv --> NULL. */
|
|
|
|
case 793: value = 794; break; /* fmin --> fmin. */
|
|
|
|
case 794: return NULL; /* fmin --> NULL. */
|
|
|
|
case 789: value = 790; break; /* fsub --> fsub. */
|
|
|
|
case 790: return NULL; /* fsub --> NULL. */
|
|
|
|
case 797: value = 798; break; /* fminnm --> fminnm. */
|
|
|
|
case 798: return NULL; /* fminnm --> NULL. */
|
|
|
|
case 748: value = 749; break; /* fccmp --> fccmp. */
|
|
|
|
case 749: return NULL; /* fccmp --> NULL. */
|
|
|
|
case 750: value = 751; break; /* fccmpe --> fccmpe. */
|
|
|
|
case 751: return NULL; /* fccmpe --> NULL. */
|
|
|
|
case 811: value = 812; break; /* fcsel --> fcsel. */
|
|
|
|
case 812: return NULL; /* fcsel --> NULL. */
|
2015-12-14 18:22:36 +01:00
|
|
|
case 130: value = 365; break; /* movi --> sshr. */
|
|
|
|
case 365: value = 367; break; /* sshr --> srshr. */
|
|
|
|
case 367: return NULL; /* srshr --> NULL. */
|
2015-12-14 18:40:03 +01:00
|
|
|
case 138: value = 387; break; /* mvni --> ushr. */
|
|
|
|
case 387: value = 389; break; /* ushr --> urshr. */
|
|
|
|
case 389: value = 391; break; /* urshr --> sri. */
|
|
|
|
case 391: value = 393; break; /* sri --> sqshlu. */
|
|
|
|
case 393: return NULL; /* sqshlu --> NULL. */
|
2015-12-14 18:22:36 +01:00
|
|
|
case 131: value = 366; break; /* orr --> ssra. */
|
|
|
|
case 366: value = 368; break; /* ssra --> srsra. */
|
|
|
|
case 368: value = 369; break; /* srsra --> shl. */
|
|
|
|
case 369: value = 370; break; /* shl --> sqshl. */
|
|
|
|
case 370: return NULL; /* sqshl --> NULL. */
|
2015-12-14 18:40:03 +01:00
|
|
|
case 139: value = 388; break; /* bic --> usra. */
|
|
|
|
case 388: value = 390; break; /* usra --> ursra. */
|
|
|
|
case 390: value = 392; break; /* ursra --> sli. */
|
|
|
|
case 392: value = 394; break; /* sli --> uqshl. */
|
|
|
|
case 394: return NULL; /* uqshl --> NULL. */
|
|
|
|
case 801: value = 802; break; /* fmadd --> fmadd. */
|
|
|
|
case 802: return NULL; /* fmadd --> NULL. */
|
|
|
|
case 805: value = 806; break; /* fnmadd --> fnmadd. */
|
|
|
|
case 806: return NULL; /* fnmadd --> NULL. */
|
2015-12-14 18:22:36 +01:00
|
|
|
case 132: value = 371; break; /* movi --> shrn. */
|
|
|
|
case 371: value = 372; break; /* shrn --> shrn2. */
|
|
|
|
case 372: value = 379; break; /* shrn2 --> sshll. */
|
|
|
|
case 379: value = 381; break; /* sshll --> sshll2. */
|
|
|
|
case 381: return NULL; /* sshll2 --> NULL. */
|
2015-12-14 18:40:03 +01:00
|
|
|
case 140: value = 395; break; /* mvni --> sqshrun. */
|
|
|
|
case 395: value = 396; break; /* sqshrun --> sqshrun2. */
|
|
|
|
case 396: value = 403; break; /* sqshrun2 --> ushll. */
|
|
|
|
case 403: value = 405; break; /* ushll --> ushll2. */
|
|
|
|
case 405: return NULL; /* ushll2 --> NULL. */
|
2015-12-14 18:22:36 +01:00
|
|
|
case 133: value = 375; break; /* orr --> sqshrn. */
|
|
|
|
case 375: value = 376; break; /* sqshrn --> sqshrn2. */
|
|
|
|
case 376: return NULL; /* sqshrn2 --> NULL. */
|
2015-12-14 18:40:03 +01:00
|
|
|
case 141: value = 399; break; /* bic --> uqshrn. */
|
|
|
|
case 399: value = 400; break; /* uqshrn --> uqshrn2. */
|
|
|
|
case 400: return NULL; /* uqshrn2 --> NULL. */
|
2015-12-14 18:22:36 +01:00
|
|
|
case 135: value = 383; break; /* movi --> scvtf. */
|
2015-12-14 18:40:03 +01:00
|
|
|
case 383: value = 384; break; /* scvtf --> scvtf. */
|
|
|
|
case 384: return NULL; /* scvtf --> NULL. */
|
2015-12-14 18:22:36 +01:00
|
|
|
case 143: value = 144; break; /* movi --> movi. */
|
2015-12-14 18:40:03 +01:00
|
|
|
case 144: value = 407; break; /* movi --> ucvtf. */
|
|
|
|
case 407: value = 408; break; /* ucvtf --> ucvtf. */
|
|
|
|
case 408: return NULL; /* ucvtf --> NULL. */
|
|
|
|
case 137: value = 385; break; /* fmov --> fcvtzs. */
|
|
|
|
case 385: value = 386; break; /* fcvtzs --> fcvtzs. */
|
|
|
|
case 386: return NULL; /* fcvtzs --> NULL. */
|
|
|
|
case 409: value = 410; break; /* fcvtzu --> fcvtzu. */
|
|
|
|
case 410: return NULL; /* fcvtzu --> NULL. */
|
|
|
|
case 803: value = 804; break; /* fmsub --> fmsub. */
|
|
|
|
case 804: return NULL; /* fmsub --> NULL. */
|
|
|
|
case 807: value = 808; break; /* fnmsub --> fnmsub. */
|
|
|
|
case 808: return NULL; /* fnmsub --> NULL. */
|
2012-08-13 16:52:54 +02:00
|
|
|
default: return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return aarch64_opcode_table + value;
|
|
|
|
}
|
|
|
|
|
|
|
|
const aarch64_opcode *
|
|
|
|
aarch64_find_alias_opcode (const aarch64_opcode *opcode)
|
|
|
|
{
|
|
|
|
/* Use the index as the key to locate the alias opcode. */
|
|
|
|
int key = opcode - aarch64_opcode_table;
|
|
|
|
int value;
|
|
|
|
switch (key)
|
|
|
|
{
|
|
|
|
case 2: value = 3; break; /* sbc --> ngc. */
|
|
|
|
case 4: value = 5; break; /* sbcs --> ngcs. */
|
|
|
|
case 7: value = 8; break; /* adds --> cmn. */
|
|
|
|
case 10: value = 11; break; /* subs --> cmp. */
|
|
|
|
case 12: value = 13; break; /* add --> mov. */
|
|
|
|
case 14: value = 15; break; /* adds --> cmn. */
|
|
|
|
case 17: value = 18; break; /* subs --> cmp. */
|
|
|
|
case 20: value = 21; break; /* adds --> cmn. */
|
|
|
|
case 22: value = 23; break; /* sub --> neg. */
|
|
|
|
case 24: value = 26; break; /* subs --> negs. */
|
2015-12-14 18:22:36 +01:00
|
|
|
case 149: value = 150; break; /* umov --> mov. */
|
|
|
|
case 151: value = 152; break; /* ins --> mov. */
|
|
|
|
case 153: value = 154; break; /* ins --> mov. */
|
|
|
|
case 235: value = 236; break; /* not --> mvn. */
|
|
|
|
case 310: value = 311; break; /* orr --> mov. */
|
|
|
|
case 379: value = 380; break; /* sshll --> sxtl. */
|
|
|
|
case 381: value = 382; break; /* sshll2 --> sxtl2. */
|
2015-12-14 18:40:03 +01:00
|
|
|
case 403: value = 404; break; /* ushll --> uxtl. */
|
|
|
|
case 405: value = 406; break; /* ushll2 --> uxtl2. */
|
|
|
|
case 526: value = 527; break; /* dup --> mov. */
|
|
|
|
case 605: value = 610; break; /* sbfm --> sxtw. */
|
|
|
|
case 612: value = 614; break; /* bfm --> bfc. */
|
|
|
|
case 616: value = 620; break; /* ubfm --> uxth. */
|
|
|
|
case 638: value = 640; break; /* csinc --> cset. */
|
|
|
|
case 641: value = 643; break; /* csinv --> csetm. */
|
|
|
|
case 644: value = 645; break; /* csneg --> cneg. */
|
|
|
|
case 663: value = 663; break; /* rev --> rev. */
|
|
|
|
case 670: value = 671; break; /* lslv --> lsl. */
|
|
|
|
case 672: value = 673; break; /* lsrv --> lsr. */
|
|
|
|
case 674: value = 675; break; /* asrv --> asr. */
|
|
|
|
case 676: value = 677; break; /* rorv --> ror. */
|
|
|
|
case 686: value = 687; break; /* madd --> mul. */
|
|
|
|
case 688: value = 689; break; /* msub --> mneg. */
|
|
|
|
case 690: value = 691; break; /* smaddl --> smull. */
|
|
|
|
case 692: value = 693; break; /* smsubl --> smnegl. */
|
|
|
|
case 695: value = 696; break; /* umaddl --> umull. */
|
|
|
|
case 697: value = 698; break; /* umsubl --> umnegl. */
|
|
|
|
case 708: value = 709; break; /* extr --> ror. */
|
|
|
|
case 915: value = 916; break; /* and --> bic. */
|
|
|
|
case 917: value = 918; break; /* orr --> mov. */
|
|
|
|
case 920: value = 921; break; /* ands --> tst. */
|
|
|
|
case 924: value = 926; break; /* orr --> uxtw. */
|
|
|
|
case 927: value = 928; break; /* orn --> mvn. */
|
|
|
|
case 931: value = 932; break; /* ands --> tst. */
|
|
|
|
case 962: value = 1058; break; /* ldaddb --> staddb. */
|
|
|
|
case 963: value = 1059; break; /* ldaddh --> staddh. */
|
|
|
|
case 964: value = 1060; break; /* ldadd --> stadd. */
|
|
|
|
case 966: value = 1061; break; /* ldaddlb --> staddlb. */
|
|
|
|
case 969: value = 1062; break; /* ldaddlh --> staddlh. */
|
|
|
|
case 972: value = 1063; break; /* ldaddl --> staddl. */
|
|
|
|
case 974: value = 1064; break; /* ldclrb --> stclrb. */
|
|
|
|
case 975: value = 1065; break; /* ldclrh --> stclrh. */
|
|
|
|
case 976: value = 1066; break; /* ldclr --> stclr. */
|
|
|
|
case 978: value = 1067; break; /* ldclrlb --> stclrlb. */
|
|
|
|
case 981: value = 1068; break; /* ldclrlh --> stclrlh. */
|
|
|
|
case 984: value = 1069; break; /* ldclrl --> stclrl. */
|
|
|
|
case 986: value = 1070; break; /* ldeorb --> steorb. */
|
|
|
|
case 987: value = 1071; break; /* ldeorh --> steorh. */
|
|
|
|
case 988: value = 1072; break; /* ldeor --> steor. */
|
|
|
|
case 990: value = 1073; break; /* ldeorlb --> steorlb. */
|
|
|
|
case 993: value = 1074; break; /* ldeorlh --> steorlh. */
|
|
|
|
case 996: value = 1075; break; /* ldeorl --> steorl. */
|
|
|
|
case 998: value = 1076; break; /* ldsetb --> stsetb. */
|
|
|
|
case 999: value = 1077; break; /* ldseth --> stseth. */
|
|
|
|
case 1000: value = 1078; break; /* ldset --> stset. */
|
|
|
|
case 1002: value = 1079; break; /* ldsetlb --> stsetlb. */
|
|
|
|
case 1005: value = 1080; break; /* ldsetlh --> stsetlh. */
|
|
|
|
case 1008: value = 1081; break; /* ldsetl --> stsetl. */
|
|
|
|
case 1010: value = 1082; break; /* ldsmaxb --> stsmaxb. */
|
|
|
|
case 1011: value = 1083; break; /* ldsmaxh --> stsmaxh. */
|
|
|
|
case 1012: value = 1084; break; /* ldsmax --> stsmax. */
|
|
|
|
case 1014: value = 1085; break; /* ldsmaxlb --> stsmaxlb. */
|
|
|
|
case 1017: value = 1086; break; /* ldsmaxlh --> stsmaxlh. */
|
|
|
|
case 1020: value = 1087; break; /* ldsmaxl --> stsmaxl. */
|
|
|
|
case 1022: value = 1088; break; /* ldsminb --> stsminb. */
|
|
|
|
case 1023: value = 1089; break; /* ldsminh --> stsminh. */
|
|
|
|
case 1024: value = 1090; break; /* ldsmin --> stsmin. */
|
|
|
|
case 1026: value = 1091; break; /* ldsminlb --> stsminlb. */
|
|
|
|
case 1029: value = 1092; break; /* ldsminlh --> stsminlh. */
|
|
|
|
case 1032: value = 1093; break; /* ldsminl --> stsminl. */
|
|
|
|
case 1034: value = 1094; break; /* ldumaxb --> stumaxb. */
|
|
|
|
case 1035: value = 1095; break; /* ldumaxh --> stumaxh. */
|
|
|
|
case 1036: value = 1096; break; /* ldumax --> stumax. */
|
|
|
|
case 1038: value = 1097; break; /* ldumaxlb --> stumaxlb. */
|
|
|
|
case 1041: value = 1098; break; /* ldumaxlh --> stumaxlh. */
|
|
|
|
case 1044: value = 1099; break; /* ldumaxl --> stumaxl. */
|
|
|
|
case 1046: value = 1100; break; /* lduminb --> stuminb. */
|
|
|
|
case 1047: value = 1101; break; /* lduminh --> stuminh. */
|
|
|
|
case 1048: value = 1102; break; /* ldumin --> stumin. */
|
|
|
|
case 1050: value = 1103; break; /* lduminlb --> stuminlb. */
|
|
|
|
case 1053: value = 1104; break; /* lduminlh --> stuminlh. */
|
|
|
|
case 1056: value = 1105; break; /* lduminl --> stuminl. */
|
|
|
|
case 1106: value = 1107; break; /* movn --> mov. */
|
|
|
|
case 1108: value = 1109; break; /* movz --> mov. */
|
|
|
|
case 1114: value = 1122; break; /* hint --> psb. */
|
|
|
|
case 1127: value = 1131; break; /* sys --> tlbi. */
|
2012-08-13 16:52:54 +02:00
|
|
|
default: return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return aarch64_opcode_table + value;
|
|
|
|
}
|
|
|
|
|
|
|
|
const aarch64_opcode *
|
|
|
|
aarch64_find_next_alias_opcode (const aarch64_opcode *opcode)
|
|
|
|
{
|
|
|
|
/* Use the index as the key to locate the next opcode. */
|
|
|
|
int key = opcode - aarch64_opcode_table;
|
|
|
|
int value;
|
|
|
|
switch (key)
|
|
|
|
{
|
2015-11-27 16:02:26 +01:00
|
|
|
case 3: value = 2; break; /* ngc --> sbc. */
|
|
|
|
case 5: value = 4; break; /* ngcs --> sbcs. */
|
|
|
|
case 8: value = 7; break; /* cmn --> adds. */
|
|
|
|
case 11: value = 10; break; /* cmp --> subs. */
|
|
|
|
case 13: value = 12; break; /* mov --> add. */
|
|
|
|
case 15: value = 14; break; /* cmn --> adds. */
|
|
|
|
case 18: value = 17; break; /* cmp --> subs. */
|
|
|
|
case 21: value = 20; break; /* cmn --> adds. */
|
|
|
|
case 23: value = 22; break; /* neg --> sub. */
|
2012-08-13 16:52:54 +02:00
|
|
|
case 26: value = 25; break; /* negs --> cmp. */
|
2015-11-27 16:02:26 +01:00
|
|
|
case 25: value = 24; break; /* cmp --> subs. */
|
2015-12-14 18:22:36 +01:00
|
|
|
case 150: value = 149; break; /* mov --> umov. */
|
|
|
|
case 152: value = 151; break; /* mov --> ins. */
|
|
|
|
case 154: value = 153; break; /* mov --> ins. */
|
|
|
|
case 236: value = 235; break; /* mvn --> not. */
|
|
|
|
case 311: value = 310; break; /* mov --> orr. */
|
|
|
|
case 380: value = 379; break; /* sxtl --> sshll. */
|
|
|
|
case 382: value = 381; break; /* sxtl2 --> sshll2. */
|
2015-12-14 18:40:03 +01:00
|
|
|
case 404: value = 403; break; /* uxtl --> ushll. */
|
|
|
|
case 406: value = 405; break; /* uxtl2 --> ushll2. */
|
|
|
|
case 527: value = 526; break; /* mov --> dup. */
|
|
|
|
case 610: value = 609; break; /* sxtw --> sxth. */
|
|
|
|
case 609: value = 608; break; /* sxth --> sxtb. */
|
|
|
|
case 608: value = 611; break; /* sxtb --> asr. */
|
|
|
|
case 611: value = 607; break; /* asr --> sbfx. */
|
|
|
|
case 607: value = 606; break; /* sbfx --> sbfiz. */
|
|
|
|
case 606: value = 605; break; /* sbfiz --> sbfm. */
|
|
|
|
case 614: value = 615; break; /* bfc --> bfxil. */
|
|
|
|
case 615: value = 613; break; /* bfxil --> bfi. */
|
|
|
|
case 613: value = 612; break; /* bfi --> bfm. */
|
|
|
|
case 620: value = 619; break; /* uxth --> uxtb. */
|
|
|
|
case 619: value = 622; break; /* uxtb --> lsr. */
|
|
|
|
case 622: value = 621; break; /* lsr --> lsl. */
|
|
|
|
case 621: value = 618; break; /* lsl --> ubfx. */
|
|
|
|
case 618: value = 617; break; /* ubfx --> ubfiz. */
|
|
|
|
case 617: value = 616; break; /* ubfiz --> ubfm. */
|
|
|
|
case 640: value = 639; break; /* cset --> cinc. */
|
|
|
|
case 639: value = 638; break; /* cinc --> csinc. */
|
|
|
|
case 643: value = 642; break; /* csetm --> cinv. */
|
|
|
|
case 642: value = 641; break; /* cinv --> csinv. */
|
|
|
|
case 645: value = 644; break; /* cneg --> csneg. */
|
|
|
|
case 663: value = 664; break; /* rev --> rev64. */
|
|
|
|
case 671: value = 670; break; /* lsl --> lslv. */
|
|
|
|
case 673: value = 672; break; /* lsr --> lsrv. */
|
|
|
|
case 675: value = 674; break; /* asr --> asrv. */
|
|
|
|
case 677: value = 676; break; /* ror --> rorv. */
|
|
|
|
case 687: value = 686; break; /* mul --> madd. */
|
|
|
|
case 689: value = 688; break; /* mneg --> msub. */
|
|
|
|
case 691: value = 690; break; /* smull --> smaddl. */
|
|
|
|
case 693: value = 692; break; /* smnegl --> smsubl. */
|
|
|
|
case 696: value = 695; break; /* umull --> umaddl. */
|
|
|
|
case 698: value = 697; break; /* umnegl --> umsubl. */
|
|
|
|
case 709: value = 708; break; /* ror --> extr. */
|
|
|
|
case 916: value = 915; break; /* bic --> and. */
|
|
|
|
case 918: value = 917; break; /* mov --> orr. */
|
|
|
|
case 921: value = 920; break; /* tst --> ands. */
|
|
|
|
case 926: value = 925; break; /* uxtw --> mov. */
|
|
|
|
case 925: value = 924; break; /* mov --> orr. */
|
|
|
|
case 928: value = 927; break; /* mvn --> orn. */
|
|
|
|
case 932: value = 931; break; /* tst --> ands. */
|
|
|
|
case 1058: value = 962; break; /* staddb --> ldaddb. */
|
|
|
|
case 1059: value = 963; break; /* staddh --> ldaddh. */
|
|
|
|
case 1060: value = 964; break; /* stadd --> ldadd. */
|
|
|
|
case 1061: value = 966; break; /* staddlb --> ldaddlb. */
|
|
|
|
case 1062: value = 969; break; /* staddlh --> ldaddlh. */
|
|
|
|
case 1063: value = 972; break; /* staddl --> ldaddl. */
|
|
|
|
case 1064: value = 974; break; /* stclrb --> ldclrb. */
|
|
|
|
case 1065: value = 975; break; /* stclrh --> ldclrh. */
|
|
|
|
case 1066: value = 976; break; /* stclr --> ldclr. */
|
|
|
|
case 1067: value = 978; break; /* stclrlb --> ldclrlb. */
|
|
|
|
case 1068: value = 981; break; /* stclrlh --> ldclrlh. */
|
|
|
|
case 1069: value = 984; break; /* stclrl --> ldclrl. */
|
|
|
|
case 1070: value = 986; break; /* steorb --> ldeorb. */
|
|
|
|
case 1071: value = 987; break; /* steorh --> ldeorh. */
|
|
|
|
case 1072: value = 988; break; /* steor --> ldeor. */
|
|
|
|
case 1073: value = 990; break; /* steorlb --> ldeorlb. */
|
|
|
|
case 1074: value = 993; break; /* steorlh --> ldeorlh. */
|
|
|
|
case 1075: value = 996; break; /* steorl --> ldeorl. */
|
|
|
|
case 1076: value = 998; break; /* stsetb --> ldsetb. */
|
|
|
|
case 1077: value = 999; break; /* stseth --> ldseth. */
|
|
|
|
case 1078: value = 1000; break; /* stset --> ldset. */
|
|
|
|
case 1079: value = 1002; break; /* stsetlb --> ldsetlb. */
|
|
|
|
case 1080: value = 1005; break; /* stsetlh --> ldsetlh. */
|
|
|
|
case 1081: value = 1008; break; /* stsetl --> ldsetl. */
|
|
|
|
case 1082: value = 1010; break; /* stsmaxb --> ldsmaxb. */
|
|
|
|
case 1083: value = 1011; break; /* stsmaxh --> ldsmaxh. */
|
|
|
|
case 1084: value = 1012; break; /* stsmax --> ldsmax. */
|
|
|
|
case 1085: value = 1014; break; /* stsmaxlb --> ldsmaxlb. */
|
|
|
|
case 1086: value = 1017; break; /* stsmaxlh --> ldsmaxlh. */
|
|
|
|
case 1087: value = 1020; break; /* stsmaxl --> ldsmaxl. */
|
|
|
|
case 1088: value = 1022; break; /* stsminb --> ldsminb. */
|
|
|
|
case 1089: value = 1023; break; /* stsminh --> ldsminh. */
|
|
|
|
case 1090: value = 1024; break; /* stsmin --> ldsmin. */
|
|
|
|
case 1091: value = 1026; break; /* stsminlb --> ldsminlb. */
|
|
|
|
case 1092: value = 1029; break; /* stsminlh --> ldsminlh. */
|
|
|
|
case 1093: value = 1032; break; /* stsminl --> ldsminl. */
|
|
|
|
case 1094: value = 1034; break; /* stumaxb --> ldumaxb. */
|
|
|
|
case 1095: value = 1035; break; /* stumaxh --> ldumaxh. */
|
|
|
|
case 1096: value = 1036; break; /* stumax --> ldumax. */
|
|
|
|
case 1097: value = 1038; break; /* stumaxlb --> ldumaxlb. */
|
|
|
|
case 1098: value = 1041; break; /* stumaxlh --> ldumaxlh. */
|
|
|
|
case 1099: value = 1044; break; /* stumaxl --> ldumaxl. */
|
|
|
|
case 1100: value = 1046; break; /* stuminb --> lduminb. */
|
|
|
|
case 1101: value = 1047; break; /* stuminh --> lduminh. */
|
|
|
|
case 1102: value = 1048; break; /* stumin --> ldumin. */
|
|
|
|
case 1103: value = 1050; break; /* stuminlb --> lduminlb. */
|
|
|
|
case 1104: value = 1053; break; /* stuminlh --> lduminlh. */
|
|
|
|
case 1105: value = 1056; break; /* stuminl --> lduminl. */
|
|
|
|
case 1107: value = 1106; break; /* mov --> movn. */
|
|
|
|
case 1109: value = 1108; break; /* mov --> movz. */
|
|
|
|
case 1122: value = 1121; break; /* psb --> esb. */
|
|
|
|
case 1121: value = 1120; break; /* esb --> sevl. */
|
|
|
|
case 1120: value = 1119; break; /* sevl --> sev. */
|
|
|
|
case 1119: value = 1118; break; /* sev --> wfi. */
|
|
|
|
case 1118: value = 1117; break; /* wfi --> wfe. */
|
|
|
|
case 1117: value = 1116; break; /* wfe --> yield. */
|
|
|
|
case 1116: value = 1115; break; /* yield --> nop. */
|
|
|
|
case 1115: value = 1114; break; /* nop --> hint. */
|
|
|
|
case 1131: value = 1130; break; /* tlbi --> ic. */
|
|
|
|
case 1130: value = 1129; break; /* ic --> dc. */
|
|
|
|
case 1129: value = 1128; break; /* dc --> at. */
|
|
|
|
case 1128: value = 1127; break; /* at --> sys. */
|
2012-08-13 16:52:54 +02:00
|
|
|
default: return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return aarch64_opcode_table + value;
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
aarch64_extract_operand (const aarch64_operand *self,
|
|
|
|
aarch64_opnd_info *info,
|
|
|
|
aarch64_insn code, const aarch64_inst *inst)
|
|
|
|
{
|
|
|
|
/* Use the index as the key. */
|
|
|
|
int key = self - aarch64_operands;
|
|
|
|
switch (key)
|
|
|
|
{
|
|
|
|
case 1:
|
|
|
|
case 2:
|
|
|
|
case 3:
|
|
|
|
case 4:
|
|
|
|
case 5:
|
|
|
|
case 6:
|
|
|
|
case 7:
|
|
|
|
case 9:
|
|
|
|
case 10:
|
|
|
|
case 14:
|
|
|
|
case 15:
|
|
|
|
case 16:
|
2014-09-03 15:40:41 +02:00
|
|
|
case 17:
|
2012-08-13 16:52:54 +02:00
|
|
|
case 19:
|
|
|
|
case 20:
|
|
|
|
case 21:
|
|
|
|
case 22:
|
|
|
|
case 23:
|
|
|
|
case 24:
|
|
|
|
case 25:
|
|
|
|
case 26:
|
2014-09-03 15:40:41 +02:00
|
|
|
case 27:
|
2012-08-13 16:52:54 +02:00
|
|
|
case 35:
|
2014-09-03 15:40:41 +02:00
|
|
|
case 36:
|
2012-08-13 16:52:54 +02:00
|
|
|
return aarch64_ext_regno (self, info, code, inst);
|
|
|
|
case 8:
|
|
|
|
return aarch64_ext_regrt_sysins (self, info, code, inst);
|
|
|
|
case 11:
|
2014-09-03 15:40:41 +02:00
|
|
|
return aarch64_ext_regno_pair (self, info, code, inst);
|
2012-08-13 16:52:54 +02:00
|
|
|
case 12:
|
2014-09-03 15:40:41 +02:00
|
|
|
return aarch64_ext_reg_extended (self, info, code, inst);
|
|
|
|
case 13:
|
2012-08-13 16:52:54 +02:00
|
|
|
return aarch64_ext_reg_shifted (self, info, code, inst);
|
2014-09-03 15:40:41 +02:00
|
|
|
case 18:
|
2012-08-13 16:52:54 +02:00
|
|
|
return aarch64_ext_ft (self, info, code, inst);
|
|
|
|
case 28:
|
|
|
|
case 29:
|
|
|
|
case 30:
|
2014-09-03 15:40:41 +02:00
|
|
|
return aarch64_ext_reglane (self, info, code, inst);
|
2012-08-13 16:52:54 +02:00
|
|
|
case 31:
|
2014-09-03 15:40:41 +02:00
|
|
|
return aarch64_ext_reglist (self, info, code, inst);
|
2012-08-13 16:52:54 +02:00
|
|
|
case 32:
|
2014-09-03 15:40:41 +02:00
|
|
|
return aarch64_ext_ldst_reglist (self, info, code, inst);
|
2012-08-13 16:52:54 +02:00
|
|
|
case 33:
|
2014-09-03 15:40:41 +02:00
|
|
|
return aarch64_ext_ldst_reglist_r (self, info, code, inst);
|
|
|
|
case 34:
|
2012-08-13 16:52:54 +02:00
|
|
|
return aarch64_ext_ldst_elemlist (self, info, code, inst);
|
2014-09-03 15:40:41 +02:00
|
|
|
case 37:
|
2012-08-13 16:52:54 +02:00
|
|
|
case 46:
|
|
|
|
case 47:
|
|
|
|
case 48:
|
|
|
|
case 49:
|
|
|
|
case 50:
|
|
|
|
case 51:
|
|
|
|
case 52:
|
|
|
|
case 53:
|
|
|
|
case 54:
|
|
|
|
case 55:
|
|
|
|
case 56:
|
|
|
|
case 57:
|
2014-09-03 15:40:41 +02:00
|
|
|
case 58:
|
2012-08-13 16:52:54 +02:00
|
|
|
case 66:
|
|
|
|
case 67:
|
|
|
|
case 68:
|
2013-11-05 21:50:18 +01:00
|
|
|
case 69:
|
2014-09-03 15:40:41 +02:00
|
|
|
case 70:
|
2012-08-13 16:52:54 +02:00
|
|
|
return aarch64_ext_imm (self, info, code, inst);
|
|
|
|
case 38:
|
|
|
|
case 39:
|
2014-09-03 15:40:41 +02:00
|
|
|
return aarch64_ext_advsimd_imm_shift (self, info, code, inst);
|
2012-08-13 16:52:54 +02:00
|
|
|
case 40:
|
|
|
|
case 41:
|
|
|
|
case 42:
|
2014-09-03 15:40:41 +02:00
|
|
|
return aarch64_ext_advsimd_imm_modified (self, info, code, inst);
|
|
|
|
case 43:
|
2012-08-13 16:52:54 +02:00
|
|
|
return aarch64_ext_shll_imm (self, info, code, inst);
|
|
|
|
case 59:
|
2014-09-03 15:40:41 +02:00
|
|
|
return aarch64_ext_limm (self, info, code, inst);
|
2012-08-13 16:52:54 +02:00
|
|
|
case 60:
|
2014-09-03 15:40:41 +02:00
|
|
|
return aarch64_ext_aimm (self, info, code, inst);
|
2012-08-13 16:52:54 +02:00
|
|
|
case 61:
|
2014-09-03 15:40:41 +02:00
|
|
|
return aarch64_ext_imm_half (self, info, code, inst);
|
|
|
|
case 62:
|
2012-08-13 16:52:54 +02:00
|
|
|
return aarch64_ext_fbits (self, info, code, inst);
|
2013-11-05 21:50:18 +01:00
|
|
|
case 64:
|
2014-09-03 15:40:41 +02:00
|
|
|
case 65:
|
2012-08-13 16:52:54 +02:00
|
|
|
return aarch64_ext_cond (self, info, code, inst);
|
|
|
|
case 71:
|
2014-09-03 15:40:41 +02:00
|
|
|
case 77:
|
|
|
|
return aarch64_ext_addr_simple (self, info, code, inst);
|
2012-08-13 16:52:54 +02:00
|
|
|
case 72:
|
2014-09-03 15:40:41 +02:00
|
|
|
return aarch64_ext_addr_regoff (self, info, code, inst);
|
2012-08-13 16:52:54 +02:00
|
|
|
case 73:
|
|
|
|
case 74:
|
2013-11-05 21:50:18 +01:00
|
|
|
case 75:
|
2014-09-03 15:40:41 +02:00
|
|
|
return aarch64_ext_addr_simm (self, info, code, inst);
|
|
|
|
case 76:
|
2012-08-13 16:52:54 +02:00
|
|
|
return aarch64_ext_addr_uimm12 (self, info, code, inst);
|
|
|
|
case 78:
|
2014-09-03 15:40:41 +02:00
|
|
|
return aarch64_ext_simd_addr_post (self, info, code, inst);
|
2012-08-13 16:52:54 +02:00
|
|
|
case 79:
|
2014-09-03 15:40:41 +02:00
|
|
|
return aarch64_ext_sysreg (self, info, code, inst);
|
2012-08-13 16:52:54 +02:00
|
|
|
case 80:
|
2014-09-03 15:40:41 +02:00
|
|
|
return aarch64_ext_pstatefield (self, info, code, inst);
|
2012-08-13 16:52:54 +02:00
|
|
|
case 81:
|
|
|
|
case 82:
|
|
|
|
case 83:
|
|
|
|
case 84:
|
2014-09-03 15:40:41 +02:00
|
|
|
return aarch64_ext_sysins_op (self, info, code, inst);
|
2012-08-13 16:52:54 +02:00
|
|
|
case 85:
|
2013-11-05 21:50:18 +01:00
|
|
|
case 86:
|
2014-09-03 15:40:41 +02:00
|
|
|
return aarch64_ext_barrier (self, info, code, inst);
|
|
|
|
case 87:
|
2012-08-13 16:52:54 +02:00
|
|
|
return aarch64_ext_prfop (self, info, code, inst);
|
2015-12-11 11:22:40 +01:00
|
|
|
case 88:
|
|
|
|
return aarch64_ext_hint (self, info, code, inst);
|
2012-08-13 16:52:54 +02:00
|
|
|
default: assert (0); abort ();
|
|
|
|
}
|
|
|
|
}
|