This commit applies all changes made after running the gdb/copyright.py
script.
Note that one file was flagged by the script, due to an invalid
copyright header
(gdb/unittests/basic_string_view/element_access/char/empty.cc).
As the file was copied from GCC's libstdc++-v3 testsuite, this commit
leaves this file untouched for the time being; a patch to fix the header
was sent to gcc-patches first.
gdb/ChangeLog:
Update copyright year range in all GDB files.
The following will segfault on aarch64 if foo is in another object,
was compiled as c++ and has no debug symbols:
(gdb) p (int)foo()
This is because aarch64_push_dummy_call determines the return type
of the function and then does not check for null pointer.
A null pointer for the return type means the call has no debug
information. For the code to get here, then the call must have
been cast, otherwise we'd error out sooner. In the case of a
no-debug-info call cast, the return type is the type the user
had cast the call to, but we do not have that information
available here.
However, aarch64_push_dummy_call only requires the return type in
order to calculate lang_struct_return. This information is available
in the return_method enum. The fix is to simply use this instead.
Adds testcase to check calls across objects, with all combinations
of c, c++, debug and no debug.
gdb/ChangeLog:
PR gdb/22736:
* aarch64-tdep.c (aarch64_push_dummy_call): Remove
lang_struct_return code.
gdb/testsuite/ChangeLog:
PR gdb/22736:
* gdb.cp/infcall-nodebug-lib.c: New test.
* gdb.cp/infcall-nodebug-main.c: New test.
* gdb.cp/infcall-nodebug.exp: New file.
Consider the gdb.ada/array_return.exp testcase, and in particular,
consider the following code...
type Small_Float_Vector is array (1 .. 2) of Float;
function Create_Small_Float_Vector return Small_Float_Vector is
begin
return (others => 4.25);
end Create_Small_Float_Vector;
... which declares a type which is an array with 2 floats in it
(floats are 4 bytes on AArch64), trying to get GDB to print
the return value from that function does not work:
(gdb) fin
Run till exit from #0 pck.create_small_float_vector () at /[...]/pck.adb:15
0x000000000000062c in p () at /[...]/p.adb:11
11 Vector := Create_Small_Float_Vector;
Value returned is $1 = (4.25, 0.0)
^^^
|||
We expected the value shown to be:
(gdb) fin
Run till exit from #0 pck.create_small_float_vector () at /[...]/pck.adb:15
0x000000000000062c in p () at /[...]/p.adb:11
11 Vector := Create_Small_Float_Vector;
Value returned is $1 = (4.25, 4.25)
Because the return type is an HFA, it is returned via the first two
SIMD registers. However, what happens is that the current implementation
fails to realize that this is an HFA, and therefore fetches the return
value from the wrong location. And the reason why it fails to realize
this is because it thinks that our array has 8 elements (HFAs have
a maximum of 4). Looking at aapcs_is_vfp_call_or_return_candidate_1,
where this is determined, we can easily see why (looks like a thinko):
| case TYPE_CODE_ARRAY:
| [...]
| struct type *target_type = TYPE_TARGET_TYPE (type);
| int count = aapcs_is_vfp_call_or_return_candidate_1
| (target_type, fundamental_type);
|
| if (count == -1)
| return count;
|
!! -> | count *= TYPE_LENGTH (type);
| return count;
Here, we first determine the count for one element of our array,
and so we should then be multiplying that count by the number
of elements in our array (2 in our case). But instead, we multiply it
by the total size (8). As a result, we do not classify the return
type as an HFA, and thus pick the wrong location for fetching
the return value.
gdb/ChangeLog:
* aarch64-tdep.c (aapcs_is_vfp_call_or_return_candidate_1):
return the correct count for potential HFAs.
Tested on aarch64-linux, fixes:
array_return.exp: value printed by finish of Create_Small_Float_Vector
This patch adds support for debugging Ravenscar tasks, similar to what
is done for ppc and sparc.
gdb/ChangeLog:
* aarch64-ravenscar-thread.h, aarch64-ravenscar-thread.c:
New files.
* aarch64-tdep.c: #include "aarch64-ravenscar-thread.h".
(aarch64_gdbarch_init): Add call to register_aarch64_ravenscar_ops.
* Makefile.in (ALL_64_TARGET_OBS): Add aarch64-ravenscar-thread.o.
(HFILES_NO_SRCDIR): Add aarch64-ravenscar-thread.h.
(ALLDEPFILES): Add aarch64-ravenscar-thread.c.
* configure.tgt (cpu_obs) [aarch64*-*-*]: Add ravenscar-thread.o
and aarch64-ravenscar-thread.o.
* NEWS: Add entry documenting Ravenscar tasking support
on AArch64 ELF.
Using "call" on a function that passes arguments via float registers can cause
gdb to overflow buffers.
Ensure enough memory is reserved to hold a full FP register.
This fixes gdb.base/callfuncs.exp for Aarch64 SVE.
2018-09-18 Alan Hayward <alan.hayward@arm.com>
* aarch64-tdep.c (pass_in_v): Use register size.
(aarch64_extract_return_value): Likewise.
(aarch64_store_return_value): Likewise.
Use aapcs_is_vfp_call_or_return_candidate to detect float register
args, then pass in registers if there is room.
gdb/
* aarch64-tdep.c
(aapcs_is_vfp_call_or_return_candidate): Make static
(pass_in_v_or_stack): Remove function.
(pass_in_v_vfp_candidate): New function.
(aarch64_push_dummy_call): Check for float register candidates.
aapcs_is_vfp_call_or_return_candidate is as an eventual replacement
for is_hfa_or_hva.
This function is based on the GCC code
gcc/config/aarch64/aarch64.c:aarch64_vfp_is_call_or_return_candidate ()
gdb/
* aarch64-tdep.c (HA_MAX_NUM_FLDS): New macro.
(aapcs_is_vfp_call_or_return_candidate_1): New function.
(aapcs_is_vfp_call_or_return_candidate): Likewise.
Code like this:
CORE_ADDR breaks[2] = {-1, -1};
... gives a warning with -Wnarrowing. This patch changes all
instances of this to use CORE_ADDR_MAX instead.
gdb/ChangeLog
2018-08-27 Tom Tromey <tom@tromey.com>
* rs6000-tdep.c (ppc_deal_with_atomic_sequence): Use
CORE_ADDR_MAX.
* mips-tdep.c (mips_deal_with_atomic_sequence)
(micromips_deal_with_atomic_sequence): Use CORE_ADDR_MAX.
* arch/arm-get-next-pcs.c (thumb_deal_with_atomic_sequence_raw)
(arm_deal_with_atomic_sequence_raw): Use CORE_ADDR_MAX.
* alpha-tdep.c (alpha_deal_with_atomic_sequence): Use
CORE_ADDR_MAX.
* aarch64-tdep.c (aarch64_software_single_step): Use
CORE_ADDR_MAX.
tdesc_register_size returns number of bits, not bytes.
Rename to make it clearer.
Also, fixed bug in aarch64_get_tdesc_vq which assumed bytes.
gdb/
* target-descriptions.c (tdesc_register_bitsize): Rename.
* target-descriptions.h (tdesc_register_bitsize): Likewise.
* rs6000-tdep.c (rs6000_gdbarch_init): Use new name.
* aarch64-tdep.c (aarch64_get_tdesc_vq): Convert size.
This is as per the spec:
https://developer.arm.com/products/architecture/a-profile/docs/100985/0000
gdb/
* aarch64-tdep.c (aarch64_dwarf_reg_to_regnum): Add mappings.
* aarch64-tdep.h (AARCH64_DWARF_SVE_VG): Add define.
(AARCH64_DWARF_SVE_FFR): Likewise.
(AARCH64_DWARF_SVE_P0): Likewise.
(AARCH64_DWARF_SVE_Z0): Likewise.
Add the functionality for reading/writing pseudo registers.
On SVE the V registers are pseudo registers. This is supported
by adding AARCH64_SVE_V0_REGNUM.
* aarch64-tdep.c (AARCH64_SVE_V0_REGNUM): Add define.
(aarch64_vnv_type): Add function.
(aarch64_pseudo_register_name): Add V regs for SVE.
(aarch64_pseudo_register_type): Likewise.
(aarch64_pseudo_register_reggroup_p): Likewise.
(aarch64_pseudo_read_value_2): Use V0 offset for SVE
(aarch64_pseudo_read_value): Add V regs for SVE.
(aarch64_pseudo_write_2): Use V0 offset for SVE
(aarch64_pseudo_write): Add V regs for SVE.
* aarch64-tdep.h (struct gdbarch_tdep): Add vnv_type.
Reduce code copy/paste by adding two helper functions for
aarch64_pseudo_read_value and aarch64_pseudo_write
Does not change any functionality.
gdb/
* aarch64-tdep.c (aarch64_pseudo_read_value_1): New helper func.
(aarch64_pseudo_write_1): Likewise.
(aarch64_pseudo_read_value): Use helper.
(aarch64_pseudo_write): Likewise.
Enable SVE support for GDB by reading the VQ when creating a
target description.
Also ensurse that SVE is taken into account when creating
the tdep structure, and store the current VQ value directly in tdep.
gdb/
* aarch64-linux-nat.c (aarch64_linux_read_description): Support SVE.
* aarch64-tdep.c (aarch64_get_tdesc_vq): New function.
(aarch64_gdbarch_init): Check for SVE.
* aarch64-tdep.h (gdbarch_tdep::has_sve): New function.
Previously VQ was of type long. Using uint64_t ensures it always matches the
same type as the VG register.
Note that in the Linux kernel, VQ is 16bits. We cast it up to 64bits
immediately after reading to ensure we always use the same type throughout
the code.
gdb/
* aarch64-tdep.c (aarch64_read_description): Use uint64_t for VQ.
* aarch64-tdep.h (aarch64_read_description): Likewise.
* arch/aarch64.c (aarch64_create_target_description): Likewise.
* arch/aarch64.h (aarch64_create_target_description): Likewise.
* features/aarch64-sve.c (create_feature_aarch64_sve): Likewise.
* nat/aarch64-sve-linux-ptrace.c(aarch64_sve_get_vq): Likewise.
* nat/aarch64-sve-linux-ptrace.h (aarch64_sve_get_vq): Likewise.
In order to prevent gaps in the register numbering, the Z registers
reuse the V register numbers (which become pseudos on SVE).
2018-06-01 Alan Hayward <alan.hayward@arm.com>
* aarch64-tdep.c (aarch64_sve_register_names): New const
var.
* arch/aarch64.h (enum aarch64_regnum): Add SVE entries.
(AARCH64_SVE_Z_REGS_NUM): New define.
(AARCH64_SVE_P_REGS_NUM): Likewise.
(AARCH64_SVE_NUM_REGS): Likewise.
Remove regcache_raw_write, update all callers to use regcache::raw_write
instead.
gdb/ChangeLog:
* regcache.h (regcache_raw_write): Remove, update callers to use
regcache::raw_write instead.
* regcache.c (regcache_raw_write): Remove.
This patch if the first patch in a series to add the ability to add constraints
to system registers that an instruction must adhere to in order for the register
to be usable with that instruction.
These constraints can also be used to disambiguate between registers with the
same encoding during disassembly.
This patch adds a new flags entry in the sysreg structures and ensures it is
filled in and read out during assembly/disassembly. It also adds the ability for
the assemble and disassemble functions to be able to gracefully fail and re-use
the existing error reporting infrastructure.
The return type of these functions are changed to a boolean to denote success or
failure and the error structure is passed around to them. This requires
aarch64-gen changes so a lot of the changes here are just mechanical.
gas/
PR binutils/21446
* config/tc-aarch64.c (parse_sys_reg): Return register flags.
(parse_operands): Fill in register flags.
gdb/
PR binutils/21446
* aarch64-tdep.c (aarch64_analyze_prologue,
aarch64_software_single_step, aarch64_displaced_step_copy_insn):
Indicate not interested in errors.
include/
PR binutils/21446
* opcode/aarch64.h (aarch64_opnd_info): Change sysreg to struct.
(aarch64_decode_insn): Accept error struct.
opcodes/
PR binutils/21446
* aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
and take error struct.
* aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
aarch64_ins_reglist, aarch64_ins_ldst_reglist,
aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
* aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
* aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
aarch64_ext_reglist, aarch64_ext_ldst_reglist,
aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
(determine_disassembling_preference, aarch64_decode_insn,
print_insn_aarch64_word, print_insn_data): Take errors struct.
(print_insn_aarch64): Use errors.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-gen.c (print_operand_inserter): Use errors and change type to
boolean in aarch64_insert_operan.
(print_operand_extractor): Likewise.
* aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
This patch fixes tagged pointer support for AArch64 GDB. Linux kernel
debugging failure was reported after tagged pointer support was committed.
After a discussion around best path forward to manage tagged pointers
on GDB side we are going to disable tagged pointers support for
aarch64-none-elf-gdb because for non-linux applications we cant be
sure if tagged pointers will be used by MMU or not.
Also for aarch64-linux-gdb we are going to sign extend user-space
address after clearing tag bits. This will help debug both kernel
and user-space addresses based on information from linux kernel
documentation given below:
According to AArch64 memory map:
https://www.kernel.org/doc/Documentation/arm64/memory.txt
"User addresses have bits 63:48 set to 0 while the kernel addresses have
the same bits set to 1."
According to AArch64 tagged pointers document:
https://www.kernel.org/doc/Documentation/arm64/tagged-pointers.txt
The kernel configures the translation tables so that translations made
via TTBR0 (i.e. userspace mappings) have the top byte (bits 63:56) of
the virtual address ignored by the translation hardware. This frees up
this byte for application use.
Running gdb testsuite after applying this patch introduces no regressions
and tagged pointer test cases still pass.
gdb/ChangeLog:
2018-05-10 Omair Javaid <omair.javaid@linaro.org>
PR gdb/23127
* aarch64-linux-tdep.c (aarch64_linux_init_abi): Add call to
set_gdbarch_significant_addr_bit.
* aarch64-tdep.c (aarch64_gdbarch_init): Remove call to
set_gdbarch_significant_addr_bit.
* utils.c (address_significant): Update to sign extend addr.
I noticed the existence of -Wsuggest-override and so this patch
enables it for gdb. It found a few spots that could use "override".
Also I went ahead and removed all uses of the "OVERRIDE" macro.
Using override is beneficial because it makes it harder to change a
base class and then forget to change a derived class.
Tested by the buildbot.
ChangeLog
2018-04-27 Tom Tromey <tom@tromey.com>
* configure: Rebuild.
* warning.m4 (AM_GDB_WARNINGS): Add -Wsuggest-override.
* dwarf2loc.c (class dwarf_evaluate_loc_desc): Use "override", not
"OVERRIDE".
(class symbol_needs_eval_context): Likewise.
* dwarf2read.c (mock_mapped_index::symbol_name_count)
(mock_mapped_index::symbol_name_at): Use "override". Remove
"virtual".
* dwarf2-frame.c (dwarf_expr_executor::get_addr_index): Use
"override".
(class dwarf_expr_executor): Use "override", not "OVERRIDE".
* aarch64-tdep.c (instruction_reader::read): Use "override".
(instruction_reader_test::read): Likewise.
* arm-tdep.c (instruction_reader::read): Use "override".
(instruction_reader_thumb::read): Likewise.
gdbserver/ChangeLog
2018-04-27 Tom Tromey <tom@tromey.com>
* configure: Rebuild.
pseudo registers are either from raw registers or memory, so
gdbarch methods pseudo_register_read and pseudo_register_read_value
should have regcache object which only have read methods. In other
words, we should disallow writing to regcache in these two gdbarch
methods. In order to apply this restriction, this patch adds a new
class readable_regcache, derived from reg_buffer, and it only has
raw_read and cooked_read methods. regcache is derived from
readable_regcache. This patch also passes readable_regcache instead of
regcache to gdbarch methods pseudo_register_read and
pseudo_register_read_value.
This patch moves raw_read* and cooked_read* methods to readable_regcache,
which is straightforward. One thing not straightforward is that I split
regcache::xfer_part to readable_regcache::read_part and regcache::write_part,
because readable_regcache can only have methods to read.
readable_regcache is an abstract base class, and it has a pure virtual
function raw_update, because I don't want readable_regcache know where
these raw registers are from. They can be from either the target
(readwrite regcache) or the regcache itself (readonly regcache).
gdb:
2018-02-21 Yao Qi <yao.qi@linaro.org>
* aarch64-tdep.c (aarch64_pseudo_register_read_value): Change
parameter type to 'readable_regcache *'.
* amd64-tdep.c (amd64_pseudo_register_read_value): Likewise.
* arm-tdep.c (arm_neon_quad_read): Likewise.
(arm_pseudo_read): Likewise.
* avr-tdep.c (avr_pseudo_register_read): Likewise.
* bfin-tdep.c (bfin_pseudo_register_read): Likewise.
* frv-tdep.c (frv_pseudo_register_read): Likewise.
* gdbarch.c: Re-generated.
* gdbarch.h: Re-generated.
* gdbarch.sh (pseudo_register_read): Change parameter type to
'readable_regcache *'.
(pseudo_register_read_value): Likewise.
* h8300-tdep.c (pseudo_from_raw_register): Likewise.
(h8300_pseudo_register_read): Likewise.
* hppa-tdep.c (hppa_pseudo_register_read): Likewise.
* i386-tdep.c (i386_mmx_regnum_to_fp_regnum): Likewise.
(i386_pseudo_register_read_into_value): Likewise.
(i386_pseudo_register_read_value): Likewise.
* i386-tdep.h (i386_pseudo_register_read_into_value): Update
declaration.
* ia64-tdep.c (ia64_pseudo_register_read): Likewise.
* m32c-tdep.c (m32c_raw_read): Likewise.
(m32c_read_flg): Likewise.
(m32c_banked_register): Likewise.
(m32c_banked_read): Likewise.
(m32c_sb_read): Likewise.
(m32c_part_read): Likewise.
(m32c_cat_read): Likewise.
(m32c_r3r2r1r0_read): Likewise.
(m32c_pseudo_register_read): Likewise.
* m68hc11-tdep.c (m68hc11_pseudo_register_read): Likewise.
* mep-tdep.c (mep_pseudo_cr32_read): Likewise.
(mep_pseudo_cr64_read): Likewise.
(mep_pseudo_register_read): Likewise.
* mips-tdep.c (mips_pseudo_register_read): Likewise.
* msp430-tdep.c (msp430_pseudo_register_read): Likewise.
* nds32-tdep.c (nds32_pseudo_register_read): Likewise.
* regcache.c (regcache::raw_read): Move it to readable_regcache.
(regcache::cooked_read): Likewise.
(regcache::cooked_read_value): Likewise.
(regcache_cooked_read_signed):
(regcache::cooked_read): Likewise.
* regcache.h (readable_regcache): New class.
(regcache): Inherit readable_regcache. Move some methods to
readable_regcache.
* rl78-tdep.c (rl78_pseudo_register_read): Change
parameter type to 'readable_regcache *'.
* rs6000-tdep.c (do_regcache_raw_read): Remove.
(e500_pseudo_register_read): Change parameter type to
'readable_regcache *'.
(dfp_pseudo_register_read): Likewise.
(vsx_pseudo_register_read): Likewise.
(efpr_pseudo_register_read): Likewise.
* s390-tdep.c (s390_pseudo_register_read): Likewise.
* sh-tdep.c (sh_pseudo_register_read): Likewise.
* sh64-tdep.c (pseudo_register_read_portions): Likewise.
(sh64_pseudo_register_read): Likewise.
* sparc-tdep.c (sparc32_pseudo_register_read): Likewise.
* sparc64-tdep.c (sparc64_pseudo_register_read): Likewise.
* spu-tdep.c (spu_pseudo_register_read_spu): Likewise.
(spu_pseudo_register_read): Likewise.
* xtensa-tdep.c (xtensa_register_read_masked): Likewise.
(xtensa_pseudo_register_read): Likewise.
The patch later in this series will move regcache's raw_read and
cooked_read methods to a new class regcache_read, and regcache is
dervied from it. Also pass regcache_read instead of regcache to gdbarch
methods pseudo_register_read and pseudo_register_read_value. In order
to prepare for this change, this patch changes regcache_raw_read to
regcache->raw_read. On the other hand, since we are in C++, I prefer
using class method (regcache->raw_read).
gdb:
2018-01-22 Yao Qi <yao.qi@linaro.org>
* aarch64-tdep.c (aarch64_pseudo_read_value): Call regcache
method raw_read instead of regcache_raw_read.
* amd64-tdep.c (amd64_pseudo_register_read_value): Likewise.
* arm-tdep.c (arm_neon_quad_read): Likewise.
* avr-tdep.c (avr_pseudo_register_read): Likewise.
* bfin-tdep.c (bfin_pseudo_register_read): Likewise.
* frv-tdep.c (frv_pseudo_register_read): Likewise.
* h8300-tdep.c (h8300_pseudo_register_read): Likewise.
* i386-tdep.c (i386_mmx_regnum_to_fp_regnum): Likewise.
(i386_pseudo_register_read_into_value): Likewise.
* mep-tdep.c (mep_pseudo_cr32_read): Likewise.
* msp430-tdep.c (msp430_pseudo_register_read): Likewise.
* nds32-tdep.c (nds32_pseudo_register_read): Likewise.
* rl78-tdep.c (rl78_pseudo_register_read): Likewise.
* s390-linux-tdep.c (s390_pseudo_register_read): Likewise.
* sparc-tdep.c (sparc32_pseudo_register_read): Likewise.
* sparc64-tdep.c (sparc64_pseudo_register_read): Likewise.
* spu-tdep.c (spu_pseudo_register_read_spu): Likewise.
* xtensa-tdep.c (xtensa_pseudo_register_read): Likewise.
ARMv8 supports tagged address, that is, the top one byte in address
is ignored. It is always enabled on aarch64-linux. See
https://www.kernel.org/doc/Documentation/arm64/tagged-pointers.txt
The tag in the tagged address is modeled as non-significant bits in
address, so this patch adds a new gdbarch method significant_addr_bit and
clear the non-significant bits (the top byte in ARMv8) of the virtual
address at the point before passing address to target cache layer. IOW,
the address used in the target cache layer is already cleared.
Before this patch,
(gdb) x/x 0x0000000000411030
0x411030 <global>: 0x00000000
(gdb) x/x 0xf000000000411030
0xf000000000411030: Cannot access memory at address 0xf000000000411030
After this patch,
(gdb) x/x 0x0000000000411030
0x411030 <global>: 0x00000000
(gdb) x/x 0xf000000000411030
0xf000000000411030: 0x00000000
Note that I used address_significant in paddress, but it causes a
regression gdb.base/long_long.exp, because gdb clears the non-significant
bits in address, but test still expects them.
p/a val.oct^M
$24 = 0x2ee53977053977^M
(gdb) FAIL: gdb.base/long_long.exp: p/a val.oct
so I defer the change there.
gdb:
2017-12-08 Yao Qi <yao.qi@linaro.org>
* aarch64-tdep.c (aarch64_gdbarch_init): Install gdbarch
significant_addr_bit.
* gdbarch.sh (significant_addr_bit): New.
* gdbarch.c, gdbarch.h: Re-generated.
* target.c (memory_xfer_partial): Call address_significant.
* utils.c (address_significant): New function.
* utils.h (address_significant): Declare.
2017-12-08 Yao Qi <yao.qi@linaro.org>
gdb/testsuite:
* gdb.arch/aarch64-tagged-pointer.c: New file.
* gdb.arch/aarch64-tagged-pointer.exp: New file.
displaced_step_closure is a type defined in multiple -tdep.c files.
Trying to xfree it from the common code (infrun.c) is a problem when we
try to poison xfree for non-POD types. Because there can be multiple of
these types in the same build, this patch makes a hierarchy of classes
with a virtual destructor. When the common code deletes the object
through a displaced_step_closure pointer, it will invoke the right
destructor.
The amd64 used a last-member array with a variable size. That doesn't
work with new, so I changed it for an std::vector. Other architectures
which used a simple byte buffer as a closure now use a shared
buf_displaced_step_closure, a closure type that only contains a
gdb::byte_vector.
Reg-tested on the buildbot.
gdb/ChangeLog:
* infrun.h: Include common/byte-vector.h.
(struct displaced_step_closure): New struct.
(struct buf_displaced_step_closure): New struct.
* infrun.c (displaced_step_closure::~displaced_step_closure):
Provide default implementation.
(displaced_step_clear): Deallocate step closure with delete.
* aarch64-tdep.c (displaced_step_closure): Rename to ...
(aarch64_displaced_step_closure): ... this, extend
displaced_step_closure.
(aarch64_displaced_step_data) <dsc>: Change type to
aarch64_displaced_step_closure.
(aarch64_displaced_step_copy_insn): Adjust to type change, use
unique_ptr.
(aarch64_displaced_step_fixup): Add cast for displaced step
closure.
* amd64-tdep.c (displaced_step_closure): Rename to ...
(amd64_displaced_step_closure): ... this, extend
displaced_step_closure.
<insn_buf>: Change type to std::vector<gdb_byte>.
<max_len>: Remove.
(fixup_riprel): Change type of DSC parameter, adjust to type
change of insn_buf.
(fixup_displaced_copy): Change type of DSC parameter.
(amd64_displaced_step_copy_insn): Instantiate
amd64_displaced_step_closure.
(amd64_displaced_step_fixup): Add cast for closure type, adjust
to type change of insn_buf.
* arm-linux-tdep.c (arm_linux_cleanup_svc): Change type of
parameter DSC.
(arm_linux_copy_svc): Likewise.
(cleanup_kernel_helper_return): Likewise.
(arm_catch_kernel_helper_return): Likewise.
(arm_linux_displaced_step_copy_insn): Instantiate
arm_displaced_step_closure.
* arm-tdep.c (arm_pc_is_thumb): Add cast for closure.
(displaced_read_reg): Change type of parameter DSC.
(branch_write_pc): Likewise.
(load_write_pc): Likewise.
(alu_write_pc): Likewise.
(displaced_write_reg): Likewise.
(arm_copy_unmodified): Likewise.
(thumb_copy_unmodified_32bit): Likewise.
(thumb_copy_unmodified_16bit): Likewise.
(cleanup_preload): Likewise.
(install_preload): Likewise.
(arm_copy_preload): Likewise.
(thumb2_copy_preload): Likewise.
(install_preload_reg): Likewise.
(arm_copy_preload_reg): Likewise.
(cleanup_copro_load_store): Likewise.
(install_copro_load_store): Likewise.
(arm_copy_copro_load_store) Likewise.
(thumb2_copy_copro_load_store): Likewise.
(cleanup_branch): Likewise.
(install_b_bl_blx): Likewise.
(arm_copy_b_bl_blx): Likewise.
(thumb2_copy_b_bl_blx): Likewise.
(thumb_copy_b): Likewise.
(install_bx_blx_reg): Likewise.
(arm_copy_bx_blx_reg): Likewise.
(thumb_copy_bx_blx_reg): Likewise.
(cleanup_alu_imm): Likewise.
(arm_copy_alu_imm): Likewise.
(thumb2_copy_alu_imm): Likewise.
(cleanup_alu_reg): Likewise.
(install_alu_reg): Likewise.
(arm_copy_alu_reg): Likewise.
(thumb_copy_alu_reg): Likewise.
(cleanup_alu_shifted_reg): Likewise.
(install_alu_shifted_reg): Likewise.
(arm_copy_alu_shifted_reg): Likewise.
(cleanup_load): Likewise.
(cleanup_store): Likewise.
(arm_copy_extra_ld_st): Likewise.
(install_load_store): Likewise.
(thumb2_copy_load_literal): Likewise.
(thumb2_copy_load_reg_imm): Likewise.
(arm_copy_ldr_str_ldrb_strb): Likewise.
(cleanup_block_load_all): Likewise.
(cleanup_block_store_pc): Likewise.
(cleanup_block_load_pc): Likewise.
(arm_copy_block_xfer): Likewise.
(thumb2_copy_block_xfer): Likewise.
(cleanup_svc): Likewise.
(install_svc): Likewise.
(arm_copy_svc): Likewise.
(thumb_copy_svc): Likewise.
(arm_copy_undef): Likewise.
(thumb_32bit_copy_undef): Likewise.
(arm_copy_unpred): Likewise.
(arm_decode_misc_memhint_neon): Likewise.
(arm_decode_unconditional): Likewise.
(arm_decode_miscellaneous): Likewise.
(arm_decode_dp_misc): Likewise.
(arm_decode_ld_st_word_ubyte): Likewise.
(arm_decode_media): Likewise.
(arm_decode_b_bl_ldmstm): Likewise.
(arm_decode_ext_reg_ld_st): Likewise.
(thumb2_decode_dp_shift_reg): Likewise.
(thumb2_decode_ext_reg_ld_st): Likewise.
(arm_decode_svc_copro): Likewise.
(thumb2_decode_svc_copro): Likewise.
(install_pc_relative): Likewise.
(thumb_copy_pc_relative_16bit): Likewise.
(thumb_decode_pc_relative_16bit): Likewise.
(thumb_copy_pc_relative_32bit): Likewise.
(thumb_copy_16bit_ldr_literal): Likewise.
(thumb_copy_cbnz_cbz): Likewise.
(thumb2_copy_table_branch): Likewise.
(cleanup_pop_pc_16bit_all): Likewise.
(thumb_copy_pop_pc_16bit): Likewise.
(thumb_process_displaced_16bit_insn): Likewise.
(decode_thumb_32bit_ld_mem_hints): Likewise.
(thumb_process_displaced_32bit_insn): Likewise.
(thumb_process_displaced_insn): Likewise.
(arm_process_displaced_insn): Likewise.
(arm_displaced_init_closure): Likewise.
(arm_displaced_step_fixup): Add cast for closure.
* arm-tdep.h: Include infrun.h.
(displaced_step_closure): Rename to ...
(arm_displaced_step_closure): ... this, extend
displaced_step_closure.
<u::svc::copy_svc_os>: Change type of parameter DSC.
<cleanup>: Likewise.
(arm_process_displaced_insn): Likewise.
(arm_displaced_init_closure): Likewise.
(displaced_read_reg): Likewise.
(displaced_write_reg): Likewise.
* i386-linux-tdep.c (i386_linux_displaced_step_copy_insn):
Adjust.
* i386-tdep.h: Include infrun.h.
(i386_displaced_step_closure): New typedef.
* i386-tdep.c (i386_displaced_step_copy_insn): Use
i386_displaced_step_closure.
(i386_displaced_step_fixup): Adjust.
* rs6000-tdep.c (ppc_displaced_step_closure): New typedef.
(ppc_displaced_step_copy_insn): Use ppc_displaced_step_closure
and unique_ptr.
(ppc_displaced_step_fixup): Adjust.
* s390-linux-tdep.c (s390_displaced_step_closure): New typedef.
(s390_displaced_step_copy_insn): Use s390_displaced_step_closure
and unique_ptr.
(s390_displaced_step_fixup): Adjust.
This patch is an initial C++-ification of pv_area, from
prologue-value. It turns pv_area into a class with a constructor and
destructor; renames the data members; and changes various functions to
be member functions. This allows the removal of
make_cleanup_free_pv_area.
gdb/ChangeLog
2017-10-12 Tom Tromey <tom@tromey.com>
* s390-linux-tdep.c (s390_store, s390_load)
(s390_check_for_saved, s390_analyze_prologue): Update.
* rx-tdep.c (check_for_saved, rx_analyze_prologue): Update.
* rl78-tdep.c (rl78_analyze_prologue, check_for_saved): Update.
* prologue-value.h (class pv_area): Move from prologue-value.c.
Change names of members. Add constructor, destructor, member
functions.
(make_pv_area, free_pv_area, make_cleanup_free_pv_area)
(pv_area_store, pv_area_fetch, pv_area_store_would_trash)
(pv_area_fetch, pv_area_scan): Don't declare.
* prologue-value.c (struct pv_area::area_entry): Now member of
pv_area.
(struct pv_area): Move to prologue-value.h.
(pv_area::pv_area): Rename from make_pv_area.
(pv_area::~pv_area): Rename from free_pv_area.
(do_free_pv_area_cleanup, make_cleanup_free_pv_area): Remove.
(clear_entries, find_entry, overlaps, store_would_trash, store)
(fetch, find_reg, scan): Now member of pv_area.
Remove "area" argument. Update.
* msp430-tdep.c (check_for_saved, msp430_analyze_prologue):
Update.
* mn10300-tdep.c (push_reg, check_for_saved)
(mn10300_analyze_prologue): Update.
* mep-tdep.c (is_arg_spill, check_for_saved)
(mep_analyze_prologue): Update.
* m32c-tdep.c (m32c_pv_push, m32c_srcdest_fetch)
(m32c_srcdest_store, m32c_pv_enter, m32c_is_arg_spill)
(m32c_is_struct_return, m32c_analyze_prologue): Update.
* arm-tdep.c (thumb_analyze_prologue, arm_analyze_prologue):
Update.
* arc-tdep.c (arc_is_in_prologue, arc_analyze_prologue): Update.
* aarch64-tdep.c (aarch64_analyze_prologue): Update.
As a first small step to getting rid of doublest.h, this patch removes the
include of "floatformat.h" in "doublest.h". This is actually not needed
for the file itself. A few source files now need to include "floatformat.h"
directly, since they got it indirectly via "doublest.h" and still need it.
In reviewing which files need it, I found a number of files that include
"floatformat.h" directly without actually needing it at all. Similarly,
a number of files include "doublest.h" without needing it. I've also
removed those unnecessary include statements.
gdb/ChangeLog:
2017-10-05 Ulrich Weigand <uweigand@de.ibm.com>
* doublest.h: Do not include "floatformat.h". Remove stale comments.
* gdbtypes.c: Include "floatformat.h".
* value.c: Likewise.
* m68k-tdep.c: Likewise.
* findvar.c: Do not include "floatformat.h".
* amd64-darwin-tdep.c: Likewise.
* arm-linux-tdep.c: Likewise.
* i386-darwin-tdep.c: Likewise.
* i387-tdep.c: Likewise.
* m68k-linux-tdep.c: Likewise.
* mep-tdep.c: Likewise.
* mips-tdep.c: Likewise.
* nios2-tdep.c: Likewise.
* s390-linux-tdep.c: Likewise.
* sparc-obsd-tdep.c: Likewise.
* sparc-tdep.c: Likewise.
* sparc64-tdep.c: Likewise.
* spu-tdep.c: Likewise.
* tic6x-tdep.c: Likewise.
* tilegx-tdep.c: Likewise.
* vax-tdep.c: Likewise.
* xstormy16-tdep.c: Likewise.
* xtensa-tdep.c: Likewise.
* top.c: Do not include "doublest.h".
* aarch64-tdep.c: Likewise.
* alpha-tdep.c: Likewise.
* arm-linux-tdep.c: Likewise.
* m68k-linux-tdep.c: Likewise.
* tilegx-tdep.c: Likewise.
* xstormy16-tdep.c: Likewise.
With the growing number of selftests, I think it would be useful to be
able to run only a subset of the tests. This patch associates a name to
each registered selftest. It then allows doing something like:
(gdb) maintenance selftest aarch64
Running self-tests.
Running selftest aarch64-analyze-prologue.
Running selftest aarch64-process-record.
Ran 2 unit tests, 0 failed
or with gdbserver:
./gdbserver --selftest=aarch64
In both cases, only the tests that contain "aarch64" in their name are
ran. To help validate that the tests you want to run were actually ran,
it also prints a message with the test name before running each test.
Right now, all the arch-dependent tests are registered as a single test
of the selftests. To be able to filter those too, I made them
"first-class citizen" selftests. The selftest type is an interface,
with different implementations for "simple selftests" and "arch
selftests". The run_tests function simply iterates on that an invokes
operator() on each test.
I changed the tests data structure from a vector to a map, because
- it allows iterating in a stable (alphabetical) order
- it allows to easily verify if a test with a given name has been
registered, to avoid duplicates
There's also a new command "maintenance info selftests" that lists the
registered selftests.
gdb/ChangeLog:
* common/selftest.h (selftest): New struct/interface.
(register_test): Add name parameter, add new overload.
(run_tests): Add filter parameter.
(for_each_selftest_ftype): New typedef.
(for_each_selftest): New declaration.
* common/selftest.c (tests): Change type to
map<string, unique_ptr<selftest>>.
(simple_selftest): New struct.
(register_test): New function.
(register_test): Add name parameter and use it.
(run_tests): Add filter parameter and use it. Add prints.
Adjust to vector -> map change.
* aarch64-tdep.c (_initialize_aarch64_tdep): Add names when
registering selftests.
* arm-tdep.c (_initialize_arm_tdep): Likewise.
* disasm-selftests.c (_initialize_disasm_selftests): Likewise.
* dwarf2-frame.c (_initialize_dwarf2_frame): Likewise.
* dwarf2loc.c (_initialize_dwarf2loc): Likewise.
* findvar.c (_initialize_findvar): Likewise.
* gdbarch-selftests.c (_initialize_gdbarch_selftests): Likewise.
* maint.c (maintenance_selftest): Update call to run_tests.
(maintenance_info_selftests): New function.
(_initialize_maint_cmds): Register "maintenance info selftests"
command. Update "maintenance selftest" doc.
* regcache.c (_initialize_regcache): Add names when registering
selftests.
* rust-exp.y (_initialize_rust_exp): Likewise.
* selftest-arch.c (gdbarch_selftest): New struct.
(gdbarch_tests): Remove.
(register_test_foreach_arch): Add name parameter. Call
register_test.
(tests_with_arch): Remove, move most content to
gdbarch_selftest::operator().
(_initialize_selftests_foreach_arch): Remove.
* selftest-arch.h (register_test_foreach_arch): Add name
parameter.
(run_tests_with_arch): New declaration.
* utils-selftests.c (_initialize_utils_selftests): Add names
when registering selftests.
* utils.c (_initialize_utils): Likewise.
* unittests/array-view-selftests.c
(_initialize_array_view_selftests): Likewise.
* unittests/environ-selftests.c (_initialize_environ_selftests):
Likewise.
* unittests/function-view-selftests.c
(_initialize_function_view_selftests): Likewise.
* unittests/offset-type-selftests.c
(_initialize_offset_type_selftests): Likewise.
* unittests/optional-selftests.c
(_initialize_optional_selftests): Likewise.
* unittests/scoped_restore-selftests.c
(_initialize_scoped_restore_selftests): Likewise.
* NEWS: Document "maintenance selftest" and "maint info
selftests".
gdb/gdbserver/ChangeLog:
* server.c (captured_main): Accept argument for --selftest.
Update run_tests call.
* linux-x86-tdesc-selftest.c (initialize_low_tdesc): Add names
when registering selftests.
gdb/doc/ChangeLog:
* gdb.texinfo (Maintenance Commands): Document filter parameter
of "maint selftest". Document "maint info selftests" command.
As an update to commit ede5f15146 ("gdbarch.h: Change
gdbarch_info::tdep_info's type to void *") replace the definition of the
`tdep_info' member in `struct gdbarch_info' with an anonymous union,
comprising the original member, with its type reverted to `struct
gdbarch_tdep_info *', a `tdesc_data' member of a `struct tdesc_arch_data
*' type and an `id' member of an `int *' type. Remove now unnecessary
casts throughout use places then, making code easier to read an less
prone to errors, which may happen with casting.
gdb/
* gdbarch.sh (gdbarch_info): Replace the `tdep_info' member with
a union of `tdep_info', `tdesc_data' and `id'.
* aarch64-tdep.c (aarch64_gdbarch_init): Use `info.tdesc_data'
rather than `info.tdep_info'.
* amd64-linux-tdep.c (amd64_linux_init_abi): Likewise.
* i386-linux-tdep.c (i386_linux_init_abi): Likewise.
* i386-tdep.c (i386_gdbarch_init): Likewise.
* mips-linux-tdep.c (mips_linux_init_abi): Likewise.
* mips-tdep.c (mips_gdbarch_init): Likewise.
* nds32-tdep.c (nds32_gdbarch_init): Likewise.
* rs6000-tdep.c (rs6000_gdbarch_init): Likewise.
* ppc-linux-tdep.c (ppu2spu_sniffer): Use `info.id' rather than
`info.tdep_info'.
(ppc_linux_init_abi): Use `info.tdesc_data' rather than
`info.tdep_info'.
* sparc-tdep.c (sparc32_gdbarch_init): Likewise.
* spu-multiarch.c (spu_gdbarch): Use `info.id' rather than
`info.tdep_info'.
* spu-tdep.c (spu_gdbarch_init): Likewise.
* gdbarch.h: Regenerate.
This is a follow-up to
[PATCH 0/6] Unify the disassembler selection in gdb and objdump
https://sourceware.org/ml/binutils/2017-05/msg00192.html
that is, opcodes is able to select the right disassembler, so gdb
doesn't have to select them. Instead, gdb can just use
default_print_insn. As a result, these print_insn_XXX are not used
out of opcodes, so this patch also moves their declarations from
include/dis-asm.h to opcodes/disassemble.h. With this change,
GDB doesn't use any print_insn_XXX directly any more.
gdb:
2017-06-14 Yao Qi <yao.qi@linaro.org>
* aarch64-tdep.c (aarch64_gdb_print_insn): Call
default_print_insn instead of print_insn_aarch64.
* arm-tdep.c (gdb_print_insn_arm): Call
default_print_insn instead of print_insn_big_arm
and print_insn_little_arm.
* i386-tdep.c (i386_print_insn): Call default_print_insn
instead of print_insn_i386.
* ia64-tdep.c (ia64_print_insn): Call
default_print_insn instead of print_insn_ia64.
* mips-tdep.c (gdb_print_insn_mips): Call
default_print_insn instead of print_insn_big_mips
and print_insn_little_mips.
* spu-tdep.c (gdb_print_insn_spu): Call default_print_insn
instead of print_insn_spu.
include:
2017-06-14 Yao Qi <yao.qi@linaro.org>
* dis-asm.h (print_insn_aarch64): Move it to opcodes/disassemble.h.
(print_insn_big_arm, print_insn_big_mips): Likewise.
(print_insn_i386, print_insn_ia64): Likewise.
(print_insn_little_arm, print_insn_little_mips): Likewise.
(print_insn_spu): Likewise.
opcodes:
2017-06-14 Yao Qi <yao.qi@linaro.org>
* aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
* arm-dis.c: Likewise.
* ia64-dis.c: Likewise.
* mips-dis.c: Likewise.
* spu-dis.c: Likewise.
* disassemble.h (print_insn_aarch64): New declaration, moved from
include/dis-asm.h.
(print_insn_big_arm, print_insn_big_mips): Likewise.
(print_insn_i386, print_insn_ia64): Likewise.
(print_insn_little_arm, print_insn_little_mips): Likewise.
The size of wchar_t on AArch64 and ARM is 4-byte, so we can use the
default value (4*TARGET_CHAR_BIT).
This patch fixes some fails in gdb.cp/wide_char_types.exp on
aarch64-linux.
gdb:
2017-04-25 Yao Qi <yao.qi@linaro.org>
* aarch64-tdep.c (aarch64_gdbarch_init): Don't call
set_gdbarch_wchar_bit.
* arm-tdep.c (arm_gdbarch_init): Likewise.
gdb-8.0-branch
./configure --enable-werror --enable-targets=all
aarch64-tdep.c:3045:13: error: ‘void selftests::aarch64_process_record_test()’ declared ‘static’ but never defined [-Werror=unused-function]
arm-tdep.c:9601:13: error: ‘void selftests::arm_record_test()’ declared ‘static’ but never defined [-Werror=unused-function]
gdb/ChangeLog
2017-04-21 Jan Kratochvil <jan.kratochvil@redhat.com>
* aarch64-tdep.c (selftests::aarch64_process_record_test): Make it #if
GDB_SELF_TEST.
* arm-tdep.c (selftests::arm_record_test): Likewise.
GDB is currently not aware that wchar_t is a built-in type in C++
mode. This is usually not a problem because the debug info describes
the type, so when you have a program loaded, you don't notice this.
However, if you try expressions involving wchar_t before a program is
loaded, gdb errors out:
(gdb) p (wchar_t)-1
No symbol table is loaded. Use the "file" command.
(gdb) p L"hello"
No type named wchar_t.
(gdb) ptype L"hello"
No type named wchar_t.
This commit teaches gdb about the type. After:
(gdb) p (wchar_t)-1
$1 = -1 L'\xffffffff'
(gdb) p L"hello"
$2 = L"hello"
(gdb) ptype L"hello"
type = wchar_t [6]
Unlike char16_t/char32_t, unfortunately, the underlying type of
wchar_t is implementation dependent, both size and signness. So this
requires adding a couple new gdbarch hooks.
I grepped the GCC code base for WCHAR_TYPE and WCHAR_TYPE_SIZE, and it
seems to me that the majority of the ABIs have a 4-byte signed
wchar_t, so that's what I made the default for GDB too. And then I
looked for which ports have a 16-bit and/or unsigned wchar_t, and made
GDB follow suit.
gdb/ChangeLog:
2017-04-12 Pedro Alves <palves@redhat.com>
PR gdb/21323
* c-lang.c (cplus_primitive_types) <cplus_primitive_type_wchar_t>:
New enum value.
(cplus_language_arch_info): Register cplus_primitive_type_wchar_t.
* gdbtypes.h (struct builtin_type) <builtin_wchar>: New field.
* gdbtypes.c (gdbtypes_post_init): Create the "wchar_t" type.
* gdbarch.sh (wchar_bit, wchar_signed): New per-arch values.
* gdbarch.h, gdbarch.c: Regenerate.
* aarch64-tdep.c (aarch64_gdbarch_init): Override
gdbarch_wchar_bit and gdbarch_wchar_signed.
* alpha-tdep.c (alpha_gdbarch_init): Likewise.
* arm-tdep.c (arm_gdbarch_init): Likewise.
* avr-tdep.c (avr_gdbarch_init): Likewise.
* h8300-tdep.c (h8300_gdbarch_init): Likewise.
* i386-nto-tdep.c (i386nto_init_abi): Likewise.
* i386-tdep.c (i386_go32_init_abi): Likewise.
* m32r-tdep.c (m32r_gdbarch_init): Likewise.
* moxie-tdep.c (moxie_gdbarch_init): Likewise.
* nds32-tdep.c (nds32_gdbarch_init): Likewise.
* rs6000-aix-tdep.c (rs6000_aix_init_osabi): Likewise.
* sh-tdep.c (sh_gdbarch_init): Likewise.
* sparc-tdep.c (sparc32_gdbarch_init): Likewise.
* sparc64-tdep.c (sparc64_init_abi): Likewise.
* windows-tdep.c (windows_init_abi): Likewise.
* xstormy16-tdep.c (xstormy16_gdbarch_init): Likewise.
gdb/testsuite/ChangeLog:
2017-04-12 Pedro Alves <palves@redhat.com>
PR gdb/21323
* gdb.cp/wide_char_types.c: Include <wchar.h>.
(wchar): New global.
* gdb.cp/wide_char_types.exp (wide_char_types_program)
(do_test_wide_char, wide_char_types_no_program, top level): Add
wchar_t testing.
This patch fixes the bug of handling PRFM instruction. PRFM is documented
in a table with other load and store instructions, but it doesn't do any
load or store. This patch also adds a unit test to PRFM instruction.
gdb:
2017-03-23 Yao Qi <yao.qi@linaro.org>
* aarch64-tdep.c (aarch64_process_record_test): Declare.
(_initialize_aarch64_tdep): Register it.
(aarch64_record_load_store): Handle PRFM instruction.
(aarch64_process_record_test): New function.