95f283e8f6
2008-05-23 H.J. Lu <hongjiu.lu@intel.com>
...
PR gas/6518
* config/tc-i386.c (match_template): Report ambiguous operand
size, not invalid suffix when there is no match in Intel
syntax.
2008-05-23 13:55:36 +00:00
c462b453bd
2008-05-22 Paul Brook <paul@codesourcery.com>
...
gas/
* config/tc-arm.c (parse_cond): Covert to lowercase before matching.
2008-05-22 17:03:55 +00:00
7fac05361c
* config/tc-arm.c (arm_cpus): Add Faraday ARMv4 and ARMv5TE
...
compatible cores: fa526, fa626, fa626te, fa726te.
* doc/c-arm.texi (ARM Opts): Add -mcpu={fa526, fa626, fa626te,
fa726te} options.
2008-05-21 08:20:17 +00:00
35903be00c
gas/
...
* config/tc-mips.c (mips_frob_file): Don't match MIPS16 relocs
with non-MIPS16 relocs.
gas/testsuite/
* gas/mips/mips16-hilo-match.s: New test.
* gas/mips/mip16-hilo-match.d: New test output.Index: config/tc-mips.c
2008-05-09 19:28:47 +00:00
c41e87e39e
* config/tc-mips.c (md_begin): Use strncmp to compare TARGET_OS, in
...
case that some characters append at the end of the name.
(mips_ip): Likewise.
(s_change_sec): Likewise.
(md_section_align): Likewise.
2008-05-09 18:18:22 +00:00
51c8ebc1d0
bfd/
...
* elf32-xtensa.c (xtensa_property_section_name): New.
(xtensa_make_property_section): New.
(xtensa_get_property_section): Make static. Do not create a new
section if it does not exist.
gas/
* config/tc-xtensa.c (xtensa_create_property_segments): Use
xtensa_make_property_section instead of xtensa_get_property_section.
(xtensa_create_xproperty_segments): Likewise.
2008-05-07 23:13:09 +00:00
f1f8f695c0
gas/
...
2008-05-02 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention XSAVE, EPT and MOVBE.
* config/tc-i386.c (cpu_arch): Add .movbe and .ept.
(md_show_usage): Add .movbe and .ept.
* doc/c-i386.texi: Add movbe and ept to -march=. Document
.movbe and .ept.
gas/testsuite/
2008-05-02 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run movbe, movbe-intel, inval-movbe, ept,
ept-intel, inval-ept, x86-64-movbe, x86-64-movbe-intel,
x86-64-inval-movbe. x86-64-ept, x86-64-ept-intel and
x86-64-inval-ept.
* gas/i386/arch-10.s: Add movbe and invept.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/ept.d: New file
* gas/i386/ept-intel.d: Likewise.
* gas/i386/ept.s: Likewise.
* gas/i386/inval-ept.l: Likewise.
* gas/i386/inval-ept.s: Likewise.
* gas/i386/inval-movbe.l: Likewise.
* gas/i386/inval-movbe.s: Likewise.
* gas/i386/movbe.d: Likewise.
* gas/i386/movbe-intel.d: Likewise.
* gas/i386/movbe.s: Likewise.
* gas/i386/x86-64-inval-ept.l: Likewise.
* gas/i386/x86-64-inval-ept.s: Likewise.
* gas/i386/x86-64-inval-movbe.l: Likewise.
* gas/i386/x86-64-inval-movbe.s: Likewise.
* gas/i386/x86-64-ept.d: Likewise.
* gas/i386/x86-64-ept-intel.d: Likewise.
* gas/i386/x86-64-ept.s: Likewise.
* gas/i386/x86-64-movbe.d: Likewise.
* gas/i386/x86-64-movbe-intel.d: Likewise.
* gas/i386/x86-64-movbe.s: Likewise.
* gas/i386/arch-10.d: Updated.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
opcodes/
2008-05-02 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (MOVBE_Fixup): New.
(Mo): Likewise.
(PREFIX_0F3880): Likewise.
(PREFIX_0F3881): Likewise.
(PREFIX_0F38F0): Updated.
(prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
(three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
* i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
CPU_EPT_FLAGS.
(cpu_flags): Add CpuMovbe and CpuEPT.
* i386-opc.h (CpuMovbe): New.
(CpuEPT): Likewise.
(CpuLM): Updated.
(i386_cpu_flags): Add cpumovbe and cpuept.
* i386-opc.tbl: Add entries for movbe and EPT instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2008-05-02 16:53:40 +00:00
2b661f3dc2
* config/tc-sparc.c (v9a_asr_table): Fix order of softint entries.
2008-04-30 03:50:39 +00:00
037b32b9ff
* config/tc-mips.c (file_mips_soft_float, file_mips_single_float):
...
New statics.
(OPTION_ELF_BASE): Make room for new option macros.
(OPTION_SOFT_FLOAT, OPTION_HARD_FLOAT, OPTION_SINGLE_FLOAT,
OPTION_DOUBLE_FLOAT): New option macros.
(md_longopts): Add msoft-float, mhard-float, msingle-float and
mdouble-float.
(md_parse_option): Handle OPTION_SINGLE_FLOAT,
OPTION_DOUBLE_FLOAT, OPTION_SOFT_FLOAT and OPTION_HARD_FLOAT.
(md_show_usage): Add -msoft-float, -mhard-float, -msingle-float
and -mdouble-float.
(struct mips_set_options): New fields soft_float and single_float.
(mips_opts): Initialized them. Add comment for each field
initializer.
(mips_after_parse_args): Set them based on file_mips_soft_float
and file_mips_single_float.
(s_mipsset): Add support for `.set softfloat', `.set hardfloat',
`.set singlefloat' and `.set doublefloat'.
(is_opcode_valid): New function to invoke OPCODE_IS_MEMBER.
Handle single-float and soft-float instructions here.
(macro_build, mips_ip): Use it instead of OPCODE_IS_MEMBER.
(is_opcode_valid_16): New function.
(mips16_ip): Use it instead of OPCODE_IS_MEMBER.
(macro) <M_LDC1_AB, M_SDC1_AB, M_L_DOB, M_L_DAB, M_S_DAB,
M_S_DOB>: Remove special-casing of r4650.
* doc/c-mips.texi (-march=): Add Octeon.
(MIPS Opts): Document -msoft-float and -mhard-float. Document
-msingle-float and -mdouble-float.
(MIPS floating-point): New section. Document `.set softfloat' and
`.set hardfloat'. Document `.set singlefloat' and `.set
doublefloat'.
2008-04-28 17:06:28 +00:00
f04d18b76a
gas/
...
* config/tc-sparc.c: Accept 'softint_clear' and 'softint_set'
%asr aliases.
* doc/c-sparc.texi: Consistently refer to architecture 'versions',
rather than occaisionally 'levels'. Consistently refer to Sun's
UNIX variant as SunOS, every version of Solaris is also SunOS.
Document new 'softint_clear' and 'softint_set' aliases. Clarify
which architecture versions support '%dcr', '%cq', and '%gl'. Add
section on 32-bit/64-bit opcode translations.
opcodes/
* sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
instead of %sys_tick_cmpr, as suggested in architecture manuals.
2008-04-25 19:58:03 +00:00
fe4fa32c96
2008-04-23 Mike Frysinger <vapier@gentoo.org>
...
* Makefile.am (OBJ_FORMAT_CFILES): Add config/obj-fdpicelf.c.
(OBJ_FORMAT_HFILES): Add config/obj-fdpicelf.h.
(obj-fdpicelf.o): Define.
* Makefile.in: Regenerate.
* configure.tgt: Set bfd_gas to yes when fmt is fdpicelf.
(bfin-*-*): Delete.
(bfin-*-linux-uclibc): New; set fmt to fdpicelf and em to linux.
(bfin-*-uclinux*): New; set fmt to elf and em to linux.
* config/obj-fdpicelf.c: New.
* config/obj-fdpicelf.h: Likewise.
* config/tc-bfin.c (bfin_flags, bfin_pic_flag): Set default based on
the OBJ_FDPIC_ELF define.
(OPTION_NOPIC): Define.
(md_longopts): Add mnopic and mno-fdpic.
(md_parse_option): Handle OPTION_NOPIC.
2008-04-23 18:40:34 +00:00
44bf236263
* config/obj-elf.c (obj_elf_section_type): Add prototype
...
before obj_elf_section_word and add 'warn' arg.
(obj_elf_section_word): Add type pointer arg, and if no #SECTION
is matched, try checking for #SECTION_TYPE.
(obj_elf_section): Adjust for new args.
(obj_elf_type_name): New function.
(obj_elf_type): Call it, and accept STT_foo number strings
in .type statements as output by SunPRO compiler.
2008-04-23 13:54:56 +00:00
1a6b486f73
opcodes/
...
* sparc-opc.c (asi_table): Add UltraSPARC and Niagara
extended values.
(prefetch_table): Add missing values.
gas/
* config/tc-sparc.c (v9a_asr_table): Add missing
'stick' and 'stick_cmpr', and document ordering rules
of table.
(tc_gen_reloc): Accept BFD_RELOC_SPARC_PC22 and
BFD_RELOC_SPARC_PC10.
* doc/c-sparc.texi: New section on Sparc constants.
Add documentation for %stick and %stick_cmpr.
gas/testsuite/
* gas/sparc/pc2210.d: New file.
* gas/sparc/pc2210.d: Likewise.
* gas/sparc/sparc.exp: Run new %pc22/%pc10 relocation test.
2008-04-23 07:49:33 +00:00
81f8a9131a
gas/
...
2008-04-22 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (md_assemble): Don't check SSE instructions
if noavx is 0.
opcodes/
2008-04-22 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Add NoAVX.
* i386-opc.h (NoAVX): New.
(OldGcc): Updated.
(i386_opcode_modifier): Add noavx.
* i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
instructions which don't have AVX equivalent.
* i386-tbl.h: Regenerated.
2008-04-22 22:27:13 +00:00
eff014d916
2008-04-18 H.J. Lu <hongjiu.lu@intel.com>
...
* config/tc-i386.c (build_modrm_byte): Don't check FMA to swap
REG and NDS for instructions with immediate operand.
2008-04-18 18:22:37 +00:00
dae39accc2
gas/
...
2008-04-18 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (build_modrm_byte): Swap REG and NDS for
FMA.
gas/testsuite/
2008-04-18 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/arch-10.d: Updated.
* gas/i386/avx.d: Likewise.
* gas/i386/avx-intel.d: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
* gas/i386/x86-64-avx.d: Likewise.
* gas/i386/x86-64-avx-intel.d: Likewise.
opcodes/
2008-04-18 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (OP_VEX_FMA): New.
(OP_EX_VexImmW): Likewise.
(VexFMA): Likewise.
(Vex128FMA): Likewise.
(EXVexImmW): Likewise.
(get_vex_imm8): Likewise.
(OP_EX_VexReg): Likewise.
(vex_i4_done): Renamed to ...
(vex_w_done): This.
(prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
FMA instructions.
(print_insn): Updated.
(OP_EX_VexW): Rewrite to swap register in VEX with EX.
(OP_REG_VexI4): Check invalid high registers.
2008-04-18 13:10:32 +00:00
14865d7608
* config/tc-sparc.c (sparc_ip): Recognize %pc22 and %pc10.
2008-04-18 08:47:35 +00:00
739f7f82be
bfd/
...
* reloc.c (BFD_RELOC_SPARC_GOTDATA_HIX22,
BFD_RELOC_SPARC_GOTDATA_LOX10, BFD_RELOC_SPARC_GOTDATA_OP_HIX22,
BFD_RELOC_SPARC_GOTDATA_OP_LOX10, BFD_RELOC_SPARC_GOTDATA_OP): New.
* libbfd.h: Regnerate.
* bfd-in2.h: Regenerate.
* elfxx-sparc.c (_bfd_sparc_elf_howto_table): Add entries for
GOTDATA relocations.
(sparc_reloc_map): Likewise.
(_bfd_sparc_elf_check_relocs): Handle R_SPARC_GOTDATA_* like
R_SPARC_GOT*.
(_bfd_sparc_elf_gc_sweep_hook): Likewise.
(_bfd_sparc_elf_relocate_section): Transform R_SPARC_GOTDATA_HIX22,
R_SPARC_GOTDATA_LOX10, R_SPARC_GOTDATA_OP_HIX22, and
R_SPARC_GOTDATA_OP_LOX10 into the equivalent R_SPARC_GOT* reloc.
Simply ignore R_SPARC_GOTDATA_OP relocations.
gas/
* config/tc-sparc.c (sparc_ip): Add support for gotdata mnemonics
and relocation generation.
(tc_gen_reloc): Likewise.
gas/testsuite/
* gas/sparc/gotops32.d: New.
* gas/sparc/gotops32.s: Likewise.
* gas/sparc/gotops64.d: Likewise.
* gas/sparc/gotops64.s: Likewise.
* gas/sparc/sparc.exp: Run new gotdata tests.
ld/testsuite/
* ld-sparc/gotop32.dd: New.
* ld-sparc/gotop32.rd: Likewise.
* ld-sparc/gotop32.s: Likewise.
* ld-sparc/gotop32.sd: Likewise.
* ld-sparc/gotop32.td: Likewise.
* ld-sparc/gotop64.dd: Likewise.
* ld-sparc/gotop64.rd: Likewise.
* ld-sparc/gotop64.s: Likewise.
* ld-sparc/gotop64.sd: Likewise.
* ld-sparc/gotop64.td: Likewise.
* ld-sparc/sparc.exp: Run new gotdata tests.
2008-04-16 08:51:18 +00:00
52b5ca5b35
2008-04-15 Andrew Stubbs <andrew.stubbs@st.com>
...
gas/
* config/tc-sh.c (md_apply_fix): Make sure BFD_RELOC_SH_PCRELIMM8BY4
relocations are properly aligned, and not negative.
gas/testsuite/
* gas/sh/arch/arch.exp: Align PC-relative instructions in the gererated
assembly files.
* gas/sh/arch/sh-dsp.s: Regenerate.
* gas/sh/arch/sh.s: Regenerate.
* gas/sh/arch/sh2.s: Regenerate.
* gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s: Regenerate.
* gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s: Regenerate.
* gas/sh/arch/sh2a-nofpu.s: Regenerate.
* gas/sh/arch/sh2a-or-sh3e.s: Regenerate.: Regenerate.
* gas/sh/arch/sh2a-or-sh4.s: Regenerate.
* gas/sh/arch/sh2a.s: Regenerate.
* gas/sh/arch/sh2e.s: Regenerate.
* gas/sh/arch/sh3-dsp.s: Regenerate.
* gas/sh/arch/sh3-nommu.s: Regenerate.
* gas/sh/arch/sh3.s: Regenerate.
* gas/sh/arch/sh3e.s: Regenerate.
* gas/sh/arch/sh4-nofpu.s: Regenerate.
* gas/sh/arch/sh4-nommu-nofpu.s: Regenerate.
* gas/sh/arch/sh4.s: Regenerate.
* gas/sh/arch/sh4a-nofpu.s: Regenerate.
* gas/sh/arch/sh4a.s: Regenerate.
* gas/sh/arch/sh4al-dsp.s: Regenerate.
* gas/sh/err-mova.s: New test.
ld/testsuite/
* ld-sh/arch/sh-dsp.s: Regenerate.
* ld-sh/arch/sh.s: Regenerate.
* ld-sh/arch/sh2.s: Regenerate.
* ld-sh/arch/sh2a-nofpu-or-sh3-nommu.s: Regenerate.
* ld-sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s: Regenerate.
* ld-sh/arch/sh2a-nofpu.s: Regenerate.
* ld-sh/arch/sh2a-or-sh3e.s: Regenerate.: Regenerate.
* ld-sh/arch/sh2a-or-sh4.s: Regenerate.
* ld-sh/arch/sh2a.s: Regenerate.
* ld-sh/arch/sh2e.s: Regenerate.
* ld-sh/arch/sh3-dsp.s: Regenerate.
* ld-sh/arch/sh3-nommu.s: Regenerate.
* ld-sh/arch/sh3.s: Regenerate.
* ld-sh/arch/sh3e.s: Regenerate.
* ld-sh/arch/sh4-nofpu.s: Regenerate.
* ld-sh/arch/sh4-nommu-nofpu.s: Regenerate.
* ld-sh/arch/sh4.s: Regenerate.
* ld-sh/arch/sh4a-nofpu.s: Regenerate.
* ld-sh/arch/sh4a.s: Regenerate.
* ld-sh/arch/sh4al-dsp.s: Regenerate.
2008-04-15 15:53:26 +00:00
19a6653ce8
ppc e500mc support
2008-04-14 11:01:38 +00:00
daf50ae75d
gas/
...
2008-04-10 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention -msse-check=[none|error|warning].
* config/tc-i386.c (sse_check): New.
(OPTION_MSSE_CHECK): Likewise.
(md_assemble): Check SSE instructions if needed.
(md_longopts): Add -msse-check.
(md_parse_option): Handle OPTION_MSSE_CHECK.
(md_show_usage): Show -msse-check=[none|error|warning].
* doc/c-i386.texi: Document -msse-check=[none|error|warning].
gas/testsuite/
2008-04-10 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run sse-check, sse-check-warn,
sse-check-error, x86-64-sse-check, x86-64-sse-check-warn and
x86-64-sse-check-error.
* gas/i386/sse-check.d: New.
* gas/i386/sse-check.s: Likewise.
* gas/i386/sse-check-error.l: Likewise.
* gas/i386/sse-check-error.s: Likewise.
* gas/i386/sse-check-warn.d: Likewise.
* gas/i386/sse-check-warn.e: Likewise.
* gas/i386/x86-64-sse-check.d: Likewise.
* gas/i386/x86-64-sse-check-error.l: Likewise.
* gas/i386/x86-64-sse-check-error.s: Likewise.
* gas/i386/x86-64-sse-check-warn.d: Likewise.
2008-04-10 17:53:40 +00:00
40f1253383
gas/
...
2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (parse_real_register): Return AVX register
only if AVX is enabled.
gas/testsuite/
2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/att-regs.s: Add AVX register test.
* gas/i386/intel-regs.s: Likewise.
* gas/i386/att-regs.d: Updated.
* gas/i386/intel-regs.d: Likewise.
2008-04-07 13:07:16 +00:00
783d3e7187
PR gas/6043
...
* config/tc-sh64.c (shmedia_md_pcrel_from_section): Use
md_pcrel_from_section for BFD_RELOC_64 and BFD_RELOC_64_PCREL.
* gas/sh/sh64/eh-1.d: New.
* gas/sh/sh64/eh-1.d: Likewise.
2008-04-07 02:55:08 +00:00
1b6e95c267
2008-04-04 Adrian Bunk <bunk@stusta.de>
...
Bob Wilson <bob.wilson@acm.org>
* config/tc-xtensa.c (xg_apply_fix_value): Check return code from
call to decode_reloc.
2008-04-04 23:25:49 +00:00
594ab6a333
gas/
...
2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention XSAVE. Change CLMUL to PCLMUL.
* config/tc-i386.c (cpu_arch): Add .pclmul.
(md_show_usage): Replace clmul with pclmul.
* doc/c-i386.texi: Likewise.
gas/testsuite/
2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/arch-10-1.l: Replace CLMUL with PCLMUL.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/arch-10.s: Likewise.
* gas/i386/clmul-intel.d: Likewise.
* gas/i386/clmul.d: Likewise.
* gas/i386/clmul.s: Likewise.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/x86-64-clmul-intel.d: Likewise.
* gas/i386/x86-64-clmul.d: Likewise.
* gas/i386/x86-64-clmul.s: Likewise.
* gas/i386/arch-10.d: Replace clmul with pclmul.
* gas/i386/x86-64-arch-2.d: Likewise.
opcodes/
2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
with CPU_PCLMUL_FLAGS/CpuPCLMUL.
(cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
* i386-opc.tbl: Likewise.
* i386-opc.h (CpuCLMUL): Renamed to ...
(CpuPCLMUL): This.
(CpuFMA): Updated.
(i386_cpu_flags): Replace cpuclmul with cpupclmul.
* i386-init.h: Regenerated.
2008-04-04 16:34:23 +00:00
c0f3af977b
binutils/
...
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* dwarf.c (dwarf_regnames_i386): Add AVX registers.
(dwarf_regnames_x86_64): Likewise.
gas/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention AES, CLMUL, AVX/FMA and -msse2avx.
* doc/c-i386.texi: Add avx, aes, clmul and fma to -march=.
Document -msse2avx, .avx, .aes, .clmul and .fma.
* config/tc-i386.c (YMMWORD_MNEM_SUFFIX): New.
(vex_prefix): Likewise.
(sse2avx): Likewise.
(CPU_FLAGS_ARCH_MATCH): Likewise.
(CPU_FLAGS_64BIT_MATCH): Likewise.
(CPU_FLAGS_32BIT_MATCH): Likewise.
(CPU_FLAGS_PERFECT_MATCH): Likewise.
(regymm): Likewise.
(vex_imm4): Likewise.
(fits_in_imm4): Likewise.
(build_vex_prefix): Likewise.
(VEX_check_operands): Likewise.
(bad_implicit_operand): Likewise.
(OPTION_MSSE2AVX): Likewise.
(T_YMMWORD): Likewise.
(_i386_insn): Add vex.
(cpu_arch): Add .avx, .aes, .clmul and .fma.
(cpu_flags_match): Changed to take a pointer to const template.
Enable encoding SSE instructions with VEX prefix for -msse2avx.
(match_mem_size): Also check ymmword.
(operand_type_match): Clear ymmword.
(md_begin): Allow '_' in mnemonic.
(type_names): Add OPERAND_TYPE_VEX_IMM4.
(process_immext): Update assert.
(md_assemble): Don't call process_immext if sse2avx and immext
are true. Call build_vex_prefix if vex is true.
(parse_insn): Updated for cpu_flags_match.
(swap_operands): Handle 5 operands.
(match_template): Handle 5 operands. Updated for cpu_flags_match.
Check regymm. Call VEX_check_operands. Handle YMMWORD_MNEM_SUFFIX.
(process_suffix): Handle YMMWORD_MNEM_SUFFIX.
(check_byte_reg): Check regymm.
(process_operands): Duplicate the destination register for
-msse2avx if needed.
(build_modrm_byte): Updated for instructions with VEX encoding.
(output_insn): Output VEX prefix if needed.
(md_longopts): Add msse2avx.
(md_parse_option): Handle OPTION_MSSE2AVX.
(md_show_usage): Add avx, aes, clmul, fma and -msse2avx.
(intel_e09): Support YMMWORD.
(intel_e11): Likewise.
(intel_get_token): Likewise.
gas/testsuite/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run aes, aes-intel, x86-64-aes,
x86-64-aes-intel, avx, avx-intel, inval-avx, x86-64-avx,
x86-64-avx-intel and x86-64-inval-avx.
* gas/cfi/cfi-i386.s: Add tests for AVX register maps.
* gas/cfi/cfi-x86_64.s: Likewise.
* gas/i386/aes.d: New.
* gas/i386/aes.s: Likewise.
* gas/i386/aes-intel.d: Likewise.
* gas/i386/avx.d: Likewise.
* gas/i386/avx.s: Likewise.
* gas/i386/avx-intel.d: Likewise.
* gas/i386/clmul.d: Likewise.
* gas/i386/clmul-intel.d: Likewise.
* gas/i386/clmul.s: Likewise.
* gas/i386/i386.exp: Likewise.
* gas/i386/inval-avx.l: Likewise.
* gas/i386/inval-avx.s: Likewise.
* gas/i386/sse2avx.d: Likewise.
* gas/i386/sse2avx.s: Likewise.
* gas/i386/x86-64-aes.d: Likewise.
* gas/i386/x86-64-aes.s: Likewise.
* gas/i386/x86-64-aes-intel.d: Likewise.
* gas/i386/x86-64-avx.d: Likewise.
* gas/i386/x86-64-avx.s: Likewise.
* gas/i386/x86-64-avx-intel.d: Likewise.
* gas/i386/x86-64-clmul.d: Likewise.
* gas/i386/x86-64-clmul-intel.d: Likewise.
* gas/i386/x86-64-clmul.s: Likewise.
* gas/i386/x86-64-inval-avx.l: Likewise.
* gas/i386/x86-64-inval-avx.s: Likewise.
* gas/i386/x86-64-sse2avx.d: Likewise.
* gas/i386/x86-64-sse2avx.s: Likewise.
* gas/i386/arch-10.s: Add tests for AVX, AES, CLMUL and FMA.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/rexw.s: Add AVX tests.
* gas/i386/x86-64-opcode-inval.s: Remove lds/les test.
* gas/cfi/cfi-i386.d: Updated.
* gas/cfi/cfi-x86_64.d: Likewise.
* gas/i386/arch-10.d: Likewise.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/rexw.d: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
* gas/i386/x86-64-opcode-inval.d: Likewise.
* gas/i386/x86-64-opcode-inval-intel.d: Likewise.
include/opcode/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (MAX_OPERANDS): Set to 5.
(MAX_MNEM_SIZE): Changed to 20.
opcodes/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (OP_E_register): New.
(OP_E_memory): Likewise.
(OP_VEX): Likewise.
(OP_EX_Vex): Likewise.
(OP_EX_VexW): Likewise.
(OP_XMM_Vex): Likewise.
(OP_XMM_VexW): Likewise.
(OP_REG_VexI4): Likewise.
(PCLMUL_Fixup): Likewise.
(VEXI4_Fixup): Likewise.
(VZERO_Fixup): Likewise.
(VCMP_Fixup): Likewise.
(VPERMIL2_Fixup): Likewise.
(rex_original): Likewise.
(rex_ignored): Likewise.
(Mxmm): Likewise.
(XMM): Likewise.
(EXxmm): Likewise.
(EXxmmq): Likewise.
(EXymmq): Likewise.
(Vex): Likewise.
(Vex128): Likewise.
(Vex256): Likewise.
(VexI4): Likewise.
(EXdVex): Likewise.
(EXqVex): Likewise.
(EXVexW): Likewise.
(EXdVexW): Likewise.
(EXqVexW): Likewise.
(XMVex): Likewise.
(XMVexW): Likewise.
(XMVexI4): Likewise.
(PCLMUL): Likewise.
(VZERO): Likewise.
(VCMP): Likewise.
(VPERMIL2): Likewise.
(xmm_mode): Likewise.
(xmmq_mode): Likewise.
(ymmq_mode): Likewise.
(vex_mode): Likewise.
(vex128_mode): Likewise.
(vex256_mode): Likewise.
(USE_VEX_C4_TABLE): Likewise.
(USE_VEX_C5_TABLE): Likewise.
(USE_VEX_LEN_TABLE): Likewise.
(VEX_C4_TABLE): Likewise.
(VEX_C5_TABLE): Likewise.
(VEX_LEN_TABLE): Likewise.
(REG_VEX_XX): Likewise.
(MOD_VEX_XXX): Likewise.
(PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
(PREFIX_0F3A44): Likewise.
(PREFIX_0F3ADF): Likewise.
(PREFIX_VEX_XXX): Likewise.
(VEX_OF): Likewise.
(VEX_OF38): Likewise.
(VEX_OF3A): Likewise.
(VEX_LEN_XXX): Likewise.
(vex): Likewise.
(need_vex): Likewise.
(need_vex_reg): Likewise.
(vex_i4_done): Likewise.
(vex_table): Likewise.
(vex_len_table): Likewise.
(OP_REG_VexI4): Likewise.
(vex_cmp_op): Likewise.
(pclmul_op): Likewise.
(vpermil2_op): Likewise.
(m_mode): Updated.
(es_reg): Likewise.
(PREFIX_0F38F0): Likewise.
(PREFIX_0F3A60): Likewise.
(reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
(prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
and PREFIX_VEX_XXX entries.
(x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
(three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
PREFIX_0F3ADF.
(mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
Add MOD_VEX_XXX entries.
(ckprefix): Initialize rex_original and rex_ignored. Store the
REX byte in rex_original.
(get_valid_dis386): Handle the implicit prefix in VEX prefix
bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
(print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
calling get_valid_dis386. Use rex_original and rex_ignored when
printing out REX.
(putop): Handle "XY".
(intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
ymmq_mode.
(OP_E_extended): Updated to use OP_E_register and
OP_E_memory.
(OP_XMM): Handle VEX.
(OP_EX): Likewise.
(XMM_Fixup): Likewise.
(CMP_Fixup): Use ARRAY_SIZE.
* i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
CPU_FMA_FLAGS and CPU_AVX_FLAGS.
(operand_type_init): Add OPERAND_TYPE_REGYMM and
OPERAND_TYPE_VEX_IMM4.
(cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
(opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
VexImmExt and SSE2AVX.
(operand_types): Add RegYMM, Ymmword and Vex_Imm4.
* i386-opc.h (CpuAVX): New.
(CpuAES): Likewise.
(CpuCLMUL): Likewise.
(CpuFMA): Likewise.
(Vex): Likewise.
(Vex256): Likewise.
(VexNDS): Likewise.
(VexNDD): Likewise.
(VexW0): Likewise.
(VexW1): Likewise.
(Vex0F): Likewise.
(Vex0F38): Likewise.
(Vex0F3A): Likewise.
(Vex3Sources): Likewise.
(VexImmExt): Likewise.
(SSE2AVX): Likewise.
(RegYMM): Likewise.
(Ymmword): Likewise.
(Vex_Imm4): Likewise.
(Implicit1stXmm0): Likewise.
(CpuXsave): Updated.
(CpuLM): Likewise.
(ByteOkIntel): Likewise.
(OldGcc): Likewise.
(Control): Likewise.
(Unspecified): Likewise.
(OTMax): Likewise.
(i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
(i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
vex3sources, veximmext and sse2avx.
(i386_operand_type): Add regymm, ymmword and vex_imm4.
* i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
* i386-reg.tbl: Add AVX registers, ymm0..ymm15.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2008-04-03 14:03:21 +00:00
2460c166ae
/gas:
...
2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
* config/tc-avr.c (mcu_types): Add attiny167.
* doc/c-avr.texi: Likewise.
/include:
2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
* opcode/avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
2008-03-28 21:51:38 +00:00
70881657a2
/gas:
...
2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
* config/tc-avr.c (mcu_types): Add atmega32u4.
* doc/c-avr.texi: Likewise.
2008-03-28 21:04:22 +00:00
25755480bf
/gas:
...
2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
* config/tc-avr.c (mcu_types): Add atmega32c1.
* doc/c-avr.texi: Likewise.
2008-03-28 19:24:52 +00:00
4641781c11
2008-03-28 Paul Brook <paul@codesourcery.com>
...
gas/
* config/tc-arm.c (parse_neon_mov): Parse register before immediate
to avoid spurious symbols.
2008-03-28 18:13:52 +00:00
025987eae0
* config/tc-m68k.c (md_convert_frag_1): Replace as_fatal with
...
as_bad_where.
2008-03-28 09:51:13 +00:00
38de72b9a0
* config/tc-avr.c (mcu_types): Add atmega32m1.
...
* doc/c-avr.texi: Likewise.
2008-03-27 14:52:35 +00:00
35997600fc
* config/tc-arm.c (do_neon_cvt): Move variable declarations to
...
start of block.
(do_neon_ext): Fix sign of comparison.
2008-03-27 14:12:15 +00:00
e2c038d34c
gas/:
...
* config/tc-bfin.c (bfin_start_line_hook): Localize the labels
generated for LOOP_BEGIN and LOOP_END instructions.
(bfin_gen_loop): Likewise.
gas/testsuite/:
* gas/bfin/flow.d: Adjust since the generated labels for LOOP_BEGIN
and LOOP_END instruction are local now.
* gas/bfin/flow2.d: Likewise.
2008-03-26 16:33:33 +00:00
ee171c8f94
gas/
...
* config/bfin-parse.y (check_macfunc_option): Allow (IU)
option for multiply and multiply-accumulate to data register
instruction.
(check_macfuncs): Don't check if accumulator matches the data register
here.
(assign_macfunc): Check if accumulator matches the
data register in each rule that moves to the data
register.
gas/testsuite/
* gas/bfin/arithmetic.s, gas/bfin/arithmetic.d: Add check
for IU option.
* gas/bfin/expected_errors.l, gas/bfin/expected_errors.s:
Add check for mismatch of accumulator and data register.
opcodes/
* bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
multiply and multiply-accumulate to data register instruction.
2008-03-26 16:21:10 +00:00
c1db045b89
gas/:
...
* config/bfin-parse.y (check_macfunc_option): New.
(check_macfuncs): Check option by calling check_macfunc_option.
Fix comparison always true warnings. Both scalar instructions
of vector instruction must share the same mode option. Only allow
option mode at the end of the second instruction of the vector.
(asm_1): Check option by calling check_macfunc_option.
gas/testsuite/:
* gas/bfin/expected_errors.l, gas/bfin/expected_errors.s: Add
tests for bad options of "multiply and multipy-accumulate to
accumulator" instructions. Add new vector instruction option
mode tests.
* gas/bfin/vector2.s: Add new vector instruction option mode test.
* gas/bfin/vector2.d: Adjust accordingly.
* gas/bfin/expected_errors.s, gas/bfin/expected_errors.l: Add test
for mismatched half registers in vector multipy-accumulate
instructions.
2008-03-26 15:58:27 +00:00
99bfa74a53
gas/
...
From Jie Zhang <jie.zhang@analog.com>
* config/bfin-parse.y (asm_1): Check AREGS in comparison
instructions. And call yyerror () when comparing PREG with
DREG.
gas/testsuite/:
* gas/bfin/expected_comparison_errors.l: New test.
* gas/bfin/expected_comparison_errors.s: New test.
* gas/bfin/bfin.exp: Add expected_comparison_errors.
2008-03-26 15:18:42 +00:00
5746fb46c8
2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com>
...
* opcodes/s390-mkopc.c (s390_opcode_cpu_val): S390_OPCODE_Z10 added.
(s390_cond_extensions): Reduced extensions to the compare related.
(main): z10 cpu type option added.
(expandConditionalJump): Renamed to ...
(insertExpandedMnemonic): ... this.
* opcodes/s390-opc.c: Re-group the operand format makros.
(INSTR_RIE_RRPU, INSTR_RIE_RRP0, INSTR_RIE_RUPI,
INSTR_RIE_R0PI, INSTR_RIE_RUPU, INSTR_RIE_R0PU, INSTR_RIE_R0IU,
INSTR_RIE_R0I0, INSTR_RIE_R0UU, INSTR_RIE_R0U0,
INSTR_RIE_RRUUU, INSTR_RIS_RURDI, INSTR_RIS_R0RDI, INSTR_RIS_RURDU,
INSTR_RIS_R0RDU, INSTR_RRF_U0RR, INSTR_RRF_00RR, INSTR_RRS_RRRDU,
INSTR_RRS_RRRD0, INSTR_RXY_URRD, INSTR_SIY_IRD, INSTR_SIL_RDI,
INSTR_SIL_RDU): New instruction formats added.
(MASK_RIE_RRPU, MASK_RIE_RRP0, MASK_RIE_RUPI, MASK_RIE_R0PI,
MASK_RIE_RUPU, MASK_RIE_R0PU, MASK_RIE_R0IU, MASK_RIE_R0I0,
MASK_RIE_R0UU, MASK_RIE_R0U0, MASK_RIE_RRUUU, MASK_RIS_RURDI,
MASK_RIS_R0RDI, MASK_RIS_RURDU, MASK_RIS_R0RDU, MASK_RRF_U0RR,
MASK_RRF_00RR, MASK_RRS_RRRDU, MASK_RRS_RRRD0, MASK_RXY_URRD,
MASK_SIY_IRD, MASK_SIL_RDI, MASK_SIL_RDU): New instruction format
masks added.
(s390_opformats): New formats added "ris", "rrs", "sil".
* opcodes/s390-opc.txt: Add the conditional jumps with the
extensions removed from automatic expansion in s390-mkopc.c manually.
(asi - trtre): Add new System z10 EC instructions.
* include/opcode/s390.h (s390_opcode_cpu_val): S390_OPCODE_Z10 added.
2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com>
* config/tc-s390.c (md_parse_option): z10 option added.
2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com>
* gas/s390/zarch-z10.d: New file.
* gas/s390/zarch-z10.s: New file.
* gas/s390/s390.exp: Run the z10 testcases.
2008-03-19 10:29:18 +00:00
da6b876ee6
PR 5946
...
* config/tc-hppa.c (is_same_frag): Delete.
2008-03-16 23:16:03 +00:00
3b49282506
2008-03-14 Sterling Augustine <sterling@tensilica.com>
...
* config/tc-xtensa.h (xtensa_relax_statesE): Update comment for
RELAX_LOOP_END_ADD_NOP.
2008-03-14 20:17:39 +00:00
15290f0adc
2008-03-09 Paul Brook <paul@codesourcery.com>
...
gas/
* config/tc-arm.c (arm_cpu_option_table): Add cortex-a9.
* doc/c-arm.texi: Add cortex-a9.
2008-03-09 15:20:31 +00:00
b1cc4aeb65
2008-03-09 Paul Brook <paul@codesourcery.com>
...
bfd/
* elf32-arm.c (elf32_arm_merge_eabi_attributes): Handle new
Tag_VFP_arch values.
binutils/
* readelf.c (arm_attr_tag_VFP_arch): Add "VFPv3-D16".
gas/
* config/tc-arm.c (fpu_vfp_ext_d32): New vairable.
(parse_vfp_reg_list, encode_arm_vfp_reg): Use it.
(arm_option_cpu_value): Add vfpv3-d16, vfpv2 and vfpv3.
(aeabi_set_public_attributes): Handle Tag_VFP_arch=VFPV3-D16.
* doc/c-arm.texi: Document new ARM FPU variants.
gas/testsuite/
* gas/arm/vfpv3-d16-bad.d: New test.
* gas/arm/vfpv3-d16-bad.l: New test.
include/opcode/
* arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
2008-03-09 13:23:29 +00:00
39623e120c
2008-03-07 Paul Brook <paul@codesourcery.com>
...
bfd/
* elf32-arm.c (elf32_arm_howto_table_1): Fix bitmasks for MOVW and
MOVT relocations.
(elf32_arm_final_link_relocate): Fix off by one MOVW/MOVT sign
extension.
(elf32_arm_relocate_section): Handle MOVW and MOVT
relocations. Improve safety check for other weird relocations.
(elf32_arm_check_relocs): Only set h->needs_plt for branch/call
relocations.
gas/
* config/tc-arm.c (md_apply_fix): Use correct offset range.
ld/testsuite/
* ld-arm/arm-elf.exp (armelftests): Add movw-merge and arm-app-movw.
* ld-arm/arm-app-movw.s: New test.
* ld-arm/arm-app.r: Update expected output.
* ld-arm/movw-merge.d: New test.
* ld-arm/movw-merge.s: New test.
2008-03-08 01:20:39 +00:00
d815f1a994
* config/tc-ppc.c (ppc_setup_opcodes): Tidy. Add code to test
...
for strict ordering of powerpc_opcodes, but disable for now.
2008-03-06 23:01:00 +00:00
7e8064706d
2008-03-04 Paul Brook <paul@codesourcery.com>
...
gas/
* config/tc-arm.c (arm_ext_barrier, arm_ext_msr): New.
(arm_ext_v7m): Rename...
(arm_ext_m): ... to this. Include v6-M.
(do_t_add_sub): Allow narrow low-reg non flag setting adds.
(do_t_mrs, do_t_msr, aeabi_set_public_attributes): Use arm_ext_m.
(md_assemble): Allow wide msr instructions.
(insns): Add classifications for v6-m instructions.
(arm_cpu_option_table): Add cortex-m1.
(arm_arch_option_table): Add armv6-m.
(cpu_arch): Add ARM_ARCH_V6M. Fix numbering of other v6 variants.
gas/testsuite/
* gas/arm/archv6m.d: New test.
* gas/arm/archv6m.s: New test.
* gas/arm/t16-bad.s: Test low register non flag setting add.
* gas/arm/t16-bad.l: Update expected output.
include/opcode/
* arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
(ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
(ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
2008-03-05 01:31:26 +00:00
77cba8a32b
bfd/
...
* xtensa-isa.c (xtensa_isa_num_pipe_stages): Make max_stage static and
only compute its value once.
gas/
* config/tc-xtensa.c (xtensa_num_pipe_stages): New.
(md_begin): Initialize it.
(resources_conflict): Use it.
2008-03-03 23:23:41 +00:00
58502fec59
2008-03-03 Sterling Augustine <sterling@tensilica.com>
...
* config/tc-xtensa.h (RELAX_XTENSA_NONE): New.
2008-03-03 22:14:45 +00:00
783de16343
* config/tc-ppc.h (struct _ppc_fix_extra): New.
...
(ppc_cpu): Declare.
(TC_FIX_TYPE, TC_INIT_FIX_DATA): Define.
* config/tc-ppc.c (ppu_cpu): Make global.
(ppc_insert_operand): Add ppu_cpu parameter.
(md_assemble): Adjust for above change.
(md_apply_fix): Pass tc_fix_data.ppc_cpu to ppc_insert_operand.
2008-03-01 07:24:47 +00:00
584206dbd5
* config/tc-arm.c (do_bx): Only test EF_ARM_EABI_VERSION on ELF
...
targeted ARM ports, otherwise just skip generating the reloc.
2008-02-22 16:47:01 +00:00
5ad3420347
* config/tc-arm.c (do_bx): Only test EF_ARM_EABI_VERSION on ELF
...
targeted ARM ports.
2008-02-22 15:14:44 +00:00
H.J. Lu
Paul Brook
Nick Clifton
Catherine Moore
Chao-ying Fu
Bob Wilson
David S. Miller
Adam Nemet
Mike Frysinger
Andrew Stubbs
Alan Modra
Kaz Kojima
Eric B. Weddington
Nathan Sidwell
Bernd Schmidt
Andreas Krebbel