bfd PR binutils/19775
* archive.c (bfd_generic_openr_next_archived_file): Allow zero
length elements in the archive.
binutils PR binutils/19775
* testsuite/binutils-all/ar.exp (proc empty_archive): New proc.
Run the new proc.
* testsuite/binutils-all/empty: New, empty, file.
2016-03-07 Jiong Wang <jiong.wang@arm.com>
bfd/
* elfnn-aarch64.c (elfNN_aarch64_check_relocs): Always create .got section
if the symbol "_GLOBAL_OFFSET_TABLE_" referenced.
ld/
* testsuite/ld-aarch64/implicit_got_section_1.s: New test source file.
* testsuite/ld-aarch64/implicit_got_section_1.d: New test expected result.
* testsuite/ld-aarch64/aarch64-elf.exp: Run new test.
Common symbol in executable is a definition, which overrides definition
from shared objects. When linker sees a new definition from a shared
object, the new dynamic definition should be overridden by the previous
common symbol in executable.
bfd/
PR ld/19579
* elflink.c (_bfd_elf_merge_symbol): Treat common symbol in
executable as definition if the new definition comes from a
shared library.
ld/
PR ld/19579
* testsuite/ld-elf/pr19579a.c: New file.
* testsuite/ld-elf/pr19579b.c: Likewise.
* testsuite/ld-elf/shared.exp: Run PR ld/19579 test.
bfd/
2016-02-29 Cupertino Miranda <Cupertino.Miranda@synopsys.com>
* elf32-arc.c (arc_elf_final_write_processing): Add condition to
the flag change.
(elf_arc_relocate_section): Fixes and conditions to support PIE.
Assert for code sections dynamic relocs.
gas/
2016-02-29 Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com>
* config/tc-arc.c: Enable code density instructions for ARC EM.
ld/
2016-02-29 Cupertino Miranda <Cupertino.Miranda@synopsys.com>
* scripttempl/arclinux.sc: Force .tdata and .tbss to always be
generated.
For these three relocations, 17 bit signed value should be used, instead of
16 bit. The bitsize field is changed from 16 to 17, this field in aarch64
backend is used for overflow check only.
bfd/
2016-02-26 Renlin Li <renlin.li@arm.com>
* elfnn-aarch64.c (elfNN_aarch64_howto_table): Fix signed overflow
check for MOVW_SABS_G0, MOVW_SABS_G1, MOVW_SABS_G2.
ld/
2016-02-26 Renlin Li <renlin.li@arm.com>
* testsuite/ld-aarch64/aarch64-elf.exp: Run new testcases.
* testsuite/ld-aarch64/emit-relocs-270.d: Update to use new boundary.
* testsuite/ld-aarch64/emit-relocs-271.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-272.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-270-overflow.d: New.
* testsuite/ld-aarch64/emit-relocs-270-overflow.s: New.
* testsuite/ld-aarch64/emit-relocs-271-overflow.d: New.
* testsuite/ld-aarch64/emit-relocs-271-overflow.s: New.
* testsuite/ld-aarch64/emit-relocs-272-overflow.d: New.
* testsuite/ld-aarch64/emit-relocs-272-overflow.s: New.
R_386_GOT32X, R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX relocations
retrieve the symbol address via its GOT slot. If the symbol address is
known at the link-time, we can use it directly by changing instruction
encoding. Indirect branch can only be converted to PC relative direct
branch. MOV can be changed to LEA or encoded differently with signed
address. The subset of binary operations can be encoded only with
signed address.
If undefined weak symbol is resolved to zero link-time, we can use it
as address. Zero addresss can't used with PC relative direct branch
when PIC is true since the current PC is unknown. In 64-bit, 32-bit
relocation for PC relatiave direct branch to zero may also overflow.
If this optimization causes relocation overflow, --no-relax can be used
to work around it.
bfd/
PR ld/19609
* elf32-i386.c (elf_i386_convert_load): Convert to R_386_32 for
load with locally bound symbols if PIC is false or there is no
base register. Optimize branch to 0 if PIC is false.
(elf_i386_relocate_section): Don't generate dynamic relocations
against undefined weak symbols if PIC is false.
* elf64-x86-64.c (elf_x86_64_convert_load): Disable optimization
if we can't estimate relocation overflow with --no-relax.
Convert to R_X86_64_32S/R_X86_64_32 for load with locally bound
symbols if PIC is false. Optimize branch to 0 if PIC is false.
(elf_x86_64_relocate_section): Don't generate dynamic relocations
against undefined weak symbols if PIC is false.
ld/
PR ld/19609
* testsuite/ld-i386/got1.dd: Updated.
* testsuite/ld-i386/lea1c.d: Likewise.
* testsuite/ld-i386/load1-nacl.d: Likewise.
* testsuite/ld-i386/load1.d: Likewise.
* testsuite/ld-i386/load4b.d: Likewise.
* testsuite/ld-i386/load5b.d: Likewise.
* testsuite/ld-i386/mov1b.d: Likewise.
* testsuite/ld-x86-64/mov1b.d: Likewise.
* testsuite/ld-x86-64/mov1d.d: Likewise.
* testsuite/ld-ifunc/ifunc-21-i386.d: Likewise.
* testsuite/ld-ifunc/ifunc-21-x86-64.d: Likewise.
* testsuite/ld-ifunc/ifunc-22-i386.d: Likewise.
* testsuite/ld-ifunc/ifunc-22-x86-64.d: Likewise.
* testsuite/ld-x86-64/gotpcrel1.dd: Likewise.
* testsuite/ld-x86-64/lea1a.d: Likewise.
* testsuite/ld-x86-64/lea1b.d: Likewise.
* testsuite/ld-x86-64/lea1c.d: Likewise.
* testsuite/ld-x86-64/lea1d.d: Likewise.
* testsuite/ld-x86-64/lea1e.d: Likewise.
* testsuite/ld-x86-64/lea1f.d: Likewise.
* testsuite/ld-x86-64/mov1b.d: Likewise.
* testsuite/ld-x86-64/mov1d.d: Likewise.
* testsuite/ld-x86-64/pr13082-3b.d: Likewise.
* testsuite/ld-x86-64/pr13082-4b.d: Likewise.
* testsuite/ld-x86-64/lea1.s: Add tests for 32-bit registers.
* testsuite/ld-i386/pr19609-1.s: New file.
* testsuite/ld-i386/pr19609-1a.d: Likewise.
* testsuite/ld-i386/pr19609-1b.d: Likewise.
* testsuite/ld-i386/pr19609-1c.d: Likewise.
* testsuite/ld-i386/pr19609-1d.d: Likewise.
* testsuite/ld-i386/pr19609-1e.d: Likewise.
* testsuite/ld-i386/pr19609-1f.d: Likewise.
* testsuite/ld-i386/pr19609-1g.d: Likewise.
* testsuite/ld-i386/pr19609-1h.d: Likewise.
* testsuite/ld-i386/pr19609-1i.d: Likewise.
* testsuite/ld-i386/pr19609-2.s: Likewise.
* testsuite/ld-i386/pr19609-2a.d: Likewise.
* testsuite/ld-i386/pr19609-2b.d: Likewise.
* testsuite/ld-i386/pr19609-2c.d: Likewise.
* testsuite/ld-i386/undefweak.s: Likewise.
* testsuite/ld-i386/undefweaka.d: Likewise.
* testsuite/ld-i386/undefweakb.d: Likewise.
* testsuite/ld-x86-64/pr13082-3c.d: Likewise.
* testsuite/ld-x86-64/pr13082-3d.d: Likewise.
* testsuite/ld-x86-64/pr19609-1.s: Likewise.
* testsuite/ld-x86-64/pr19609-1a.d: Likewise.
* testsuite/ld-x86-64/pr19609-1b.d: Likewise.
* testsuite/ld-x86-64/pr19609-1c.d: Likewise.
* testsuite/ld-x86-64/pr19609-1d.d: Likewise.
* testsuite/ld-x86-64/pr19609-1e.d: Likewise.
* testsuite/ld-x86-64/pr19609-1f.d: Likewise.
* testsuite/ld-x86-64/pr19609-1g.d: Likewise.
* testsuite/ld-x86-64/pr19609-1h.d: Likewise.
* testsuite/ld-x86-64/pr19609-1i.d: Likewise.
* testsuite/ld-x86-64/pr19609-1j.d: Likewise.
* testsuite/ld-x86-64/pr19609-1k.d: Likewise.
* testsuite/ld-x86-64/pr19609-1l.d: Likewise.
* testsuite/ld-x86-64/pr19609-1m.d: Likewise.
* testsuite/ld-x86-64/pr19609-2.s: Likewise.
* testsuite/ld-x86-64/pr19609-2a.d: Likewise.
* testsuite/ld-x86-64/pr19609-2b.d: Likewise.
* testsuite/ld-x86-64/pr19609-2c.d: Likewise.
* testsuite/ld-x86-64/pr19609-2d.d: Likewise.
* testsuite/ld-x86-64/pr19609-3.s: Likewise.
* testsuite/ld-x86-64/pr19609-3a.d: Likewise.
* testsuite/ld-x86-64/pr19609-3b.d: Likewise.
* testsuite/ld-x86-64/pr19609-4.s: Likewise.
* testsuite/ld-x86-64/pr19609-4a.d: Likewise.
* testsuite/ld-x86-64/pr19609-4b.d: Likewise.
* testsuite/ld-x86-64/pr19609-4c.d: Likewise.
* testsuite/ld-x86-64/pr19609-4d.d: Likewise.
* testsuite/ld-x86-64/pr19609-4e.d: Likewise.
* testsuite/ld-x86-64/pr19609-5.s: Likewise.
* testsuite/ld-x86-64/pr19609-5a.d: Likewise.
* testsuite/ld-x86-64/pr19609-5b.d: Likewise.
* testsuite/ld-x86-64/pr19609-5c.d: Likewise.
* testsuite/ld-x86-64/pr19609-5d.d: Likewise.
* testsuite/ld-x86-64/pr19609-5e.d: Likewise.
* testsuite/ld-x86-64/pr19609-6.s: Likewise.
* testsuite/ld-x86-64/pr19609-6a.d: Likewise.
* testsuite/ld-x86-64/pr19609-6b.d: Likewise.
* testsuite/ld-x86-64/pr19609-6c.d: Likewise.
* testsuite/ld-x86-64/pr19609-6d.d: Likewise.
* testsuite/ld-x86-64/pr19609-7.s: Likewise.
* testsuite/ld-x86-64/pr19609-7a.d: Likewise.
* testsuite/ld-x86-64/pr19609-7b.d: Likewise.
* testsuite/ld-x86-64/pr19609-7c.d: Likewise.
* testsuite/ld-x86-64/pr19609-7d.d: Likewise.
* testsuite/ld-i386/i386.exp: Run undefweak tests and tests for
PR ld/19609.
* testsuite/ld-x86-64/x86-64.exp: Run pr13082-3c, pr13082-3d
and tests for PR ld/19609.
* elf64-ppc.c (create_linkage_sections): Create sfpr when
save_restore_funcs, rest of sections when not relocatable.
(ppc64_elf_init_stub_bfd): Always call create_linkage_sections.
(sfpr_define): Define all symbols on emitted code.
(ppc64_elf_func_desc_adjust): Adjust for sfpr now being created
when relocatable. Move sfpr_define loop earlier.
Add elf_x86_64_need_pic and replace x86_64_elf_howto_table[r_type].name
with howto->name.
* elf64-x86-64.c (elf_x86_64_need_pic): New function.
(elf_x86_64_relocate_section): Use it. Replace
x86_64_elf_howto_table[r_type] with howto.
We need to update symbol version for symbols from linker script.
bfd/
PR ld/19698
* elflink.c (bfd_elf_record_link_assignment): Set versioned if
symbol version is unknown.
ld/
PR ld/19698
* testsuite/ld-elf/pr19698.d: New file.
* testsuite/ld-elf/pr19698.s: Likewise.
* testsuite/ld-elf/pr19698.t: Likewise.
Since plt_got.offset may be updated in x86 allocate_dynrelocs, set
plt_got.offset to (bfd_vma) -1 when setting needs_plt to 0.
* elf32-i386.c (elf_i386_allocate_dynrelocs): Set plt_got.offset
to (bfd_vma) -1 when setting needs_plt to 0.
* elf64-x86-64.c (elf_x86_64_allocate_dynrelocs): Likewise.
Linker assigned symbols should be made dynamic by default only when
creating shared object or relocatable executable.
bfd/
* elflink.c (bfd_elf_record_link_assignment): Check for shared
library, instead of PIC, and don't check PDE when making linker
assigned symbol dynamic.
ld/
* testsuite/ld-frv/fdpic-pie-6.d: Updated.
* testsuite/ld-mips-elf/pie-n32.d: Likewise.
* testsuite/ld-mips-elf/pie-n64.d: Likewise.
* testsuite/ld-mips-elf/pie-o32.d: Likewise.
We should always create the dynsym section, even if it is empty, with
dynamic sections.
* elflink.c (_bfd_elf_link_renumber_dynsyms): Always create the
dynsym section, even if it is empty, with dynamic sections.
elfNN_aarch64_size_stubs, the caller of aarch64_type_stub has redirected
the final destination of long branch veneer to plt stub if the call
should go through it.
It's redundant to do the same check and redirect again from scratch
inside aarch64_type_stub.
bfd/
* elfnn-aarch64. (aarch64_type_of_stub): Remove redundation calcuation
for destination. Remove useless function parameters.
(elfNN_aarch64_size_stubs): Update parameters for aarch64_type_of_stub.
In embedded environments, including boot loaders, the non-PIC executable
needs to export its symbols to modules loaded in the future. We should
always create dynamic sections for -E/--dynamic-list.
bfd/
PR ld/19617
* elflink.c (elf_link_add_object_symbols): Always create dynamic
sections for -E/--dynamic-list.
ld/
PR ld/19617
* testsuite/ld-elf/pr19617.s: New file.
* testsuite/ld-elf/pr19617a.d: Likewise.
* testsuite/ld-elf/pr19617b.d: Likewise.
* testsuite/ld-elf/pr19617c.d: Likewise.
In <https://sourceware.org/ml/binutils/2015-12/msg00190.html> (commit
4a07dc8135), Kwok fixed a problem with
the template used for a dummy BFD for an IR file for LTO on MinGW,
where the input and output formats are not the same.
A problem, however, remains in the case of linking for
x86_64-w64-mingw32 -m32, where LTO linking reports an ambiguity
between the pe-i386 and pei-i386 formats. An object (pe-i386) with
plugin data is being tested by the linker to see what formats match.
The default format initially set by the linker when
bfd_check_format_matches is called is pei-i386 (as that's the output
format from the linker script), which does not match, so the function
goes on to the loop over possible BFD vectors. The pe-i386 vector
matches, as it should. One other vector matches: the plugin vector.
bfd_check_format_matches tests a vector for matching by temporarily
modifying the BFD object to use that vector then using
_bfd_check_format on it. So the BFD object is temporarily using
plugin_vec. _bfd_check_format ends up using bfd_plugin_object_p which
uses plugin_object_p from ld which uses plugin_get_ir_dummy_bfd which
succeeds, having created a BFD based on link_info.output_bfd (because
srctemplate is the BFD temporarily using plugin_vec, even after Kwok's
patch link_info.output_bfd is all that's available to base the dummy
BFD on). So we end up with a match from the plugin vector which uses
the pei-i386 vector even though the pei-i386 vector itself does not
match the input object. (In the i686-mingw32 case, as opposed to this
multilib case, pe-i386 is the default BFD target, which would
short-circuit that logic.)
There are two cases of the linker handling inputs with a plugin: they
may be inputs that are also accepted by some non-plugin BFD format, as
here, or they may be a format that would not be recognized at all, as
with some tests in the ld testsuite. In the former case, there is no
need for BFD to accept the objects using the plugin vector, as the
linker has its own logic to allow plugins to claim objects accepted by
some other BFD vector. Thus, this patch arranges for the plugin
vector to have the lowest match priority, and for the priority from
that vector to be used in the relevant case (the attempted match to
the plugin vector results in TEMP pointing to the pei-i386 vector).
Tested for GCC and Binutils testsuites for x86_64-pc-linux-gnu, as
well as verifying that it fixes the observed LTO issue for
x86_64-w64-mingw32.
* plugin.c (plugin_vec): Set match priority to 255.
* format.c (bfd_check_format_matches) [BFD_SUPPORTS_PLUGINS]: When
matching against the plugin vector, take priority from there not
from TEMP.
gas * doc/as.texinfo (.section): Document that numeric values can now
be used for the flags and type fields of the ELF target's .section
directive. Add notes about the restrictions on setting flags and
types.
* config/obj-elf.c (obj_elf_change_section): Allow known sections
to be given processor specific section types. Allow processor and
application specific flags of a section to be set after
definition.
(obj_elf_parse_section_letters): Handle parsing numeric values.
(obj_elf_section_type): Handle parsing numeric values.
(obj_elf_section): Allow numeric type values.
* config/obj-elf.h (obj_elf_change_section): Update prototype.
* testsuite/gas/elf/section10.d: New test.
* testsuite/gas/elf/section10.s: Source file for new test.
* testsuite/gas/elf/elf.exp: Run the new test.
* testsuite/gas/i386/ilp32/x86-64-unwind.d: Remove dependency upon
the description of the flags produced by readelf.
* testsuite/gas/tic6x/scomm-directive-4.d: Likewise.
* NEWS: Mention the new feature.
bfd * elf-bfd.h (struct bfd_elf_special_section): Use unsigned values
for length and type fields. Use a signed value for the
suffix_length field.
binutils* readelf.c (get_section_type_name): Add hex prefix to offsets
printed for LOPROC and LOOS values. Ensure that a result is
always returned for the V850 target, even when an unrecognised
processor specific value is encountered.
(process_section_headers): Display key values in the order in
which they appear to the user. Add the "C (compressed)" value to
the list.
ld * testsuite/ld-i386/pr12718.d: Remove dependency upon the
description of the flags produced by readelf.
* testsuite/ld-i386/pr12921.d: Likewise.
* testsuite/ld-i386/tlsbin-nacl.rd: Likewise.
* testsuite/ld-i386/tlsbin.rd: Likewise.
* testsuite/ld-i386/tlsbindesc-nacl.rd: Likewise.
* testsuite/ld-i386/tlsbindesc.rd: Likewise.
* testsuite/ld-i386/tlsdesc-nacl.rd: Likewise.
* testsuite/ld-i386/tlsdesc.rd: Likewise.
* testsuite/ld-i386/tlsgdesc-nacl.rd: Likewise.
* testsuite/ld-i386/tlsgdesc.rd: Likewise.
* testsuite/ld-i386/tlsnopic-nacl.rd: Likewise.
* testsuite/ld-i386/tlsnopic.rd: Likewise.
* testsuite/ld-i386/tlspic-nacl.rd: Likewise.
* testsuite/ld-i386/tlspic.rd: Likewise.
* testsuite/ld-s390/tlsbin.rd: Likewise.
* testsuite/ld-s390/tlsbin_64.rd: Likewise.
* testsuite/ld-s390/tlspic.rd: Likewise.
* testsuite/ld-s390/tlspic_64.rd: Likewise.
* testsuite/ld-sh/tlsbin-2.d: Likewise.
* testsuite/ld-sh/tlspic-2.d: Likewise.
* testsuite/ld-tic6x/common.d: Likewise.
* testsuite/ld-tic6x/shlib-1.rd: Likewise.
* testsuite/ld-tic6x/shlib-1b.rd: Likewise.
* testsuite/ld-tic6x/shlib-1r.rd: Likewise.
* testsuite/ld-tic6x/shlib-1rb.rd: Likewise.
* testsuite/ld-tic6x/shlib-app-1.rd: Likewise.
* testsuite/ld-tic6x/shlib-app-1b.rd: Likewise.
* testsuite/ld-tic6x/shlib-app-1r.rd: Likewise.
* testsuite/ld-tic6x/shlib-app-1rb.rd: Likewise.
* testsuite/ld-tic6x/shlib-noindex.rd: Likewise.
* testsuite/ld-tic6x/static-app-1.rd: Likewise.
* testsuite/ld-tic6x/static-app-1b.rd: Likewise.
* testsuite/ld-tic6x/static-app-1r.rd: Likewise.
* testsuite/ld-tic6x/static-app-1rb.rd: Likewise.
* testsuite/ld-x86-64/ilp32-4-nacl.d: Likewise.
* testsuite/ld-x86-64/ilp32-4.d: Likewise.
* testsuite/ld-x86-64/pr12718.d: Likewise.
* testsuite/ld-x86-64/pr12921.d: Likewise.
* testsuite/ld-x86-64/split-by-file-nacl.rd: Likewise.
* testsuite/ld-x86-64/split-by-file.rd: Likewise.
* testsuite/ld-x86-64/tlsbin-nacl.rd: Likewise.
* testsuite/ld-x86-64/tlsbin.rd: Likewise.
* testsuite/ld-x86-64/tlsbindesc-nacl.rd: Likewise.
* testsuite/ld-x86-64/tlsbindesc.rd: Likewise.
* testsuite/ld-x86-64/tlsdesc-nacl.rd: Likewise.
* testsuite/ld-x86-64/tlsdesc.rd: Likewise.
* testsuite/ld-x86-64/tlsgdesc-nacl.rd: Likewise.
* testsuite/ld-x86-64/tlsgdesc.rd: Likewise.
* testsuite/ld-x86-64/tlspic-nacl.rd: Likewise.
* testsuite/ld-x86-64/tlspic.rd: Likewise.
* testsuite/ld-xtensa/tlsbin.rd: Likewise.
* testsuite/ld-xtensa/tlspic.rd: Likewise.
The least significant bit in GOT offset is to record whether we have
initialized the GOT entry in R_386_GOT32 processing. We need to mask
it off for R_386_GOT32X.
PR ld/19601
* elf32-i386.c (elf_i386_relocate_section): Mask off the least
significant bit in GOT offset for R_386_GOT32X.
PR 19405
* elf32-nios2.c (nios2_elf32_install_imm16): Allow for signed
immediate values.
* elf-eh-frame.c (_bfd_elf_discard_section_eh_frame): Limit the
number of messages about FDE encoding preventing .eh_frame_hdr
generation.
bfd * elfnn-aarch64.c (elfNN_aarch64_relocate_section): Add a more
helpful warning message to explain why certain AArch64 relocs
might overflow.
ld * testsuite/ld-aarch64/reloc-overflow-bad.d: New test.
* testsuite/ld-aarch64/reloc-overflow-1.s: New source file.
* testsuite/ld-aarch64/reloc-overflow-2.s: New source file.
* testsuite/ld-aarch64/aarch64-elf.exp: Run the new test.
bfd * elfnn-aarch64.c (elfNN_aarch64_relocate_section): Add a more
helpful warning message to explain why certain AArch64 relocs
might overflow.
ld * testsuite/ld-aarch64/reloc-overflow-bad.d: New test.
* testsuite/ld-aarch64/reloc-overflow-1.s: New source file.
* testsuite/ld-aarch64/reloc-overflow-2.s: New source file.
* testsuite/ld-aarch64/aarch64-elf.exp: Run the new test.
elf_x86_64_convert_load is very time consuming since it is called on
each input section and has a loop over input text sections to estimate
the branch distrance. We can store the estimated distrances in the
compressed_size field of the output section, which is only used to
decompress the compressed input section.
Before the patch, linking clang 3.9 takes 52 seconds. After the patch,
it only takes 2.5 seconds.
PR ld/19542
* elf64-x86-64.c (elf_x86_64_convert_load): Store the estimated
distrances in the compressed_size field of the output section.
This tightens the condition under which ld optimizes PIC entry code
to non-PIC.
bfd/
* elf64-ppc.c (ppc64_elf_relocate_section): Further restrict
ELFv2 entry optimization.
gold/
* powerpc.cc (relocate): Further restrict ELFv2 entry optimization.
The HAS_RELOC bit should be cleared when relocations are removed from
relocatable files.
bfd/
PR binutils/19547
* elf.c (assign_section_numbers): Clear HAS_RELOC if there are
no relocations in relocatable files.
binutils/
PR binutils/19547
* testsuite/binutils-all/objcopy.exp
(objcopy_test_without_global_symbol): New proc.
Run objcopy_test_without_global_symbol.
* testsuite/binutils-all/pr19547.c: New file.
Don't add DT_NEEDED if a symbol from a library loaded via DT_NEEDED
doesn't match the symbol referenced by regular object.
bfd/
PR ld/19553
* elflink.c (elf_link_add_object_symbols): Don't add DT_NEEDED
if a symbol from a library loaded via DT_NEEDED doesn't match
the symbol referenced by regular object.
ld/testsuite/
PR ld/19553
* testsuite/ld-elf/indirect.exp: Run tests for PR ld/19553.
* testsuite/ld-elf/pr19553.map: New file.
* testsuite/ld-elf/pr19553.map: Likewise.
* testsuite/ld-elf/pr19553a.c: Likewise.
* testsuite/ld-elf/pr19553b.c: Likewise.
* testsuite/ld-elf/pr19553b.out: Likewise.
* testsuite/ld-elf/pr19553c.c: Likewise.
* testsuite/ld-elf/pr19553c.out: Likewise.
* testsuite/ld-elf/pr19553d.c: Likewise.
* testsuite/ld-elf/pr19553d.out: Likewise.
Changing "pushq $1" in the following to "pushq $too_big" results in an
abort. BFD shouldn't abort on (deliberately) bad user input.
400480: ff 25 9a 0b 20 00 jmpq *0x200b9a(%rip)
400486: 68 01 00 00 00 pushq $0x1
40048b: e9 d0 ff ff ff jmpq 400460 <_init+0x20>
* elf64-x86-64.c (elf_x86_64_get_plt_sym_val): Don't abort on
an out of range reloc_index.
* elf32-i386.c (elf_i386_get_plt_sym_val): Likewise.
../../bfd/elf64-s390.c: In function 'elf_s390_reloc_name_lookup':
../../bfd/elf64-s390.c:340:5: error: statement is indented as if it were guarded by... [-Werror=misleading-indentation]
if (strcasecmp (elf64_s390_vtinherit_howto.name, r_name) == 0)
^~
../../bfd/elf64-s390.c:333:3: note: ...this 'for' clause, but it is not
for (i = 0;
^~~
bfd/
* elf64-s390.c (elf_s390_reloc_name_lookup): Fix indentation.
There is no need to check relocation IFUNC symbol if there are no
dynamic symbols.
bfd/
PR ld/19539
* elf32-i386.c (elf_i386_reloc_type_class): Check relocation
against STT_GNU_IFUNC symbol only with dynamic symbols.
* elf64-x86-64.c (elf_x86_64_reloc_type_class): Likewise.
ld/
PR ld/19539
* testsuite/ld-elf/pr19539.d: New file.
* testsuite/ld-elf/pr19539.s: Likewise.
* testsuite/ld-elf/pr19539.t: Likewise.
We should set BFD_DECOMPRESS to decompress debug sections when reading in
DWARF debug sections.
bfd/
PR binutils/19523
* dwarf2.c (_bfd_dwarf2_slurp_debug_info): Set BFD_DECOMPRESS to
decompress debug sections.
binutils/
PR binutils/19523
* Makefile.am (check-DEJAGNU): Pass CC and CC_FOR_BUILD to
runtest.
* Makefile.in: Regenerated.
* testsuite/binutils-all/compress.exp (test_gnu_debuglink): New
proc.
Run test_gnu_debuglink for native ELF build.
Just mask higher bits off, which returns the same set of 3-bit register
encodings of { 0, 1, 2, 3, 4, 5, 6, 7 } for the allowed 5-bit encodings
of { 16, 17, 2, 3, 4, 5, 6, 7 }. Input has already been validated with
OP16_VALID_REG.
bfd/
* elfxx-mips.c (BZ16_REG_FIELD): Simplify calculation.
PR ld/19455
* elf32-arm.c (elf32_arm_create_dynamic_sections): Set the ELF
class of the linker stub bfd.
(elf32_arm_check_relocs): Skip check for pic format after
processing a vxWorks R_ARM_ABS12 reloc.
* elflink.c (bfd_elf_final_link): Check for ELFCLASSNONE when
reporting a class mismatch.
* testsuite/ld-arm/vxworks1-lib.dd: Update for current
disassmebler output.
* testsuite/ld-arm/vxworks1-lib.rd: Likewise.
* testsuite/ld-arm/vxworks1.dd: Likewise.
* testsuite/ld-arm/vxworks1.rd: Likewise.
* testsuite/ld-arm/vxworks1.ld: Set the output format.
As defined at AArch64 ELF Specification (4.6.7 Call and Jump
relocations), symbol with type of non STT_FUNC but in different input
section with relocation place should insert long branch veneer also.
Meanwhile the current long branch veneer infrastructure havn't considered
the situation where the branch destination is "sym_value + rela->addend".
This was OK because we only insert veneer for long call destination is
STT_FUNC symbol for which the addend is always zero. But as we relax the
support to other situations by this patch, we need to handle addend be
non-zero value. For example, for static function, relocation against
"local symbol" are turned into relocation against "section symbol + offset"
where there is a valid addend.
bfd/
* elfnn-aarch64.c (aarch64_type_of_stub): Allow insert long branch
veneer for sym_sec != input_sec.
(elfNN_aarch64_size_stub): Support STT_SECTION symbol.
(elfNN_aarch64_final_link_relocate): Take rela addend into account when
calculation destination.
ld/
* testsuite/ld-aarch64/farcall-section.d: Delete.
* testsuite/ld-aarch64/farcall-section.s: Delete.
* testsuite/ld-aarch64/farcall-b-section.d: New expectation file.
* testsuite/ld-aarch64/farcall-bl-section.d: Likewise.
* testsuite/ld-aarch64/farcall-b-section.s: New testcase.
* testsuite/ld-aarch64/farcall-bl-section.s: Likewise.
* testsuite/ld-aarch64/aarch64-elf.exp: Likewise.
Since it will sometime have more than just prpsinfo. Also,
elf32-ppc.c needlessly includes this header.
* elf-linux-core.h: Rename from elf-linux-psinfo.h.
* elf.c: Adjust #include.
* elf32-ppc.c: Don't #include elf-linux-psinfo.h
* Makefile.am (SOURCE_HFILES): Update.
* Makefile.in: Regenerate.
* po/SRC-PORFILES.in: Regenerate.
Corefile code should be moved after running config.bfd, because it
uses want64.
* configure.ac: Move corefile selection later in file. Move
tdefaults code immediately after other target vector code.
* configure: Regenerate.
bfd/ChangeLog:
* elf32-arm.c ((elf32_arm_special_sections): Remove catch of noread
section using '.text.noread' pattern.
gas/ChangeLog:
* config/obj-elf.c (obj_elf_change_section) : Allow arm section with
SHF_ARM_NOREAD section flag.
* config/tc-arm.h (md_elf_section_letter) : Implement this hook to
handle letter 'y'.
(arm_elf_section_letter) : Declare it.
* config/tc-arm.c (arm_elf_section_letter): Handle letter 'y' to set
SHF_ARM_NOREAD section flag.
* doc/c-arm.texi (ARM section attribute 'y'): Document it.
gas/testsuite/ChangeLog:
* gas/arm/section-execute-only.s: New test case.
* gas/arm/section-execute-only.d: Expected output.
ld/testsuite/ChangeLog:
* ld-arm/thumb1-noread-not-present-mixing-two-section.s: Add 'y'
attribute usage.
* ld-arm/thumb1-noread-present-one-section.s: Likewise.
* ld-arm/thumb1-noread-present-two-section.s: Likewise.
* ld-arm/thumb1-input-section-flag-match.s: Likewise.
binutils/ChangeLog:
* readelf.c (get_elf_section_flags): Display y letter for section
with SHF_ARM_NOREAD section flag in readelf section output.
(process_section_headers): Add y letter in readelf section output
key mapping for ARM architecture.
bfd/ChangeLog:
* arc-plt.def: New file.
* arc-plt.h: Likewise.
* elf32-arc.c (elf_arc_abs_plt0_entry, elf_arc_abs_pltn_entry,
elf_arcV2_abs_plt0_entry, elf_arcV2_abs_pltn_entry,
elf_arc_pic_plt0_entry, elf_arc_pic_pltn_entry,
elf_arcV2_pic_plt0_entry, elf_arcV2_pic_pltn_entry): Remove.
(name_for_global_symbol): Added.
(ADD_RELA): Helper to create dynamic relocs.
(new_got_entry_to_list): Create a new got entry in linked list.
(symbol_has_entry_of_type): Search for specific type of entry in
list.
(is_reloc_for_GOT): return FALSE for any TLS related relocs.
(is_reloc_for_TLS, arc_elf_set_private_flags)
(arc_elf_print_private_bfd_data, arc_elf_copy_private_bfd_data)
(arc_elf_merge_private_bfd_data): New functions.
(debug_arc_reloc): Cleaned debug info printing.
(PDATA reloc): Changed not to perform address alignment.
(reverse_me): Added. Fix for ARC_32 relocs.
(arc_do_relocation): Return bfd_reloc_of when no relocation should
occur.
(arc_get_local_got_ents): Renamed from arc_get_local_got_offsets.
Changed function to access an array of list of GOT entries instead
of just an array of offsets.
(elf_arc_relocate_section): Added support for PIC and TLS related relocations.
(elf_arc_check_relocs): Likewise.
(elf_arc_adjust_dynamic_symbol, elf_arc_finish_dynamic_symbol,
(elf_arc_finish_dynamic_sections): Likewise
(arc_create_dynamic_sections): Modified conditions to create
dynamic sections.
(ADD_SYMBOL_REF_SEC_AND_RELOC): New macro.
(plt_do_relocs_for_symbol, relocate_plt_for_symbol)
(relocate_plt_for_entry): Changed to support new way to define PLT
related code.
(add_symbol_to_plt): Likewise.
(arc_elf_link_hash_table_create): New function.
include/ChangeLog:
* elf/arc-reloc.def (ARC_32, ARC_GOTPC, ARC_TLS_GD_GOT)
(ARC_TLS_IE_GOT, ARC_TLS_DTPOFF, ARC_TLS_DTPOFF_S9, ARC_TLS_LE_S9)
(ARC_TLS_LE_32): Fixed formula.
(ARC_TLS_GD_LD): Use new special function.
* opcode/arc-func.h: Changed all the replacement
functions to clear the patching bits before doing an or it with the value
argument.
PR ld/19440
inc * coff/internal.h (internal_syment): Use int to hold section
number.
(N_UNDEF): Cast to int not short.
(N_ABS): Likewise.
(N_DEBUG): Likewise.
(N_TV): Likewise.
(P_TV): Likewise.
bfd PR ld/19440
* coff-rs6000.c (_bfd_xcoff_swap_sym_in): Sign extend external
section number into internal section number.
* coff64-rs6000.c (_bfd_xcoff64_swap_sym_in): Likewise.
* coffswap.h (coff_swap_sym_in): Likewise.
* peXXigen.c (_bfd_XXi_swap_sym_in): Likewise.
* coffcode.h (_coff_bigobj_swap_sym_in): Make sure that internal
section number field is big enough to hold the external value.
bfd * elf32-arm.c (elf32_arm_fix_exidx_coverage): Insert cantunwind when
address in first unwind entry does not match start of section.
tests * ld-arm/arm-elf.exp: New test.
* ld-arm/unwind-mix.d: New file.
* ld-arm/unwind-mix1.s: New file.
* ld-arm/unwind-mix2.s: New file.
The convention within for relocation names is that they start with the
string "R_", however, this is not so for ARC for the display names of
relocations, however, internally, the names for the relocations types do
have the 'R_' prefix. I suspect that the missing 'R_' on the output
strings was an oversight, as I can't see any comment to the contrary.
To bring ARC into line with other targets, this commit adds the 'R_'
prefix to the output strings used for relocation names, and updates all
of the assembler tests where this was exposed.
bfd/ChangeLog:
* elf32-arc.c (reloc_type_to_name): Change ARC_RELOC_HOWTO to
place 'R_' before the reloc name returned.
(elf_arc_howto_table): Change ARC_RELOC_HOWTO to place 'R_' before
the relocation string.
gas/ChangeLog:
* testsuite/gas/arc/adc.d: Add 'R_' prefix to relocation names.
* testsuite/gas/arc/add.d: Likewise.
* testsuite/gas/arc/and.d: Likewise.
* testsuite/gas/arc/asl.d: Likewise.
* testsuite/gas/arc/asr.d: Likewise.
* testsuite/gas/arc/bic.d: Likewise.
* testsuite/gas/arc/extb.d: Likewise.
* testsuite/gas/arc/extw.d: Likewise.
* testsuite/gas/arc/j.d: Likewise.
* testsuite/gas/arc/jl.d: Likewise.
* testsuite/gas/arc/ld2.d: Likewise.
* testsuite/gas/arc/lsr.d: Likewise.
* testsuite/gas/arc/mov.d: Likewise.
* testsuite/gas/arc/or.d: Likewise.
* testsuite/gas/arc/pcl-relocs.d: Likewise.
* testsuite/gas/arc/pcrel-relocs.d: Likewise.
* testsuite/gas/arc/pic-relocs.d: Likewise.
* testsuite/gas/arc/plt-relocs.d: Likewise.
* testsuite/gas/arc/rlc.d: Likewise.
* testsuite/gas/arc/ror.d: Likewise.
* testsuite/gas/arc/rrc.d: Likewise.
* testsuite/gas/arc/sbc.d: Likewise.
* testsuite/gas/arc/sda-relocs.d: Likewise.
* testsuite/gas/arc/sda-relocs2.d: Likewise.
* testsuite/gas/arc/sexb.d: Likewise.
* testsuite/gas/arc/sexw.d: Likewise.
* testsuite/gas/arc/st.d: Likewise.
* testsuite/gas/arc/sub.d: Likewise.
* testsuite/gas/arc/tls-relocs.d: Likewise.
* testsuite/gas/arc/xor.d: Likewise.
Factor out the parts of `_bfd_mips_elf_merge_private_bfd_data'
responsible for ABI flag merging to `mips_elf_merge_obj_abiflags'. No
functional change.
bfd/
* elfxx-mips.c (mips_elf_merge_obj_abiflags): New function,
factored out from...
(_bfd_mips_elf_merge_private_bfd_data): ... here.
We have a problem in that in making compatibility checks while merging
private BFD data on the MIPS target we give priority to the attribute
check, which may fail and cause the function to abort early on. The
problem with this is the ABI compatibility aspect recorded in the
attributes is relatively minor compared to aspects recorded in the ELF
file header. However the premature exit causes any more important
compatibility aspect violated to be masked and not reported to the user
once a problem with attributes has been noticed.
So move the attribute check after the ELF file header flag check in
`_bfd_mips_elf_merge_private_bfd_data', and do not return prematurely
there. Take advantage of the resulting grouping of ELF file header
handling together and remove the premature success return point for the
first input object being handled, letting the code later on figure out
output ABI flags even for this object.
Update LD test cases according to messages from ELF file header checks
now preceding ones from attribute checks.
bfd/
* elfxx-mips.c (_bfd_mips_elf_merge_private_bfd_data): Move
attribute check after ELF file header flag check.
ld/
* testsuite/ld-mips-elf/attr-gnu-4-14.d: Update the order of
messages expected according to MIPS BFD private data merge
changes.
* testsuite/ld-mips-elf/attr-gnu-4-24.d: Likewise.
* testsuite/ld-mips-elf/attr-gnu-4-34.d: Likewise.
* testsuite/ld-mips-elf/attr-gnu-4-41.d: Likewise.
* testsuite/ld-mips-elf/attr-gnu-4-42.d: Likewise.
* testsuite/ld-mips-elf/attr-gnu-4-43.d: Likewise.
* testsuite/ld-mips-elf/attr-gnu-4-45.d: Likewise.
* testsuite/ld-mips-elf/attr-gnu-4-46.d: Likewise.
* testsuite/ld-mips-elf/attr-gnu-4-47.d: Likewise.
* testsuite/ld-mips-elf/attr-gnu-4-48.d: Likewise.
* testsuite/ld-mips-elf/attr-gnu-4-49.d: Likewise.
* testsuite/ld-mips-elf/attr-gnu-4-54.d: Likewise.
* testsuite/ld-mips-elf/attr-gnu-4-64.d: Likewise.
* testsuite/ld-mips-elf/attr-gnu-4-74.d: Likewise.
Fix the issue of any failure from `_bfd_elf_merge_object_attributes' not
being propagated by `mips_elf_merge_obj_attributes'.
bfd/
* elfxx-mips.c (mips_elf_merge_obj_attributes): Propagate the
return status from `_bfd_elf_merge_object_attributes'.
Factor out the parts of `_bfd_mips_elf_merge_private_bfd_data'
responsible for ELF file header flag compatibility checks to
`mips_elf_merge_obj_e_flags'. As a side effect remove a premature
return point from `_bfd_mips_elf_merge_private_bfd_data'. No functional
change otherwise.
bfd/
* elfxx-mips.c (mips_elf_merge_obj_e_flags): New function,
factored out from...
(_bfd_mips_elf_merge_private_bfd_data): ... here.
Fold the handling of input MIPS ABI flags in private BFD data merging
together, moving the attribute check afterwards, and consequently making
input vs output compatibility checks only start once all input ABI flag
data has been gathered, checked for inconsistencies and put in order.
Consequently also address the issue of input ABI flag inconsistencies
being masked by a failing attribute check, which currently makes
`_bfd_mips_elf_merge_private_bfd_data' exit prematurely and therefore
prevent input ABI flag inconsistencies from being reported. Such
inconsistencies need to be reported as they may be the very cause of an
attribute check failure.
bfd/
* elfxx-mips.c (_bfd_mips_elf_merge_private_bfd_data): Fold the
handling of input MIPS ABI flags together.
We currently special-case the handling of attribute checks on input
objects and make them even before we check a given input object actually
contains any sections. This does not add value as empty objects do not
cause a compatibility concern and we already make this observation for
other properties such as ELF file header flags. Moreover the attributes
themselves are stored in a `.gnu.attributes' section so the absence of
any section (except from a few special cases) implies there have been no
attributes provided either. Therefore it is safe to move the attribute
checks later on, after the null-section check has been made.
bfd/
* elfxx-mips.c (_bfd_mips_elf_merge_private_bfd_data): Suppress
attribute checks for null input.
Use local pointers to target data to reduce the amount of indirection
and improve the readability of `_bfd_mips_elf_merge_private_bfd_data'.
bfd/
* elfxx-mips.c (_bfd_mips_elf_merge_private_bfd_data): Use local
pointers to target data.
Correct a warning produced on any FP ABI mismatch observed. Unlike the
other settings, which in the presence of `.MIPS.abiflags' are duplicated
in the `e_flags' member of the ELF file header, information on the FP
ABI in use is duplicated in `.gnu.attributes' rather than in the former
place. Update the warning message accordingly.
bfd/
* elfxx-mips.c (_bfd_mips_elf_merge_private_bfd_data): Correct
an FP ABI warning.
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
(tag_cpu_arch_combine): Adjust comment in v4t_plus_v6_m with regards
to merging with ARMv8-M Baseline.
binutils/
* readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Baseline Tag_CPU_arch
value.
gas/
* config/tc-arm.c (arm_ext_v6t2_v8m): New feature for instructions
shared between ARMv6T2 and ARMv8-M.
(move_or_literal_pool): Check mov.w/mvn and movw availability against
arm_ext_v6t2 and arm_ext_v6t2_v8m respectively instead of checking
arm_arch_t2.
(do_t_branch): Error out for wide conditional branch instructions if
targetting ARMv8-M Baseline.
(non_v6t2_wide_only_insn): Add the logic for new wide-only instructions
in ARMv8-M Baseline.
(wide_insn_ok): New function.
(md_assemble): Use wide_insn_ok instead of non_v6t2_wide_only_insn and
adapt error message for unsupported wide instruction to ARMv8-M
Baseline.
(insns): Reorganize instructions shared by ARMv8-M Baseline and
ARMv6t2 architecture.
(arm_cpus): Set feature bit ARM_EXT2_V6T2_V8M for marvell-pj4 and
marvell-whitney cores.
(arm_archs): Define armv8-m.base architecture.
(cpu_arch_ver): Define ARM_ARCH_V8M_BASE architecture version.
(aeabi_set_public_attributes): Add logic to set Tag_CPU_arch to 17 for
ARMv8-M Mainline. Set Tag_DIV_use for ARMv8-M Baseline as well.
gas/testsuite/
* gas/arm/archv8m-base.d: New file.
* gas/arm/attr-march-armv8m.base.d: Likewise.
* gas/arm/armv8m.base-idiv.d: Likewise.
* gas/arm/any-armv8m.d: Adapt to deal with ARMv8-M Baseline.
include/elf/
* arm.h (TAG_CPU_ARCH_V8M_BASE): Declare.
include/opcode/
* arm.h (ARM_EXT2_V6T2_V8M): New extension bit.
(ARM_AEXT2_V8A): New architecture extension bitfield.
(ARM_AEXT2_V8_1A): Use ARM_AEXT2_V8A instead of ARM_EXT2_ATOMICS.
(ARM_AEXT_V8M_BASE): New architecture extension bitfield.
(ARM_AEXT2_V8M): Add extension bit ARM_EXT2_V6T2_V8M.
(ARM_ARCH_V6T2): Use ARM_EXT2_V6T2_V8M for the second extension
bitfield.
(ARM_ARCH_V6KT2): Likewise.
(ARM_ARCH_V6ZT2): Likewise.
(ARM_ARCH_V6KZT2): Likewise.
(ARM_ARCH_V7): Likewise.
(ARM_ARCH_V7A): Likewise.
(ARM_ARCH_V7VE): Likewise.
(ARM_ARCH_V7R): Likewise.
(ARM_ARCH_V7M): Likewise.
(ARM_ARCH_V7EM): Likewise.
(ARM_ARCH_V8A): Likewise.
(ARM_ARCH_V8M_BASE): New architecture bitfield.
(ARM_ARCH_THUMB2): Include instructions shared by ARMv6t2 and ARMv8-M.
(ARM_ARCH_V7A_SEC): Use ARM_EXT2_V6T2_V8M for the second extension
bitfield and reindent.
(ARM_ARCH_V7A_MP_SEC): Likewise.
(ARM_ARCH_V7R_IDIV): Likewise.
(ARM_ARCH_V8A_FP): Use ARM_AEXT2_V8A instead of ARM_EXT2_ATOMICS.
(ARM_ARCH_V8A_SIMD): Likewise.
(ARM_ARCH_V8A_CRYPTOV1): Likewise.
opcodes/
* arm-dis.c (arm_opcodes): Guard movw, movt cbz, cbnz, clrex, ldrex,
ldrexb, ldrexh, strex, strexb, strexh shared by ARMv6T2 and ARMv8-M by
ARM_EXT2_V6T2_V8M instead of ARM_EXT_V6T2.
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
(tag_cpu_arch_combine): Adjust v4t_plus_v6_m and comb array to account
for new TAG_CPU_ARCH_V4T_PLUS_V6_M value. Deal with NULL values in
comb array.
binutils/
* readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Mainline Tag_CPU_arch
value.
(arm_attr_tag_THUMB_ISA_use): Add ARMv8-M Mainline Tag_THUMB_ISA_use
value.
gas/
* config/tc-arm.c (arm_ext_m): Include ARMv8-M.
(arm_ext_v8m): New feature for ARMv8-M.
(arm_ext_atomics): New feature for ARMv8 atomics.
(do_tt): New encoding function for TT* instructions.
(insns): Add new entries for ARMv8-M specific instructions and
reorganize the ones shared by ARMv8-M Mainline and ARMv8-A.
(arm_archs): Define armv8-m.main architecture.
(cpu_arch_ver): Define ARM_ARCH_V8M_MAIN architecture version and
clarify the ordering rule.
(aeabi_set_public_attributes): Use TAG_CPU_ARCH_* macro to refer to
Tag_CPU_arch values for ARMv7e-M detection. Add logic to keep setting
Tag_CPU_arch to ARMv8-A for -march=all. Also set Tag_CPU_arch_profile
to 'A' if extension bit for atomic instructions is set, unless it is
ARMv8-M. Set Tag_THUMB_ISA_use to 3 for ARMv8-M. Set Tag_DIV_use to 0
for ARMv8-M Mainline.
gas/testsuite/
* gas/arm/archv8m.s: New file.
* gas/arm/archv8m-main.d: Likewise.
* gas/arm/attr-march-armv8m.main.d: Likewise.
* gas/arm/any-armv8m.s: Likewise.
* gas/arm/any-armv8m.d: Likewise.
include/elf/
* arm.h (TAG_CPU_ARCH_V8M_MAIN): Declare.
(MAX_TAG_CPU_ARCH): Define to TAG_CPU_ARCH_V8M_MAIN.
(TAG_CPU_ARCH_V4T_PLUS_V6_M): Define to unused value 15.
include/opcode/
* arm.h (ARM_EXT2_ATOMICS): New extension bit.
(ARM_EXT2_V8M): Likewise.
(ARM_EXT_V8): Adjust comment with regards to atomics and remove
mention of legacy use for that bit.
(ARM_AEXT2_V8_1A): New architecture extension bitfield.
(ARM_AEXT2_V8_2A): Likewise.
(ARM_AEXT_V8M_MAIN): Likewise.
(ARM_AEXT2_V8M): Likewise.
(ARM_ARCH_V8A): Use ARM_EXT2_ATOMICS for features in second bitfield.
(ARM_ARCH_V8_1A): Likewise with ARM_AEXT2_V8_1A.
(ARM_ARCH_V8_2A): Likewise with ARM_AEXT2_V8_2A.
(ARM_ARCH_V8M_MAIN): New architecture feature bitfield.
(ARM_ARCH_V8A_FP): Use ARM_EXT2_ATOMICS for features in second bitfield
and reindent.
(ARM_ARCH_V8A_SIMD): Likewise.
(ARM_ARCH_V8A_CRYPTOV1): Likewise.
(ARM_ARCH_V8_1A_FP): Use ARM_AEXT2_V8_1A to set second bitfield of
feature bits.
(ARM_ARCH_V8_1A_SIMD): Likewise.
(ARM_ARCH_V8_1A_CRYPTOV1): Likewise.
opcodes/
* arm-dis.c (arm_opcodes): Guard lda, ldab, ldaex, ldaexb, ldaexh, stl,
stlb, stlh, stlex, stlexb and stlexh by ARM_EXT2_ATOMICS instead of
ARM_EXT_V8.
(thumb32_opcodes): Add entries for wide ARMv8-M instructions.
bfd * elf-bfd.h: Add callback to count additional relocations.
* elf32-arm.c (_arm_elf_section_data): Add new counter.
(insert_cantunwind_after): Increment relocations counter.
(elf32_arm_fix_exidx_coverage): Remove exidx entries and add
terminating CANTUNWIND entry only in final builds.
(elf32_arm_add_relocation): New function.
(elf32_arm_write_section): Add relocations in relocatable builds.
(elf32_arm_count_additional_relocs): New function.
(elf_backend_count_additional_relocs): New define.
* bfd/elflink.c (bfd_elf_final_link): Use callback and adjust size of
.rel section.
* bfd/elfxx-target.h (elf_backend_count_additional_relocs): New define.
ld * emultempl/armelf.em (gld${EMULATION_NAME}_after_allocation): Call
elf32_arm_fix_exidx_coverage for relocatable builds.
ld/testsuite
* ld-arm/arm-elf.exp: New test.
* ld-arm/unwind-rel.d: New file.
* ld-arm/unwind-rel1.s: New file.
* ld-arm/unwind-rel2.s: New file.
* ld-arm/unwind-rel3.s: New file.
include/elf
* arm.h: Add arm SHF_ARM_NOREAD section flag.
bfd * bfd-in2.h: Regenerate.
* section.c: Add SEC_ELF_NOREAD.
* elf32-arm.c (elf32_arm_post_process_headers): Only set
PF_X attribute if a segment only contains section with
SHF_ARM_NOREAD flag.
(elf32_arm_fake_sections): Add SEC_ELF_NOREAD conversion.
(elf32_arm_section_flags): New function to convert SHF_ARM_NOREAD
to bfd flag.
(elf32_arm_lookup_section_flags): New function to allow
INPUT_SECTION_FLAGS directive with SHF_ARM_NOREAD flag.
(elf32_arm_special_sections): Add special sections array
to catch section prefix by '.text.noread' pattern.
ld/testsuite
* ld-arm/arm-elf.exp: New tests.
* ld-arm/thumb1-input-section-flag-match.d: New
* ld-arm/thumb1-input-section-flag-match.s: New
* ld-arm/thumb1-noread-not-present-mixing-two-section.d: New
* ld-arm/thumb1-noread-not-present-mixing-two-section.s: New
* ld-arm/thumb1-noread-present-one-section.d: New
* ld-arm/thumb1-noread-present-one-section.s: New
* ld-arm/thumb1-noread-present-two-section.d: New
* ld-arm/thumb1-noread-present-two-section.s: New
binutils
* readelf.c (get_elf_section_flags): Add support for ARM specific
section flags.
2015-12-16 Mickael Guene <mickael.guene@st.com>
bfd/
* bfd-in2.h: Regenerate.
* reloc.c: Add new relocations.
* libbfd.h (bfd_reloc_code_real_names): Add new relocations
display names.
* elf32-arm.c (elf32_arm_howto_table_1): Add HOWTO for new
relocations.
(elf32_arm_reloc_map): Add bfd/arm mapping for new relocations.
(elf32_arm_final_link_relocate): Implement new relocations
resolution.
gas/
* doc/c-arm.texi: Add documentation about new directives
* config/tc-arm.c (group_reloc_table): Add mapping between gas
syntax and new relocations.
(do_t_add_sub): Keep new relocations for add operand.
(do_t_mov_cmp): Keep new relocations for mov operand.
(insns): Use 'shifter operand with possible group relocation'
operand parse code for movs operand.
(md_apply_fix): Implement mov and add encoding when new
relocations on them.
(tc_gen_reloc): Add new relocations.
(arm_fix_adjustable): Since offset has a limited range ([0:255])
we disable adjust_reloc_syms() for new relocations.
gas/testsuite/
* gas/arm/adds-thumb1-reloc-local.d: New
* gas/arm/adds-thumb1-reloc-local.s: New
* gas/arm/movs-thumb1-reloc-local.d: New
* gas/arm/movs-thumb1-reloc-local.s: New
include/
* elf/arm.h: Add new arm relocations.
ld/testsuite/
* ld-arm/arm-elf.exp (armelftests_common): Add new relocations
tests.
* ld-arm/thumb1-adds.d: New
* ld-arm/thumb1-adds.s: New
* ld-arm/thumb1-movs.d: New
* ld-arm/thumb1-movs.s: New
The re-writing logic in _bfd_coff_final_link() overwrote the ".file"
part of the symbol table entry, due to not coping with the auxiliary
entry generated in all cases.
Note that while I would have wanted to add a test case,
(a) I didn't spot any one testing the base functionality here, and
(b) I wasn't able to figure out proper conditionals to use in e.g.
ld-elf/elf.exp to check for the necessary PE/PE+ support (which
varies by target).
Various fixes to linker relaxation. In general, we need to support
relaxing every branch, even if we don't relax it in the assembler,
so we can optionally defer relaxation to the linker.
* elf32-rl78.c (rl78_offset_for_reloc): Add more relocs.
(rl78_elf_relax_section): Add bc/bz/bnc/bnz/bh/bnh. Fix reloc
choices.
* config/rl78-parse.y: Make all branches relaxable via
rl78_linkrelax_branch().
* config/tc-rl78.c (rl78_linkrelax_branch): Mark all relaxable
branches with relocs.
(options): Add OPTION_NORELAX.
(md_longopts): Add -mnorelax.
(md_parse_option): Support OPTION_NORELAX.
(op_type_T): Add bh, sk, call, and br.
(rl78_opcode_type): Likewise.
(rl78_relax_frag): Fix not-relaxing logic. Add sk.
(md_convert_frag): Fix relocation handling.
(tc_gen_reloc): Strip relax relocs when not linker relaxing.
(md_apply_fix): Defer overflow handling for anything that needs a
PLT, to the linker.
* config/tc-rl78.h (TC_FORCE_RELOCATION): Force all relocations to
the linker when linker relaxing.
* doc/c-rl78.texi (norelax): Add.
This fixes some cases where the linker would incorrectly error on plt
relocs to local ifunc symbols. I've also tidied plt and ifunc
handling for ppc64, where check_relocs was allowing for the
possibility of plt calls via addr14/addr24 relocs but relocate_section
was not.
* elf32-ppc.c (ppc_elf_check_relocs): Don't error on local ifunc
plt call. Wrap long lines.
(ppc_elf_relocate_section): Wrap long lines.
* elf64-ppc.c (ppc64_elf_check_relocs): Don't error on local ifunc
plt calls. Move __tls_get_addr checks later. Don't create plt
for addr14/addr24 relocs.
(ppc64_elf_gc_sweep_hook): Adjust to suit check_relocs changes.
(ppc64_elf_relocate_section): Correct local ifunc handling for
PLT64, PLT32 and PLT16 relocs.
On 32-bit targets, memory requested for program/section headers on a
fuzzed binary can wrap to 0. A bfd_alloc of zero bytes actually
returns a one byte allocation rather than a NULL pointer. This then
leads to buffer overflows.
Making this check unconditional triggers an extremely annoying gcc-5
warning.
PR19323
* elfcode.h (elf_object_p): Check for ridiculous e_shnum and
e_phnum values.
Add a new relocation that marks large-model entry code, for edit back
to medium-model.
include/elf/
* ppc64.h (R_PPC64_ENTRY): Define.
bfd/
* reloc.c (BFD_RELOC_PPC64_ENTRY): New.
* elf64-ppc.c (reloc_howto_type ppc64_elf_howto_raw): Add
entry for R_PPC64_ENTRY.
(LD_R2_0R12, ADD_R2_R2_R12, LIS_R2, ADDIS_R2_R12): Define.
(ppc64_elf_reloc_type_lookup): Handle R_PPC64_ENTRY.
(ppc64_elf_relocate_section): Edit code at R_PPC64_ENTTY. Use
new insn defines.
* libbfd.h: Regenerate.
* bfd-in2.h: Regenerate.
Linker can't optimize R_386_GOT32 and R_386_GOT32X relocations if addend
isn't 0. It isn't valid to convert
movl foo@GOT+1(%ecx), %eax
to
leal foo@GOTOFF+1(%ecx), %eax
nor to convert
movq foo@GOTPCREL+1(%rip), %rax
to
leaq foo(%rip), %rax
for x86-64. We should check if addend is 0 before optimizing R_386_GOT32
and R_386_GOT32X relocations. Testcases are added for i386 and x86-64.
bfd/
* elf32-i386.c (elf_i386_convert_load): Skip if addend isn't 0.
(elf_i386_relocate_section): Skip R_386_GOT32X optimization if
addend isn't 0.
ld/testsuite/
* ld-i386/i386.exp: Run mov2a, mov2b and mov3.
* ld-i386/mov2.s: New file.
* ld-i386/mov2a.d: Likewise.
* ld-i386/mov2b.d: Likewise.
* ld-i386/mov3.d: Likewise.
* ld-i386/mov3.s: Likewise.
* ld-x86-64/mov2.s: Likewise.
* ld-x86-64/mov2a.d: Likewise.
* ld-x86-64/mov2b.d: Likewise.
* ld-x86-64/mov2c.d: Likewise.
* ld-x86-64/mov2d.d: Likewise.
* ld-x86-64/x86-64.exp: Run mov2a, mov2b, mov2c and mov2d.
Nick Clifton
Jiong Wang
H.J. Lu
Alan Modra
Claudiu Zissulescu
Renlin Li
Faraz Shahbazker
Rich Felker
Hans-Peter Nilsson
Joseph Myers
Walfred Tedeschi
Simon Marchi
Cupertino Miranda
Nathaniel Smith
Kamil Rytarowski
Jan Kratochvil
John David Anglin
Maciej W. Rozycki
Mickael Guene
John Baldwin
Yury Usishchev
Andrew Burgess
Sandra Loosemore
Thomas Preud'homme
Yoshinori Sato
Christophe Lyon
Jan Beulich
DJ Delorie
Kaz Kojima