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390 Commits

Author SHA1 Message Date
Michael Meissner 215ac9533c Fix brf0{t,f}.s <label> -> instruction not to execute instruction if branch succeeds 1996-09-15 03:46:52 +00:00
Ian Lance Taylor ad0d14e7a2 * Makefile.in (CC_FOR_BUILD): New variable. 
(AR, AR_FLAGS, BISON, MAKEINFO): Remove duplicate variables.
	(RANLIB, CC): Likewise.
	(end): Use $(CC_FOR_BUILD), not $(CC).
	* configure.in: Set CC_FOR_BUILD.
	* configure: Rebuild.
 1996-09-14 04:05:41 +00:00
Michael Meissner 19d44375ff For unknown traps, print contents of registers and continue execution 1996-09-14 02:36:40 +00:00
Mark Alexander 65c0d7dee9 * simops.c (OP_5F00): Fix problems with system calls. 1996-09-12 19:52:40 +00:00
Michael Meissner a57190924d Correct trap tracing information 1996-09-12 16:20:05 +00:00
Michael Meissner 1d00ce8392 Print line # and function name or filename if they exist for each PC. 1996-09-12 16:06:02 +00:00
Michael Meissner 9b280a864b Store bfd pointer in a global variable 1996-09-12 15:28:40 +00:00
Michael Meissner 5ceef1b54f fix typo 1996-09-11 22:56:25 +00:00
Michael Meissner ead4a3f157 Add tracing support; Fix some problems with hardwired sizes 1996-09-11 20:54:21 +00:00
Jeff Law 9909e232c0 * interp.c (hash): Make this an inline function 
when compiling with GCC.  Simplify.
        * simpos.c: Explicitly include "sys/syscall.h".  Remove
        some #if 0'd code.  Enable more emulated syscalls.
Checking in more stuff.
 1996-09-10 02:51:07 +00:00
Michael Meissner 2254cd90a9 Addi needs to set the carry 1996-09-09 21:12:46 +00:00
Michael Meissner 308f64d3ac Fix ld2w tracing 1996-09-09 20:45:33 +00:00
Michael Meissner 60fc5b7270 Correct tracing of cpfg 1996-09-09 20:10:31 +00:00
Michael Meissner 293c76a376 Make ex{f,t}* tests agree with book 1996-09-09 18:24:18 +00:00
Michael Meissner 069398aaff Fix accumulator shifts 1996-09-09 17:30:36 +00:00
Stu Grossman fad4a760fd * erc32.c (port_init): Disable this for __GO32__ (got no pty's 
there either...).
 1996-09-08 23:35:50 +00:00
Ian Lance Taylor f39a09c9ad * configure.in: Do build erc32 for DOS and Windows hosts. 
* configure: Rebuild.
 1996-09-08 21:24:10 +00:00
Martin Hunt ea2155e858 Fri Sep 6 17:56:17 1996 Martin M. Hunt <hunt@pizza.cygnus.com> 
* simops.c (OP_2600, OP_2601): Changed min and max comparisons
	to use signed register values.
 1996-09-07 00:58:25 +00:00
Stu Grossman 1852b017b8 * Makefile.in erc32/Makefile.in: Don't set srcroot. This should 
be inherited from the parent.  Remove INSTALL_XFORM and
	INSTALL_XFORM1.  Make INSTALL be set from configure.
 1996-09-05 01:16:22 +00:00
Ian Lance Taylor 68867afb88 * configure.in: Only build the MIPS simulator if we are using 
gcc.
	* configure: Rebuild.
 1996-09-04 19:50:55 +00:00
Michael Meissner 9b86c7e2e2 Second pass at canadian cross 1996-09-04 19:11:53 +00:00
Michael Meissner 1eaaf3050e First cut at dealing with canadian crosses; make -t in debugger set d10v_debug if DEBUG 1996-09-04 18:50:13 +00:00
Michael Meissner 7eebfc6296 More debug support; Enable -t/-v to work correctly; Add --enable-sim-cflags configure switch 1996-09-04 17:42:51 +00:00
Michael Meissner 87178dbdf7 Enhance debug support 1996-09-04 15:41:43 +00:00
Mark Alexander 8719be26c4 * simops.c: Include correct syscall.h for d10v, not host's. 
Fix #ifdef SYS_stat.
 1996-09-04 11:51:06 +00:00
Jeff Law 9fca2fd3c6 * gencode.c: Fix various indention & style problems. 
Remove test code.  Remove #if 0 code.
        * interp.c: Provide prototypes for all static functions.
        Fix minor indention problems.
        (sim_open, sim_resume): Remove unused variables.
        (sim_read): Return type is "int".
        * simops.c: Remove unused variables.
        (divh): Make result of divide-by-zero zero.
        (setf): Initialize result to keep compiler quiet.
        (sar instructions): These just clear the overflow bit.
        * v850_sim.h: Provide prototypes for put_byte, put_half
        and put_word.
Cleaning up.
 1996-09-03 18:31:48 +00:00
Michael Meissner 63a91cfb9d Portability fixes; re-add printf/putchar traps 1996-09-03 18:01:03 +00:00
Jeff Law 2b6b2c6d8e Fix typpppo 1996-09-03 17:15:16 +00:00
Jeff Law d81352b8b8 * interp.c: OP should be an array of 32bit operands! 
(v850_callback): Declare.
        (do_format_5): Fix extraction of OP[0].
        (sim_size): Remove debugging printf.
        (sim_set_callbacks): Do something useful.
        (sim_stop_reason): Gross hacks to get c-torture running.
        * simops.c: Simplify code for computing targets of bCC
        insns.   Invert 's' bit if 'ov' bit is set for some
        instructions.  Fix 'cy' bit handling for numerous
        instructions.  Make the simulator stop when a halt
        instruction is encountered.  Very crude support for
        emulated syscalls (trap 0).
        * v850_sim.h: Include "callback.h" and declare
        v850_callback.  Items in the operand array are 32bits.
Fixes & syscall stuff.
 1996-09-03 16:25:51 +00:00
Jeff Law 82feb39ed1 Opps. Forgot to commit this a few days ago. 1996-08-31 02:49:05 +00:00
Jeff Law 787d66bb4d * simops.c: Fix "not1" and "set1". 1996-08-30 21:55:26 +00:00
Jeff Law 3046d87986 * simops.c: Don't forget to initialize temp for 
"ld.h" and "ld.w"
 1996-08-30 20:15:51 +00:00
Jeff Law ba853302f2 * interp.c: Remove various debugging printfs. 1996-08-30 16:42:49 +00:00
Jeff Law 0e4ccc58f2 * simops.c: Fix satadd, satsub boundary case handling. 1996-08-30 16:41:39 +00:00
Jeff Law 83fc3bac9f * interp.c (hash): Fix. 
* interp.c (do_format_8): Get operands correctly and
        call the target function.
        * simops.c: Rough cut at "clr1", "not1", "set1", and "tst1".
 1996-08-30 16:35:10 +00:00
Jeff Law 3cb6bf7818 * interp.c (do_format_4): Get operands correctly and 
call the target function.
        * simops.c: Rough cut at "sld.b", "sld.h", "sld.w", "sst.b",
        "sst.h", and "sst.w".
 1996-08-30 05:49:07 +00:00
Jeff Law 28647e4c0c * v850_sim.h: The V850 doesn't have split I&D spaces. Change 
accordingly.  Remove many unused definitions.
        * interp.c: The V850 doesn't have split I&D spaces.  Change
        accordingly.
        (get_longlong, get_longword, get_word): Deleted.
        (write_longlong, write_longword, write_word): Deleted.
        (get_operands): Deleted.
        (get_byte, get_half, get_word): New functions.
        (put_byte, put_half, put_word): New functions.
        * simops.c: Remove unused functions.  Rough cut at
        "ld.b", "ld.h", "ld.w", "st.b", "st.h", "st.w" insns.
 1996-08-30 05:41:10 +00:00
Jeff Law 614f1c68ed * v850_sim.h (struct _state): Remove "psw" field. Add 
"sregs" field.
        (PSW): Remove bogus definition.
        * simops.c: Change condition code handling to use the psw
        register within the sregs array.  Handle "ldsr" and "stsr".
 1996-08-30 05:09:08 +00:00
Jeff Law dca41ba76b * simops.c: Handle "satadd", "satsub", "satsubi", "satsubr". 1996-08-30 04:59:02 +00:00
Jeff Law e9b6cbaca5 * interp.c (do_format_5): Get operands correctly and 
call the target function.
        (sim_resume): Don't do a PC update for format 5 instructions.
        * simops.c: Handle "jarl" and "jmp" instructions.
 1996-08-30 04:27:48 +00:00
Jeff Law 3095b8dfc5 * simops.c: Fix minor typos. Handle "cmp", "setf", "tst" 
"di", and "ei" instructions correctly.
 1996-08-30 04:11:32 +00:00
Jeff Law 2108e86459 * interp.c (do_format_3): Get operands correctly and call 
the target function.
        * simops.c: Handle bCC instructions.
 1996-08-30 03:48:13 +00:00
Jeff Law 35404c7d07 * simops.c: Add condition code handling to shift insns. 
Fix minor typos in condition code handling for other insns.
 1996-08-30 03:23:36 +00:00
Jeff Law aabce0f46c * Makefile.in: Fix typo. 
* simops.c: Add condition code handling to "sub" "subr" and
        "divh" instructions.
 1996-08-30 03:07:24 +00:00
Jeff Law 0ef0eba580 * interp.c (hash): Update to be more accurate. 
(lookup_hash): Call hash rather than computing the hash
        code here.
        (do_format_1_2): Handle format 1 and format 2 instructions.
        Get operands correctly and call the target function.
        (do_format_6): Get operands correctly and call the target
        function.
        (do_formats_9_10): Rough cut so shift ops will work.
        (sim_resume): Tweak to deal with format 1 and format 2
        handling in a single funtion.  Don't update the PC
        for format 3 insns.  Fix typos.
        * simops.c: Slightly reorganize.  Add condition code handling
        to "add", "addi", "and", "andi", "or", "ori", "xor", "xori"
        and "not" instructions.
        * v850_sim.h (reg_t): Registers are 32bits.
        (_state): The V850 has 32 general registers.  Add a 32bit
        psw and pc register too.  Add accessor macros
Fixing lots of stuff.  Starting to add condition code support.  Basically
check pointing the work to date.
 1996-08-29 23:39:23 +00:00
Jeff Law 775533747d * simops.c: Add shift support. 1996-08-29 22:29:41 +00:00
Jeff Law fb8eb42bd6 Fix typos in multiply and divide code. 1996-08-29 22:05:15 +00:00
Jeff Law e98e3b2c5a * simops.c: Add multiply & divide support. Abort for system 
instructions.
 1996-08-29 20:08:37 +00:00
Jeff Law 1fe983dcdf * simops.c: Add logicals, mov, movhi, movea, add, addi, sub 
and subr.  No condition codes yet.
 1996-08-29 19:53:37 +00:00
Jeff Law 22c1c7ddea * ChangeLog, Makefile.in, configure, configure.in, v850_sim.h, 
gencode.c, interp.c, simops.c: Created.
So we've got something to hack on.
 1996-08-29 01:06:42 +00:00