Many operand types, in particular the various kinds of registers, can't
be combined with one another (neither in templates nor in register
entries), and hence it is not a good use of resources (memory as well as
execution time) to represent them as individual bits of a bit field.
Hi,
This patch is part of a series that adds support for Armv8.6-A
to binutils.
In this last patch, the new Data Gathering Hint mnemonic is introduced.
Committed on behalf of Mihail Ionescu.
gas/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
* testsuite/gas/aarch64/dgh.s: New test.
* testsuite/gas/aarch64/dgh.d: New test.
opcodes/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
* opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
(aarch64_opcode_table): Add data gathering hint mnemonic.
* opcodes/aarch64-dis-2.c: Account for new instruction.
Is it ok for trunk?
Regards,
Mihail
Hi,
This patch is part of a series that adds support for Armv8.6-A
(Matrix Multiply and BFloat16 extensions) to binutils.
This patch introduces the Matrix Multiply (Int8, F32, F64) extensions
to the arm backend.
The following Matrix Multiply instructions are added: vummla, vsmmla,
vusmmla, vusdot, vsudot[1].
[1]https://developer.arm.com/docs/ddi0597/latest/simd-and-floating-point-instructions-alphabetic-order
Committed on behalf of Mihail Ionescu.
gas/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
* config/tc-arm.c (arm_ext_i8mm): New feature set.
(do_vusdot): New.
(do_vsudot): New.
(do_vsmmla): New.
(do_vummla): New.
(insns): Add vsmmla, vummla, vusmmla, vusdot, vsudot mnemonics.
(armv86a_ext_table): Add i8mm extension.
(arm_extensions): Move bf16 extension to context sensitive table.
(armv82a_ext_table, armv84a_ext_table, armv85a_ext_table):
Move bf16 extension to context sensitive table.
(armv86a_ext_table): Add i8mm extension.
* doc/c-arm.texi: Document i8mm extension.
* testsuite/gas/arm/i8mm.s: New test.
* testsuite/gas/arm/i8mm.d: New test.
* testsuite/gas/arm/bfloat17-cmdline-bad-3.d: Update test.
include/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
* opcode/arm.h (ARM_EXT2_I8MM): New feature macro.
opcodes/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
* arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
Regression tested on arm-none-eabi.
Is this ok for trunk?
Regards,
Mihail
Hi,
This patch is part of a series that adds support for Armv8.6-A
(Matrix Multiply and BFloat16 extensions) to binutils.
This patch introduces the Matrix Multiply (Int8, F32, F64) extensions
to the aarch64 backend.
The following instructions are added: {s/u}mmla, usmmla, {us/su}dot,
fmmla, ld1rob, ld1roh, d1row, ld1rod, uzip{1/2}, trn{1/2}.
Committed on behalf of Mihail Ionescu.
gas/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
* config/tc-aarch64.c: Add new arch fetures to suppport the mm extension.
(parse_operands): Add new operand.
* testsuite/gas/aarch64/i8mm.s: New test.
* testsuite/gas/aarch64/i8mm.d: New test.
* testsuite/gas/aarch64/f32mm.s: New test.
* testsuite/gas/aarch64/f32mm.d: New test.
* testsuite/gas/aarch64/f64mm.s: New test.
* testsuite/gas/aarch64/f64mm.d: New test.
* testsuite/gas/aarch64/sve-movprfx-mm.s: New test.
* testsuite/gas/aarch64/sve-movprfx-mm.d: New test.
include/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_I8MM): New.
(AARCH64_FEATURE_F32MM): New.
(AARCH64_FEATURE_F64MM): New.
(AARCH64_OPND_SVE_ADDR_RI_S4x32): New.
(enum aarch64_insn_class): Add new instruction class "aarch64_misc" for
instructions that do not require special handling.
opcodes/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
* aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
aarch64_feature_f64mm): New feature sets.
(INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
instructions.
(I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
macros.
(QL_MMLA64, OP_SVE_SBB): New qualifiers.
(OP_SVE_QQQ): New qualifier.
(INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
the movprfx constraint.
(aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
(aarch64_opcode_table): Define new instructions smmla,
ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod
uzip{1/2}, trn{1/2}.
* aarch64-opc.c (operand_general_constraint_met_p): Handle
AARCH64_OPND_SVE_ADDR_RI_S4x32.
(aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
* aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
Account for new instructions.
* opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
S4x32 operand.
* aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
Regression tested on arm-none-eabi.
Is it ok for trunk?
Regards,
Mihail
Hi,
This patch is part of a series that adds support for Armv8.6-A
(Matrix Multiply and BFloat16 extensions) to binutils.
This patch implements the '.bfloat' directive for the AArch64 backend.
The syntax for the directive is:
.bfloat16 <0-n numbers>
e.g.
.bfloat16 12.0
.bfloat16 0.123, 1.0, NaN, 5
This is implemented by utilizing the ieee_atof_detail function in order
to encode the slightly
different bfloat16 format.
Added testcases to verify the correct encoding for various bfloat16
values (NaN, Infinity (+ & -), normals, subnormals etc...).
Cross compiled and tested on aarch64-none-elf and aarch64-none-linux-gnu
with no issues.
Committed on behalf of Mihail Ionescu.
gas/ChangeLog:
2019-10-29 Mihail Ionescu <mihail.ionescu@arm.com>
2019-10-29 Barnaby Wilks <barnaby.wilks@arm.com>
* config/tc-aarch64.c (md_atof): Add encoding for the bfloat16 format.
* testsuite/gas/aarch64/bfloat16-directive-le.d: New test.
* testsuite/gas/aarch64/bfloat16-directive-be.d: New test.
* testsuite/gas/aarch64/bfloat16-directive.s: New test.
Is it ok for trunk?
Regards,
Mihail
Hi,
This patch is part of a series that adds support for Armv8.6-A
(Matrix Multiply and BFloat16 extensions) to binutils.
This patch implements the '.bfloat16' directive for the Arm backend.
The syntax for the directive is:
.bfloat16 <0-n numbers>
e.g.
.bfloat16 12.0
.bfloat16 0.123, 1.0, NaN, 5
This is implemented by utilizing the ieee_atof_detail function (included
in the previous patch) in order to encode the slightly different
bfloat16 format.
Added testcases to verify the correct encoding for various bfloat16
values (NaN, Infinity (+ & -), normals, subnormals etc...).
Cross compiled and tested on arm-none-eabi and arm-none-linux-gnueabihf
with no issues.
Committed on behalf of Mihail Ionescu.
gas/ChangeLog:
2019-10-21 Mihail Ionescu <mihail.ionescu@arm.com>
2019-10-21 Barnaby Wilks <barnaby.wilks@arm.com>
* config/tc-arm.c (md_atof): Add encoding for bfloat16
* testsuite/gas/arm/bfloat16-directive-le.d: New test.
* testsuite/gas/arm/bfloat16-directive-be.d: New test.
* testsuite/gas/arm/bfloat16-directive.s: New test.
Is it ok for trunk?
Regards,
Mihail
Hi,
This patch is part of a series that adds support for Armv8.6-A
(Matrix Multiply and BFloat16 extensions).
This patch contains some general refactoring of the atof_ieee
function, exposing a function that allows a higher level of control
over the format of IEEE-like floating point numbers.
This has been done in order to be able to add a directive for assembling
floating point literals in the bfloat16 format in the following patches.
Committed on behalf of Mihail Ionescu.
Tested on arm-none-eabi, arm-none-linux-gnueabihf, aarch64-none-elf
and aarch64-none-linux-gnuwith no issues.
gas/ChangeLog:
2019-10-21 Mihail Ionescu <mihail.ionescu@arm.com>
2019-10-21 Barnaby Wilks <barnaby.wilks@arm.com>
* as.h (atof_ieee_detail): Add prototype for atof_ieee_detail function.
(atof_ieee): Move some code into the atof_ieee_detail function.
(atof_ieee_detail): Add function that provides a higher level of control over generating
IEEE-like numbers.
Is it ok for trunk?
Regards,
Mihail
Hi,
This patch is part of a series that adds support for Armv8.6-A
(Matrix Multiply and BFloat16 extensions) to binutils.
This patch introduces BFloat16 instructions to the arm backend.
The following BFloat16 instructions are added: vdot, vfma{l/t},
vmmla, vfmal{t/b}, vcvt, vcvt{t/b}.
gas/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-arm.c (arm_archs): Add armv8.6-a option.
(cpu_arch_ver): Add TAG_CPU_ARCH_V8 tag for Armv8.6-a.
* doc/c-arm.texi (-march): New armv8.6-a arch.
* config/tc-arm.c (arm_ext_bf16): New feature set.
(enum neon_el_type): Add NT_bfloat value.
(B_MNEM_vfmat, B_MNEM_vfmab): New bfloat16 encoder
helpers.
(BAD_BF16): New message.
(parse_neon_type): Add bf16 type specifier.
(enum neon_type_mask): Add N_BF16 type.
(type_chk_of_el_type): Account for NT_bfloat.
(el_type_of_type_chk): Account for N_BF16.
(neon_three_args): Split out from neon_three_same.
(neon_three_same): Part split out into neon_three_args.
(CVT_FLAVOUR_VAR): Add bf16_f32 cvt flavour.
(do_neon_cvt_1): Account for vcvt.bf16.f32.
(do_bfloat_vmla): New.
(do_mve_vfma): New function to deal with the mnemonic clash between the BF16
vfmat and the MVE vfma in a VPT block with a 't'rue condition.
(do_neon_cvttb_1): Account for vcvt{t,b}.bf16.f32.
(do_vdot): New
(do_vmmla): New
(insns): Add vdot and vmmla mnemonics.
(arm_extensions): Add "bf16" extension.
* doc/c-arm.texi: Document "bf16" extension.
* testsuite/gas/arm/attr-march-armv8_6-a.d: New test.
* testsuite/gas/arm/bfloat16-bad.d: New test.
* testsuite/gas/arm/bfloat16-bad.l: New test.
* testsuite/gas/arm/bfloat16-bad.s: New test.
* testsuite/gas/arm/bfloat16-cmdline-bad-2.d: New test.
* testsuite/gas/arm/bfloat16-cmdline-bad-3.d: New test.
* testsuite/gas/arm/bfloat16-cmdline-bad.d: New test.
* testsuite/gas/arm/bfloat16-neon.s: New test.
* testsuite/gas/arm/bfloat16-non-neon.s: New test.
* testsuite/gas/arm/bfloat16-thumb-bad.d: New test.
* testsuite/gas/arm/bfloat16-thumb-bad.l: New test.
* testsuite/gas/arm/bfloat16-thumb.d: New test.
* testsuite/gas/arm/bfloat16-vfp.d: New test.
* testsuite/gas/arm/bfloat16.d: New test.
* testsuite/gas/arm/bfloat16.s: New test.
include/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/arm.h (ARM_EXT2_V8_6A, ARM_AEXT2_V8_6A,
ARM_ARCH_V8_6A): New.
* opcode/arm.h (ARM_EXT2_BF16): New feature macro.
(ARM_AEXT2_V8_6A): Include above macro in definition.
opcodes/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
* arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
Armv8.6-A.
(coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
(neon_opcodes): Add bfloat SIMD instructions.
(print_insn_coprocessor): Add new control character %b to print
condition code without checking cp_num.
(print_insn_neon): Account for BFloat16 instructions that have no
special top-byte handling.
Regression tested on arm-none-eabi.
Is it ok for trunk?
Regards,
Mihail
Hi,
This patch is part of a series that adds support for Armv8.6-A
(Matrix Multiply and BFloat16 extensions) to binutils.
This patch introduces the following BFloat16 instructions to the
aarch64 backend: bfdot, bfmmla, bfcvt, bfcvtnt, bfmlal[t/b],
bfcvtn2.
Committed on behalf of Mihail Ionescu.
gas/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (vectype_to_qualifier): Special case the
S_2H operand qualifier.
* doc/c-aarch64.texi: Document bf16 and bf16mmla4 extensions.
* testsuite/gas/aarch64/bfloat16.d: New test.
* testsuite/gas/aarch64/bfloat16.s: New test.
* testsuite/gas/aarch64/illegal-bfloat16.d: New test.
* testsuite/gas/aarch64/illegal-bfloat16.l: New test.
* testsuite/gas/aarch64/illegal-bfloat16.s: New test.
* testsuite/gas/aarch64/sve-bfloat-movprfx.s: New test.
* testsuite/gas/aarch64/sve-bfloat-movprfx.d: New test.
include/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_BFLOAT16): New feature macros.
(AARCH64_ARCH_V8_6): Include BFloat16 feature macros.
(enum aarch64_opnd_qualifier): Introduce new operand qualifier
AARCH64_OPND_QLF_S_2H.
(enum aarch64_insn_class): Introduce new class "bfloat16".
(BFLOAT16_SVE_INSNC): New feature set for bfloat16
instructions to support the movprfx constraint.
opcodes/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
in reglane special case.
* aarch64-dis-2.c (aarch64_opcode_lookup_1,
aarch64_find_next_opcode): Account for new instructions.
* aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
in reglane special case.
* aarch64-opc.c (struct operand_qualifier_data): Add data for
new AARCH64_OPND_QLF_S_2H qualifier.
* aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
(aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve,
aarch64_feature_bfloat16_bfmmla4): New feature sets.
(BFLOAT_SVE, BFLOAT): New feature set macros.
(BFLOAT_SVE_INSN, BFLOAT_BFMMLA4_INSN, BFLOAT_INSN): New macros
to define BFloat16 instructions.
(aarch64_opcode_table): Define new instructions bfdot,
bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
bfcvtn2, bfcvt.
Regression tested on aarch64-elf.
Is it ok for trunk?
Regards,
Mihail
Hi,
This patch is part of a series that adds support for Armv8.6-A
to binutils.
This first patch adds the Armv8.6-A flag to binutils.
No instructions are behind it at the moment.
Commited on behalf of Mihail Ionescu.
gas/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (armv8.6-a): New arch.
* doc/c-aarch64.texi (armv8.6-a): Document new arch.
include/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_V8_6): New.
(AARCH64_ARCH_V8_6): New.
opcodes/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-tbl.h (ARMV8_6): New macro.
Is it ok for trunk?
Regards,
Mihail
As the comments (here: almost, in the opcode table: fully) correctly
state - all register operands except MONITOR's address one are fixed
at 32 bit size. Don't print 64-bit registers there.
Also adjust x86-64-suffix.d's name such that it wouldn't be identical to
x86-64-rep-suffix.d's, but instead resemble that of its sibling
x86-64-suffix-intel.d.
Alter the sequence of conditions evaluated, without affecting the
overall result. This is going to help subsequent changes (and as a nice
side effect also slightly reduces overall indentation depth).
While doing this take the liberty of simplifying the calculation of the
operand index of the register operand in ShortForm handling.
If the extension is not found in the context sensitive table, the legacy
tables are still checked as a fallback. This is particularly useful for
Armv8.1-M as it enables the use of '.arch_extension' with the 'mve' and
'mve.fp' extensions which are not part of the legacy table.
* config/tc-arm.c (selected_ctx_ext_table) New static variable.
(arm_parse_arch): Set context sensitive extension table based on the
chosen base architecture.
(s_arm_arch_extension): Change to lookup extensions in the new context
sensitive tables.
* gas/testsuite/gas/arm/mve-ext.s: New.
* gas/testsuite/gas/arm/mve-ext.d: New.
* gas/testsuite/gas/arm/mvefp-ext.s: New.
* gas/testsuite/gas/arm/mvefp-ext.d: New.
This is a shorthand for the immediate argument being 0, as described here:
https://developer.arm.com/docs/ddi0596/latest/base-instructions-alphabetic-order/ldraa-ldrab-load-register-with-pointer-authentication
This is because the instructions still have a use with an immediate
argument of 0, unlike loads without the PAC functionality. Currently,
the mnemonics are
LDRAA Xt, [Xn, #<simm10>]!
LDRAB Xt, [Xn, #<simm10>]!
After this patch they become
LDRAA Xt, [Xn {, #<simm10>}]!
LDRAB Xt, [Xn {, #<simm10>}]!
gas * config/tc-aarch64.c (parse_address_main): Accept the omission of
the immediate argument for ldraa and ldrab as a shorthand for the
immediate being 0.
* testsuite/gas/aarch64/ldraa-ldrab-no-offset.d: New test.
* testsuite/gas/aarch64/ldraa-ldrab-no-offset.s: New test.
* testsuite/gas/aarch64/illegal-ldraa.s: Modified to accept the
writeback form with no offset.
* testsuite/gas/aarch64/illegal-ldraa.s: Removed missing offset
error.
opcodes * aarch64-opc.c (print_immediate_offset_address): Don't print the
immediate for the writeback form of ldraa/ldrab if it is 0.
* aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
* aarch64-opc-2.c: Regenerated.
Prior to changing the logic in the assembler install tests to make sure
the present defaulting of operand sizes won't get broken. There are a
few anomalies pointed out by this:
- arithmetic insns (add, sub, etc) allow defaulting when their immediate
fits in (signed) 8 bits, but they fail to assemble with larger values,
- mov, other than arithmetic insns, doesn't allow any defaulting,
- movsx/movzx default to byte sources (in AT&T mode), and their special
casing needs to be adjusted first
- bt and friends allow defaulting, while shl and friends don't,
- ambiguous AVX and AVX512 insns don't allow defaulting.
This should ultimately all become consistent (perhaps with the exception
some of the SIMD insns); respective tests will be added to the test
cases here as the issues get addressed.
The flag is used to indicate opcodes which can be switched between byte
and word/dword/qword forms (in a "canonical" way). Obviously it's quite
odd then to see it on insns not allowing for byte operands in the first
place. As a result the opcode bytes need to be adjusted accordingly,
which includes comparisons done in optimize_encoding().
To make re-introduction of such issues less likely have i386-gen
diagnose it (in a generally non-fatal way for now).
If we happen to get the fixed and variable parts of the advance_loc
in different frags, bad things happen when subtracting one from a
fr_fix of zero.
PR 25125
* dw2gencfi.c (output_cfi_insn): Don't allow DW_CFA_advance_loc4
to be placed in a different frag to the rs_cfa.
These can be generated when multiple cfi directives are emitted for an
instruction and the insn frag is closed off between directives, as
happens when listings are enabled. No doubt the advance_loc of zero
could be avoided by backtracking over frags in dw2gencfi.c before
calling cfi_add_advance_loc, but that seems like more work than
cleaning up afterwards as this patch does.
Noticed when looking at the testcase in PR25125.
PR 25125
* dw2gencfi.c (output_cfi_insn): Don't output DW_CFA_advance_loc+0.
* ehopt.c (eh_frame_estimate_size_before_relax): Return -1 for
an advance_loc of zero.
(eh_frame_relax_frag): Translate fr_subtype of 7 to size -1.
(eh_frame_convert_frag): Handle fr_subtype of 7. Abort on
unexpected fr_subtype.
The patch I made for PR12049 didn't test for a "negative" branch
properly. "if (target < address)" ought to have been
"if (target < address + fragP->fr_fix)". Rather than making that
change, this patch adds fragP->fr_fix into address earlier. The patch
also avoids running into a bad interaction with the m68k
md_prepare_relax_scan by returning zero growth immediately, since the
adjusted target expression would result in a zero "aim".
PR gas/25125
PR gas/12049
* write.c (relax_frag): Correct calculation of delta for
positive branches where "stretch" would make the branch
negative. Return zero immediately in that case. Correct
TC_PCREL_ADJUST comment.
Not much to see here, just reduce the number of calls to S_GET_VALUE
and symbol_symbolS in the comparison functions.
* config/tc-xtensa.c (xg_order_trampoline_chain_entry): Don't
call S_GET_VALUE multiple times for a symbol. Rearrange code
so it is obvious what is the primary sort key.
(xg_order_trampoline_chain): Similarly.
Also fixes m68hc1x printf arguments which would have bombed when
compiling on a 32-bit host with --enable-64-bit-bfd.
bfd/
PR 24955
* elf32-arm.c (set_cmse_veneer_addr_from_implib): Use bfd_malloc
rather than xmalloc.
* elf32-m68hc1x.c (reloc_warning): New function.
(elf32_m68hc11_relocate_section): Use it here. Cast bfd_vma values
corresponding to %lx in format strings.
* elf32-nds32.c (nds32_insertion_sort): Use a stack temporary.
gas/
* config/tc-nds32.c (nds32_set_section_relocs): Use relocs and n
parameters rather than equivalent sec->orelocation and
sec->reloc_count. Don't sort for n <= 1. Tidy.
PR 25041
opcodes * avr-dis.c (avr_operand): Fix construction of address for lds/sts
instructions.
gas * testsuite/gas/avr/pr25041.s: New test.
* testsuite/gas/avr/pr25041.d: New test driver.
So far z15 was identified as arch13. After the machine has been
announced we can now add the real name.
gas/ChangeLog:
2019-10-08 Andreas Krebbel <krebbel@linux.ibm.com>
* config/tc-s390.c (s390_parse_cpu): Add z15 as alternate CPU
name.
* doc/as.texi: Add z15 to CPU string list.
* doc/c-s390.texi: Likewise.
opcodes/ChangeLog:
2019-10-08 Andreas Krebbel <krebbel@linux.ibm.com>
* s390-mkopc.c (main): Enable z15 as CPU string in the opcode
table.
This functionality will generate a new GNU object attribute for the "data region"
has been added. This object attribute is used
mark whether the compiler has generated code assuming that data could be in the
upper or lower memory regions.
Code which assumes data is always in the lower memory region is incompatible
with code which uses the full memory range for data.
The patch also adds a new assembler directive ".mspabi_attribute" to handle the
existing MSPABI object attributes. GCC will now emit both .gnu_attribute and
.mspabi_attribute directives to indicate what options the source file was
compiled with.
The assembler will now check the values set in these directives against the
options that the it has been invoked with. If there is a discrepancy, the
assembler will exit with an error.
bfd * elf32-msp430.c (elf32_msp430_merge_mspabi_attributes): Rename to..
(elf32_msp430_merge_msp430_attributes): Add support for merging the GNU
object attribute for data region.
binutils* readelf.c (display_msp430_gnu_attribute): New.
(process_arch_specific): Use msp430 specific handler for GNU
attributes.
gas * config/tc-msp430.c (md_parse_option): Set lower_data_region_only to
FALSE if the data region is set to "upper", "either" or "none".
(msp430_object_attribute): New.
(md_pseudo_table): Handle .mspabi_attribute and .gnu_attribute.
(msp430_md_end): Replace hard-coded attribute values with enums.
Handle data region object attribute.
* doc/as.texi: Document MSP430 Data Region object attribute.
* doc/c-msp430.texi: Document the .mspabi_attribute directive.
* testsuite/gas/msp430/attr-430-small-bad.d: New test.
* testsuite/gas/msp430/attr-430-small-bad.l: New test.
* testsuite/gas/msp430/attr-430-small-good.d: New test.
* testsuite/gas/msp430/attr-430-small.s: New test.
* testsuite/gas/msp430/attr-430x-large-any-bad.d: New test.
* testsuite/gas/msp430/attr-430x-large-any-bad.l: New test.
* testsuite/gas/msp430/attr-430x-large-any-good.d: New test.
* testsuite/gas/msp430/attr-430x-large-any.s: New test.
* testsuite/gas/msp430/attr-430x-large-lower-bad.d: New test.
* testsuite/gas/msp430/attr-430x-large-lower-bad.l: New test.
* testsuite/gas/msp430/attr-430x-large-lower-good.d: New test.
* testsuite/gas/msp430/attr-430x-large-lower.s: New test.
* testsuite/gas/msp430/msp430.exp: Run new tests.
include * elf/msp430.h: Add enums for MSPABI and GNU object attribute tag names
and values.
ld * testsuite/ld-msp430-elf/attr-gnu-main.s: New test.
* testsuite/ld-msp430-elf/attr-gnu-obj.s: New test.
* testsuite/ld-msp430-elf/attr-gnu-region-lower-upper.d: New test.
* testsuite/ld-msp430-elf/attr-gnu-region-lower.d: New test.
* testsuite/ld-msp430-elf/attr-gnu-region-upper.d: New test.
* testsuite/ld-msp430-elf/msp430-elf.exp: Run new tests.
First and foremost the EsSeg attribute was misplaced for CMPSD. Then
both it and MOVSD were lacking Dword on both of their operands.
Finally string insns with multiple operands and requiring use of ES:
had the wrong operand number reported in the diagnostic.
The fix for PR12848 introduced an off by one error in the mask, this corrected
the negative overflows but not the positive overflows. As a result the
conditional branch instructions accepted a too wide positive immediate which
resulted in it corrupting the instruction during encoding.
The relocation I believe has been incorrectly named, to be consistent with the
other relocations it should have been named BRANCH21 which is why the masks for
it are confusing.
I've replaced the masks with a function out_of_range_p which should make it
harder to make such mistakes.
The mask for BL/BLX on Armv6t+ is also wrong, the extended range is 25-bits
and so the mask should be checking for 24-bits for positive overflow.
gas/ChangeLog:
PR gas/24991
* config/tc-arm.c (out_of_range_p): New.
(md_apply_fix): Use it in BFD_RELOC_THUMB_PCREL_BRANCH9,
BFD_RELOC_THUMB_PCREL_BRANCH12, BFD_RELOC_THUMB_PCREL_BRANCH20,
BFD_RELOC_THUMB_PCREL_BRANCH23, BFD_RELOC_THUMB_PCREL_BRANCH25
* testsuite/gas/arm/pr24991.d: New test.
* testsuite/gas/arm/pr24991.l: New test.
* testsuite/gas/arm/pr24991.s: New test.
This patch modifies assembler to accept the equivalent sized floating
and signless datatypes for VLDR instruction but as alias for the unsigned version.
gas/ChangeLog:
2019-09-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/tc-arm.c (do_mve_vstr_vldr_RQ): Modify function to allow float
* and signless datatypes for few cases of VLDR instruction.
* testsuite/gas/arm/mve-vldr-bad-3.l: Modify.
* testsuite/gas/arm/mve-vldr-bad-3.s: Likewise.
* testsuite/gas/arm/mve-vstrldr-1.d: Likewise.
* testsuite/gas/arm/mve-vstrldr-1.s: Likewise.
bfd/
* bfd-in.h: Move arm declaraions..
* cpu-arm.h: ..to here, new file..
* coff-arm.h: ..and here, new file..
* elf32-arm.h: ..and here, new file.
* cpu-arm.c: Include cpu-arm.h.
* coff-arm.c: Include cpu-arm.h and coff-arm.h.
* elf32-arm.c: Include cpu-arm.h and elf32-arm.h.
* pe-arm.c: Move function rename defines later.
* pe-arm-wince.c: Likewise and include sysdep.h and bfd.h early.
* bfd-in2.h: Regenerate.
gas/
* config/tc-arm.c: Include cpu-arm.h.
ld/
* emultempl/armelf.em: Include elf32-arm.h.
* emultempl/pe.em: Move func defines later and include coff-arm.h.
This one exposed a bug in tic6x gas, found with inline function
parameter type checking. struct bfd_section and struct bfd_symbol
both have a flags field, so bfd_is_com_section (symbol) compiled OK
when bfd_is_com_section was a macro but didn't special case common
symbols.
bfd/
* bfd-in.h (bfd_section_name, bfd_section_size, bfd_section_vma),
(bfd_section_lma, bfd_section_alignment, bfd_section_flags),
(bfd_section_userdata, bfd_is_com_section, discarded_section),
(bfd_get_section_limit_octets, bfd_get_section_limit): Delete macros.
* bfd.c (bfd_get_section_limit_octets, bfd_get_section_limit),
(bfd_section_list_remove, bfd_section_list_append),
(bfd_section_list_prepend, bfd_section_list_insert_after),
(bfd_section_list_insert_before, bfd_section_removed_from_list):
New inline functions.
* section.c (bfd_is_und_section, bfd_is_abs_section),
(bfd_is_ind_section, bfd_is_const_section, bfd_section_list_remove),
(bfd_section_list_append, bfd_section_list_prepend),
(bfd_section_list_insert_after, bfd_section_list_insert_before),
(bfd_section_removed_from_list): Delete macros.
(bfd_section_name, bfd_section_size, bfd_section_vma),
(bfd_section_lma, bfd_section_alignment, bfd_section_flags),
(bfd_section_userdata, bfd_is_com_section, bfd_is_und_section),
(bfd_is_abs_section, bfd_is_ind_section, bfd_is_const_section),
(discarded_section): New inline functions.
* bfd-in2.h: Regenerate.
gas/
* config/tc-tic6x.c (tc_gen_reloc): Correct common symbol check.
ld/
* emultempl/xtensaelf.em (xtensa_get_section_deps): Comment.
Use bfd_section_userdata.
(xtensa_set_section_deps): Use bfd_set_section_userdata.
* ldlang.c (lang_output_section_get): Use bfd_section_userdata.
(sort_def_symbol): Likewise, and bfd_set_section_userdata.
(init_os): Use bfd_set_section_userdata.
(print_all_symbols): Use bfd_section_userdata.
* ldlang.h (get_userdata): Delete.
Commit 21df382b91 ("x86: fold SReg{2,3}") went too far: Folding 64-bit
PUSH/POP templates into non-64-bit ones isn't correct, due to the
different operand widths, and hence suffixes permitted. Restore the
separate templates.
Add tests of PUSH/POP with q suffix and %fs/%gs operands to the
testsuite. While doing so also add PUSHF/POPF ones _without_ suffix.
These NEWS entries had been missed when the instructions were added.
gas/ChangeLog:
2019-09-19 Matthew Malcomson <matthew.malcomson@arm.com>
* NEWS: Add SVE2 and TME entries.
I get some spurious changes when running autoconf/automake for various
projects in the tree. This is likely because they were generated using
distro-patched tools last time.
I ran `autoreconf -f` in the various automake projects of the
binutils-gdb tree, and this is the result. The tools I am using have
been compiled from source, from the upstream release.
bfd/ChangeLog:
* Makefile.in: Re-generate.
* configure: Re-generate.
* doc/Makefile.in: Re-generate.
binutils/ChangeLog:
* Makefile.in: Re-generate.
* configure: Re-generate.
* doc/Makefile.in: Re-generate.
gas/ChangeLog:
* Makefile.in: Re-generate.
* configure: Re-generate.
* doc/Makefile.in: Re-generate.
gold/ChangeLog:
* testsuite/Makefile.in: Re-generate.
gprof/ChangeLog:
* Makefile.in: Re-generate.
* configure: Re-generate.
ld/ChangeLog:
* Makefile.in: Re-generate.
* configure: Re-generate.
opcodes/ChangeLog:
* Makefile.in: Re-generate.
* configure: Re-generate.
Generalize opcode arch dependencies so that we can support the
overlapping B extension Zb* subsets.
2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
gas/
* config/tc-riscv.c (riscv_multi_subset_supports): Handle
insn_class enum rather than subset char string.
(riscv_ip): Update call to riscv_multi_subset_supports.
include/
* opcode/riscv.h (riscv_insn_class): New enum.
* opcode/riscv.h (struct riscv_opcode): Change
subset field to insn_class field.
opcodes/
* riscv-opc.c (riscv_opcodes): Change subset field
to insn_class field for all instructions.
(riscv_insn_types): Likewise.
This patch adds support for MVE VCTP instruction in assembler.
gas ChangeLog:
2019-09-10 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/tc-arm.c (M_MNEM_vctp): Add new Mnemonic.
(do_mve_vctp): Add function to encode VCTP instruction.
* testsuite/gas/arm/mve-vctp-bad.d: New test.
* testsuite/gas/arm/mve-vctp-bad.l: Likewise.
* testsuite/gas/arm/mve-vctp-bad.s: Likewise.
* testsuite/gas/arm/mve-vctp.d: Likewise.
* testsuite/gas/arm/mve-vctp.s: Likewise.
This patch make changes to the assembler to encode MVE VMOV instruction "a" same as "b".
a: VMOV<c><q> <Dd>, <Dm>
b: VMOV<c><q>.F64 <Dd>, <Dm>
gas/ChangeLog:
2019-08-30 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/tc-arm.c (do_neon_mov): Modify "if" statement.
* testsuite/gas/arm/mve-vmov-bad-3.d: New test.
* testsuite/gas/arm/mve-vmov-bad-3.l: Likewise.
* testsuite/gas/arm/mve-vmov-bad-3.s: Likewise.
gas * config/tc-arm.c (parse_neon_mov): Add check to accept vector
register to both the arguments in VMOV instruction.
* testsuite/gas/arm/mve-vmov-1.d: Modify.
* testsuite/gas/arm/mve-vmov-1.s: Likewise.
* testsuite/gas/arm/mve-vorr.d: Likewise.
opcodes * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
(is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
(print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
